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2016-07-25phy: rockchip-emmc: Increase lock time allowanceDouglas Anderson
Previous PHY code waited a fixed amount of time for the DLL to lock at power on time. Unfortunately, the time for the DLL to lock is actually a bit more dynamic and can be longer if the card clock is slower. Instead of waiting a fixed 30 us, let's now dynamically wait until the lock bit gets set. We'll wait up to 10 ms which should be OK even if the card clock is at the super slow 100 kHz. On its own, this change makes the PHY power on code a little more robust. Before this change the PHY was relying on the eMMC code to make sure the PHY was only powered on when the card clock was set to at least 50 MHz before, though this reliance wasn't documented anywhere. This change will be even more useful in future changes where we actually need to be able to wait for a DLL lock at slower clock speeds. Signed-off-by: Douglas Anderson <dianders@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-07-25phy: rockchip-emmc: reindent the register definitionsBrian Norris
Some of the spacing was wrong (spaces instead of tabs), and due to longer entries added later, the columns weren't aligned. Let's get everything consistent. Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-07-25phy: rockchip-emmc: configure default output tap delayBrian Norris
The output tap delay controls helps maintain the hold requirements for eMMC. The exact value is dependent on the SoC and other factors, though it isn't really an exact science. But the default of 0 is not very good, as it doesn't give the eMMC much hold time, so let's bump up to 4 (approx 90 degree phase?). If we need to configure this any further (e.g., based on board or speed factors), we may need to consider a device tree representation. Suggested-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-07-25phy: rockchip-emmc: configure frequency range and drive impedanceShawn Lin
Signal integrity analysis has suggested we set these values. Do this in power_on(), so that they get reconfigured after suspend/resume. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-07-25phy: rockchip-emmc: give DLL some extra time to be readyShawn Lin
According to the databook, 10.2us is the max time for dll to be ready to work. However in testing, some chips need 20us for dll to be ready. This patch adds some extra margin for dllrdy to be ready, fixing our -ETIMEDOUT issues. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-07-25mmc: sdhci-brcmstb: Add driver for Broadcom BRCMSTB SoCsAl Cooper
Add SDHCI driver for Broadcom BRCMSTB SoCs. This driver works with all ARM based SoCs and the 7425, 7429 and 7435 MIPS based SoCs. The driver disables all UHS speed modes by default and relies on the Device Tree node properties to enable these modes for SoC/Board combinations that support them. Signed-off-by: Al Cooper <alcooperx@gmail.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-07-25mmc: DT: sdhci-brcmstb: Add device tree bindingsAl Cooper
The example includes the properties required to enable UHS modes. Signed-off-by: Al Cooper <alcooperx@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-07-25mmc: block: Fix tag condition with packed writesAdrian Hunter
Apparently a cut-and-paste error, 'do_data_tag' is using 'brq' for data size even though 'brq' has not been set up. Instead use blk_rq_sectors(). Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-07-25mmc: core: Disable HPI for certain Hynix eMMC cardsPratibhasagar V
Certain Hynix eMMC 4.41 cards might get broken when HPI feature is used and hence this patch disables the HPI feature for such buggy cards. As some of the other features like BKOPs/Cache/Sanitize are dependent on HPI feature, those features would also get disabled if HPI is disabled. Signed-off-by: Pratibhasagar V <pratibha@codeaurora.org> Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org> [gdavis: Forward port and cleanup] Signed-off-by: George G. Davis <george_davis@mentor.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-07-25mmc: core: Only change mode if mmc_select_bus_width() is successfulPeter Griffin
mmc_select_bus_width() returns bus width (4 or 8) on success or zero if unsupported. So only change mode if setting the bus width is successful. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-07-25mmc: Set pref erase size based on sizeGwendal Grignou
If available, eMMC stack uses HC_ERASE_GRP_SIZE as the preferred erase size. As some high capacity eMMC (64MB) reports this size to 512kB, the discard operations end up taking very long time. Improve the behaviour by instead calculating the preferred erase size based on the eMMC size. In this way the discard operations becomes faster. Signed-off-by: Gwendal Grignou <gwendal@chromium.org> [Ulf: Updated changelog and improved comment in code] Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-07-25mmc: sdhci-bcm2835: remove driverStefan Wahren
The sdhci-bcm2835 is no more needed since it has been replaced by sdhci-iproc. Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-07-25DT: bindings: remove bcm2835-sdhciStefan Wahren
The sdhci-iproc also supports bcm2835. So this binding is obsolete. Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-07-25mmc: mmc: Fix HS switch failure in mmc_select_hs400()Ziyuan Xu
To slove the issue which was found on gru board for hs400. [ 4.616946] sdhci: Secure Digital Host Controller Interface driver [ 4.623135] sdhci: Copyright(c) Pierre Ossman [ 4.722575] sdhci-pltfm: SDHCI platform and OF driver helper [ 4.730962] sdhci-arasan fe330000.sdhci: No vmmc regulator found [ 4.737444] sdhci-arasan fe330000.sdhci: No vqmmc regulator found [ 4.774930] mmc0: SDHCI controller on fe330000.sdhci [fe330000.sdhci] using ADMA [ 4.980295] mmc0: switch to high-speed from hs200 failed, err:-84 [ 4.986487] mmc0: error -84 whilst initialising MMC card We should change HS400 mode selection timing to meet JEDEC specification. The JEDEC 5.1 said that change the frequency to <= 52MHZ after HS_TIMING switch. Refer to section 6.6.2.3 "HS400" timing mode selection: Set the "Timing Interface" parameter in the HS_TIMING[185] field of the Extended CSD register to 0x1 to switch to High Speed mode and then set the clock frequency to a value not greater than 52MHZ. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-07-25mmc: mmc: fix switch timeout issue caused by jiffies precisionChaotian Jing
with CONFIG_HZ=100, the precision of jiffies is 10ms, and the generic_cmd6_time of some card is also 10ms. then, may be current time is only 5ms, but already timed out caused by jiffies precision. Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-07-25mmc: mmc: do not use CMD13 to get status after speed mode switchChaotian Jing
Per JEDEC spec, it is not recommended to use CMD13 to get card status after speed mode switch. below are two reason about this: 1. CMD13 cannot be guaranteed due to the asynchronous operation. Therefore it is not recommended to use CMD13 to check busy completion of the timing change indication. 2. After switch to HS200, CMD13 will get response of 0x800, and even the busy signal gets de-asserted, the response of CMD13 is aslo 0x800. Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-07-25mmc: mmc: Use ->card_busy() to detect busy cards in __mmc_switch()Chaotian Jing
Some MMC hosts do not support MMC_CAP_WAIT_WHILE_BUSY, but implements the ->card_busy() callback. In such cases, extend __mmc_switch() to use this method to check card status after switch command. Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-07-25mmc: sdhci: Fix sdhci_card_busy()Adrian Hunter
host->card_busy() was introduced for SD voltage switching which checks all 4 data lines. Increasingly, host->card_busy is being used to poll the the busy signal which is only data line 0 (DAT[0]). The current logic in sdhci_card_busy() does not work in that case because it returns false if any of the data lines is high. It also ignores possibilities: - data lines 1-3 are not connected and could show at any level - data lines 1-2 can be used by SDIO for other purposes According to the SD specification, it is OK to check any of the data lines for voltage switching, so change to use DAT[0] only. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-07-25mmc: tmio: make a cast explicitWolfram Sang
Sparse complains about the implicit cast. Making it explicit is indeed better coding style. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-07-25mmc: sdhci-of-arasan: implement enhanced strobe callbackShawn Lin
Currently sdhci-arasan 5.1 can support enhanced strobe function, and we now limit it just for "arasan,sdhci-5.1". Add mmc-hs400-enhanced-strobe in DT to enable the function if we're sure our controller can support it. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-07-25mmc: debugfs: add HS400 enhanced strobe descriptionShawn Lin
We introduce HS400 with enhanced strobe function, so we need to add it for debug show. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: Douglas Anderson <dianders@chromium.org> Tested-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-07-25mmc: core: implement enhanced strobe supportShawn Lin
Controllers use data strobe line to latch data from devices under hs400 mode, but not for cmd line. So since emmc 5.1, JEDEC introduces enhanced strobe mode for latching cmd response from emmc devices to host controllers. This new feature is optional, so it depends both on device's cap and host's cap to decide whether to use it or not. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Douglas Anderson <dianders@chromium.org> Tested-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-07-25mmc: core: add mmc-hs400-enhanced-strobe supportShawn Lin
This patch introduce mmc-hs400-enhanced-strobe for platforms which want to enable enhanced strobe function from DT if the mmc host controller claims to support enhanced strobe. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-07-25Documentation: mmc: add mmc-hs400-enhanced-strobeShawn Lin
mmc-hs400-enhanced-strobe is used to claim that the host can support hs400 mode with enhanced strobe introduced by emmc 5.1 spec. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-07-25MAINTAINERS: Add file patterns for mmc device tree bindingsGeert Uytterhoeven
Submitters of device tree binding documentation may forget to CC the subsystem maintainer if this is missing. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-07-25mmc: sdhci: fix wakeup configurationLudovic Desroches
Activating wakeup event is not enough to get a wakeup signal. The corresponding events have to be enabled in the Interrupt Status Enable Register too. It follows the specification and is needed at least by sdhci-of-at91. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-07-25mmc: block: correct 4KB alignment checkYuan, Juntao
In sectors alignment check, brq->data.blocks means sectors of the previous mqrq since data.blocks for mqrq_cur hasn't been updated yet. data.blocks will be updated later in mmc_blk_packed_hdr_wrq_prep or mmc_blk_rw_rq_prep. static int mmc_blk_issue_rw_rq(struct mmc_queue *mq, ...... ...... struct mmc_blk_request *brq = &mq->mqrq_cur->brq; Signed-off-by: Yuan Juntao <juntao.yuan@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-07-25mmc: sdhci: remove comment regarding timeout during tuningSimon Horman
Since commit 7ce45e950624 ("mmc: sdhci: SD tuning is broken for some controllers") sdhci_execute_tuning() no longer includes a timeout in its loop counter(s) so remove portion of the comment regarding this. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-07-25mmc: sh_mobile_sdhi: properly document R-Car versionsWolfram Sang
Replace hardcoded values with meaningful names and document what we know. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-07-25mfd: cros_ec: Add EC_PWM function definitionsBrian Norris
The EC_CMD_PWM_{GET,SET}_DUTY commands allow us to control a PWM that is attached to the EC, rather than the main host SoC. The API provides functionality-based (e.g., keyboard light, backlight) or index-based addressing of the PWM(s). Duty cycles are represented by a 16-bit value, where 0 maps to 0% duty cycle and U16_MAX maps to 100%. The period cannot be controlled. This command set is more generic than, e.g., EC_CMD_PWM_{GET,SET}_KEYBOARD_BACKLIGHT and could possibly used to replace it on future products. Let's update the command header to include the definitions. Signed-off-by: Brian Norris <briannorris@chromium.org> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2016-07-25mfd: cros_ec: Add cros_ec_cmd_xfer_status() helperTomeu Vizoso
So that callers of cros_ec_cmd_xfer() don't have to repeat boilerplate code when checking for errors from the EC side. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: Benson Leung <bleung@chromium.org> Signed-off-by: Brian Norris <briannorris@chromium.org> Acked-by: Lee Jones <lee.jones@linaro.org> Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2016-07-25binfmt_flat: use proper user space accessors with relocs processing codeNicolas Pitre
Relocs are fixed up in place in user space memory. The appropriate accessors are required for this code to work with an active MMU. The architecture specific handlers flat_get_addr_from_rp() and flat_put_addr_at_rp() for ARM and M68K are adjusted with separate patches. SuperH and Xtensa are left out as they doesn't implement __get_user_unaligned() and __put_user_unaligned() yet. The other architectures that use BFLT don't have any MMU. Signed-off-by: Nicolas Pitre <nico@linaro.org> Reviewed-by: Greg Ungerer <gerg@linux-m68k.org> Signed-off-by: Greg Ungerer <gerg@linux-m68k.org>
2016-07-25binfmt_flat: clean up create_flat_tables() and stack accessesNicolas Pitre
In addition to better code clarity, this brings proper usage of user memory accessors everywhere the stack is touched. This is essential for making this work on MMU systems. Signed-off-by: Nicolas Pitre <nico@linaro.org> Reviewed-by: Greg Ungerer <gerg@linux-m68k.org> Signed-off-by: Greg Ungerer <gerg@linux-m68k.org>
2016-07-25binfmt_flat: use generic transfer_args_to_stack()Nicolas Pitre
This gets rid of the rather ugly, open coded and suboptimal copy code. Signed-off-by: Nicolas Pitre <nico@linaro.org> Reviewed-by: Greg Ungerer <gerg@linux-m68k.org> Signed-off-by: Greg Ungerer <gerg@linux-m68k.org>
2016-07-25elf_fdpic_transfer_args_to_stack(): make it genericNicolas Pitre
This copying of arguments and environment is common to both NOMMU binary formats we support. Let's make the elf_fdpic version available to the flat format as well. While at it, improve the code a bit not to copy below the actual data area. Signed-off-by: Nicolas Pitre <nico@linaro.org> Reviewed-by: Greg Ungerer <gerg@linux-m68k.org> Signed-off-by: Greg Ungerer <gerg@linux-m68k.org>
2016-07-25binfmt_flat: prevent kernel dammage from corrupted executable headersNicolas Pitre
Signed-off-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Greg Ungerer <gerg@linux-m68k.org>
2016-07-25binfmt_flat: convert printk invocations to their modern formNicolas Pitre
Signed-off-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Greg Ungerer <gerg@linux-m68k.org>
2016-07-25binfmt_flat: assorted cleanupsNicolas Pitre
Remove excessive casts, do some code grouping, fix most important checkpatch.pl complaints, etc. No functional changes. Signed-off-by: Nicolas Pitre <nico@linaro.org> Reviewed-by: Greg Ungerer <gerg@linux-m68k.org> Signed-off-by: Greg Ungerer <gerg@linux-m68k.org>
2016-07-25drm/i915/gen9: Add WaInPlaceDecompressionHangMika Kuoppala
Add this workaround to prevent hang when in place compression is used. References: HSD#2135774 Cc: stable@vger.kernel.org Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com> Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> (cherry picked from commit 4ba9c1f7c7b8ca8c1d77f65d408e589dc87b9a2d) Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2016-07-25drm/i915/guc: Revert "drm/i915/guc: enable GuC loading & submission by default"Rodrigo Vivi
This reverts commit 041824ee25cfc535ba2d9a22c217df735ea2471e. We have latency issues that might impact the performance: #96606. and hangs and loading issues on resume after S4: #96526. This is also blocking a platform milestone so let's disable this for now while we make sure we don't have any more loading issue, or related basic hangs and it pass BAT for real in all platofmrs. In case BAT is wrong let's first fix BAT before re-enable it here. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96606 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96526 Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Dave Gordon <david.s.gordon@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Christophe Prigent <christophe.prigent@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1468884477-30086-1-git-send-email-rodrigo.vivi@intel.com (cherry picked from commit fe993bc9582ff23c9a81414acdfed8e55478e456) [danvet: Drop cc: stable since this is for 4.8 only.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2016-07-25drm/i915/bxt: Fix inadvertent CPU snooping due to incorrect MOCS configImre Deak
Setting a write-back cache policy in the MOCS entry definition also implies snooping, which has a considerable overhead. This is unexpected for a few reasons: - From user-space's point of view since it didn't want a coherent surface (it didn't set the buffer as such via the set caching IOCTL). - There is a separate MOCS entry field for snooping (which we never set). - This MOCS table is about caching in (e)LLC and there is no (e)LLC on BXT. There is a separate table for L3 cache control. Considering the above the current behavior of snooping looks like an unintentional side-effect of the WB setting. Changing it to be LLC-UC gets rid of the snooping without any ill-effects. For a coherent surface the application would use a separate MOCS entry at index 1 and call the set caching IOCTL to setup the PTE entries for the corresponding buffer to be snooped. In the future we could also add a new MOCS entry for coherent surfaces. This resulted in 70% improvement in synthetic texturing benchmarks. Kudos to Valtteri Rantala, Eero Tamminen and Michael T Frederick and Ville who helped to narrow the source of problem to the kernel and to the snooping behaviour in particular. With a follow-up change to adjust the 3rd entry value igt/gem_mocs_settings is passing after this change. v2: - Rebase on v2 of patch 1/2. v3: - Set the entry as LLC uncached instead of PTE-passthrough. This way we also keep snooping disabled, but we also make the cacheability/ coherency setting indepent of the PTE which is managed by the kernel. (Chris) CC: Rong R Yang <rong.r.yang@intel.com> CC: Yakui Zhao <yakui.zhao@intel.com> CC: Valtteri Rantala <valtteri.rantala@intel.com> CC: Eero Tamminen <eero.t.tamminen@intel.com> CC: Michael T Frederick <michael.t.frederick@intel.com> CC: Ville Syrjälä <ville.syrjala@linux.intel.com> CC: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Imre Deak <imre.deak@intel.com> Acked-by: Zhao Yakui <yakui.zhao@intel.com> Tested-by: Rong R Yang <rong.r.yang@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1467380406-11954-3-git-send-email-imre.deak@intel.com (cherry picked from commit 6bee14ed1e1136d700e5290c080e1145982ce43e) Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2016-07-25drm/i915/gen9: Clean up MOCS table definitionsImre Deak
Use named struct initializers for clarity. Also fix the target cache definition to reflect its role in GEN9 onwards. On GEN8 a TC value of 0 meant ELLC but on GEN9+ it means the TC and LRU controls are taken from the PTE. No functional change, igt/gem_mocs_settings still passing after this change. v2: (Chris) - Add back the hexa literals for the entries. Add note that igt/gem_mocs_settings still passes. CC: Rong R Yang <rong.r.yang@intel.com> CC: Yakui Zhao <yakui.zhao@intel.com> CC: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Imre Deak <imre.deak@intel.com> Acked-by: Zhao Yakui <yakui.zhao@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1467380406-11954-2-git-send-email-imre.deak@intel.com (cherry picked from commit e419899b7c19ef99e340e2b1ba585d82fd28c53b) Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2016-07-24Merge branch 'mlxsw-port-mirroring'David S. Miller
Jiri Pirko says: ==================== mlxsw: implement port mirroring offload This patchset introduces tc matchall classifier and its offload to Spectrum hardware. In combination with mirred action, defined port mirroring setup is offloaded by mlxsw/spectrum driver. The commands used for creating mirror ports: tc qdisc add dev eth25 handle ffff: ingress tc filter add dev eth25 parent ffff: \ matchall skip_sw \ action mirred egress mirror \ dev eth27 tc qdisc add dev eth25 handle 1: root prio tc filter add dev eth25 parent 1: \ matchall skip_sw \ action mirred egress mirror \ dev eth27 These patches contain: - Resource query implementation - Hardware port mirorring support for spectrum. - Definition of the matchall traffic classifier. - General support for hw-offloading for that classifier. - Specific spectrum implementaion for matchall offloading. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2016-07-24mlxsw: spectrum: Add support in matchall mirror TC offloadingYotam Gigi
This patch offloads port mirroring directives to hw using the matchall TC with action mirror. It includes both the implementation of the ndo_setup_tc function for the spectrum driver and the spectrum hardware offload configuration code. The hardware offload code is basically two new functions which are capable of adding and removing a new mirror ports pair. It is done using the MPAT, MPAR and SBIB registers: - A new Switch-Port Analyzer (SPAN) entry is added using MPAT to the 'to' port. - The 'to' port is bound to the SPAN entry using MPAR register. - In case of egress SPAN, the 'to' port gets a new internal shared buffer using SBIB register. In addition, a new database was added to the mlxsw_sp struct to store all the SPAN entries and their bound ports list. The number of supported SPAN entries is determined by resource query. Signed-off-by: Yotam Gigi <yotamg@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-07-24net/sched: act_mirred: Add helper inlines to access tcf_mirred info.Yotam Gigi
The helper function is_tcf_mirred_mirror helps finding whether an action struct is of type mirred and is configured to be of type mirror. Signed-off-by: Yotam Gigi <yotamg@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-07-24mlxsw: reg: Add the Monitoring Port Analyzer registerYotam Gigi
The MPAR register is used to bind ports to a SPAN entry (which was created using MPAT register) and thus mirror their traffic (ingress / egress) to a different port. Signed-off-by: Yotam Gigi <yotamg@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-07-24mlxsw: reg: Add Monitoring Port Analyzer Table registerYotam Gigi
The MPAT register is used to query and configure the Switch Port Analyzer (SPAN) table. This register is used to configure a port as a mirror output port, while after that a mirrored input port can be bound using MPAR register. Signed-off-by: Yotam Gigi <yotamg@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-07-24mlxsw: reg: Add Shared Buffer Internal Buffer registerYotam Gigi
The SBIB register configures per port buffer for internal use. This register is used to configure an egress mirror buffer on the egress port which does the mirroring. Signed-off-by: Yotam Gigi <yotamg@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-07-24net/sched: Add match-all classifier hw offloading.Yotam Gigi
Following the work that have been done on offloading classifiers like u32 and flower, now the match-all classifier hw offloading is possible. if the interface supports tc offloading. To control the offloading, two tc flags have been introduced: skip_sw and skip_hw. Typical usage: tc filter add dev eth25 parent ffff: \ matchall skip_sw \ action mirred egress mirror \ dev eth27 Signed-off-by: Yotam Gigi <yotamg@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-07-24net/sched: introduce Match-all classifierJiri Pirko
The matchall classifier matches every packet and allows the user to apply actions on it. This filter is very useful in usecases where every packet should be matched, for example, packet mirroring (SPAN) can be setup very easily using that filter. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Yotam Gigi <yotamg@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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