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2019-06-21arm64: tegra: Add ACONNECT, ADMA and AGIC nodesSameer Pujar
Add device tree nodes for the ACONNECT, ADMA and AGIC devices on Tegra186 and Tegra194. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-06-21arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and MakefileBen Ho
Add basic chip support for Mediatek 8183, include uart node with correct uart clocks, pwrap device Add clock controller nodes, include topckgen, infracfg, apmixedsys and subsystem. Signed-off-by: Ben Ho <Ben.Ho@mediatek.com> Signed-off-by: Erin Lo <erin.lo@mediatek.com> Signed-off-by: Seiya Wang <seiya.wang@mediatek.com> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Eddie Huang <eddie.huang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2019-06-21dt-bindings: pwm: Convert Allwinner PWM to a schemaMaxime Ripard
The Allwinner SoCs have a PWM controller supported in Linux, with a matching Device Tree binding. Now that we have the DT validation in place, let's convert the device tree bindings for that controller over to a YAML schemas. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-06-21ARM: dts: r8a7792: Add CMT0 and CMT1 to r8a7792Magnus Damm
Add CMT0 and CMT1 to the R-Car Gen2 V2H (r8a7792) SoC. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-21ARM: dts: iwg23s-sbc: Fix SDHI2 VccQ regulatorFabrizio Castro
SDR50 isn't working anymore because the GPIO regulator driver is using descriptors since commit d6cd33ad7102 ("regulator: gpio: Convert to use descriptors") which in turn causes the system to use the polarity of the GPIOs (as specified in the DT) for selecting the states, but the polarity specified in the DT is wrong. This patch fixes the regulator DT definition, and that fixes SDR50. Fixes: 9eb36b945b5c ("ARM: dts: iwg23s-sbc: Add uSD and eMMC support") Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-21ARM: dts: iwg20d-q7-common: Fix SDHI1 VccQ regularorFabrizio Castro
SDR50 isn't working anymore because the GPIO regulator driver is using descriptors since commit d6cd33ad7102 ("regulator: gpio: Convert to use descriptors") which in turn causes the system to use the polarity of the GPIOs (as specified in the DT) for selecting the states, but the polarity specified in the DT is wrong. This patch fixes the regulator DT definition, and that fixes SDR50. Fixes: 029efb3a03c5 ("ARM: dts: iwg20d-q7: Add SDHI1 support") Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-21ARM: dts: rza2mevb: Add input switchChris Brandt
Add support for input switch SW3 on the Renesas RZ/A2M EVB development board. Note that this uses the IRQ interrupt, as the RZ/A2 GPIO controller does not include interrupt support Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-21ARM: dts: r7s9210: Add IRQC device nodeChris Brandt
Enable support for the IRQC on RZ/A2M, which is a small front-end to the GIC. This allows to use up to 8 external interrupts with configurable sense select. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-21ARM: dts: rza2mevb: sort nodes of rza2mevb boardYoshihiro Kaneko
This patch sorts the nodes of arch/arm/boot/dts/r7s9210-rza2mevb.dts. * Sort subnodes of root ("/") node alphabetically * Sort following top-level nodes alphabetically * Sort subnodes of pinctrl alphabetically Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> [simon: rebase and sort new ehci nodes] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-21ARM: dts: renesas: Use ip=on for bootargsMagnus Damm
Convert bootargs from ip=dhcp to ip=on Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-20ARM: dts: meson: switch to the generic Ethernet PHY reset bindingsMartin Blumenstingl
The snps,reset-gpio bindings are deprecated in favour of the generic "Ethernet PHY reset" bindings. Replace snps,reset-gpio from the &ethmac node with reset-gpios in the ethernet-phy node. The old snps,reset-active-low property is now encoded directly as GPIO flag inside the reset-gpios property. snps,reset-delays-us is converted to reset-assert-us and reset-deassert-us. reset-assert-us is the second cell from snps,reset-delays-us while reset-deassert-us was the third cell. Instead of blindly copying the old values (which seems strange since they gave the PHY one second to come out of reset) over this also updates the delays based on the datasheets: - RTL8211F PHY on the Odroid-C1 and MXIII-Plus needs a 10ms assert delay (the datasheet mentions: "For a complete PHY reset, this pin must be asserted low for at least 10ms") and a 30ms deassert delay (the datasheet mentions: "Wait for a further 30ms (for internal circuits settling time) before accessing the PHY register"). The old settings used 10ms for assert and 1000ms for deassert. - IP101GR PHY on the EC-100 and MXQ needs a 10ms assert delay (the datasheet mentions: "Trst | Reset period | 10ms") and a 10ms deassert delay as well (the datasheet mentions: "Tclk_MII_rdy | MII/RMII clock output ready after reset released | 10ms")). The old settings used 10ms for assert and 1000ms for deassert. No functional changes intended. Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-06-20arm64: dts: sc9860: Update coresight DT bindingsLeo Yan
CoreSight DT bindings have been updated, thus the old compatible strings are obsolete and the drivers will report warning if DTS uses these obsolete strings. This patch switches to the new bindings for CoreSight dynamic funnel, so can dismiss warning during initialisation. Change-Id: Ifcc4394589f1307e92b113ebeda098b461fe085a Cc: Chunyan Zhang <zhang.chunyan@linaro.org> Cc: Orson Zhai <orsonzhai@gmail.com> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Chunyan Zhang <zhang.lyra@gmail.com>
2019-06-20arm64: dts: sc9836: Update coresight DT bindingsLeo Yan
CoreSight DT bindings have been updated, thus the old compatible strings are obsolete and the drivers will report warning if DTS uses these obsolete strings. This patch switches to the new bindings for CoreSight dynamic funnel, so can dismiss warning during initialisation. Change-Id: I2f7072bacf76aac0bb2fc891d5d71352d99e6ea8 Cc: Chunyan Zhang <zhang.chunyan@linaro.org> Cc: Orson Zhai <orsonzhai@gmail.com> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Chunyan Zhang <zhang.lyra@gmail.com>
2019-06-20arm64: tegra: Sort device tree nodes alphabeticallyThierry Reding
Device tree nodes without unit-address are to be sorted alphabetically. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-06-20arm64: tegra: Fix Jetson Nano GPU regulatorJon Hunter
There are a few issues with the GPU regulator defined for Jetson Nano which are: 1. The GPU regulator is a PWM based regulator and not a fixed voltage regulator. 2. The output voltages for the GPU regulator are not correct. 3. The regulator enable ramp delay is too short for the regulator and needs to be increased. 2ms should be sufficient. 4. This is the same regulator used on Jetson TX1 and so make the ramp delay and settling time the same as Jetson TX1. Cc: stable@vger.kernel.org Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Fixes: 6772cd0eacc8 ("arm64: tegra: Add NVIDIA Jetson Nano Developer Kit support") Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-06-20arm64: tegra: Update Jetson TX1 GPU regulator timingsJon Hunter
The GPU regulator enable ramp delay for Jetson TX1 is set to 1ms which not sufficient because the enable ramp delay has been measured to be greater than 1ms. Furthermore, the downstream kernels released by NVIDIA for Jetson TX1 are using a enable ramp delay 2ms and a settling delay of 160us. Update the GPU regulator enable ramp delay for Jetson TX1 to be 2ms and add a settling delay of 160us. Cc: stable@vger.kernel.org Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Fixes: 5e6b9a89afce ("arm64: tegra: Add VDD_GPU regulator to Jetson TX1") Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-06-20arm64: tegra: Fix AGIC register rangeJon Hunter
The Tegra AGIC interrupt controller is an ARM GIC400 interrupt controller. Per the ARM GIC device-tree binding, the first address region is for the GIC distributor registers and the second address region is for the GIC CPU interface registers. The address space for the distributor registers is 4kB, but currently this is incorrectly defined as 8kB for the Tegra AGIC and overlaps with the CPU interface registers. Correct the address space for the distributor to be 4kB. Cc: stable@vger.kernel.org Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Fixes: bcdbde433542 ("arm64: tegra: Add AGIC node for Tegra210") Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-06-20arm64: tegra: Add INA3221 channel info for Jetson TX2Nicolin Chen
There are four INA3221 chips on the Jetson TX2 (p3310 + p2771). And each INA3221 chip has three input channels to monitor power. So this patch adds these 12 channels to the DT of Jetson TX2, by following the DT binding of INA3221 and official documents from https://developer.nvidia.com/embedded/downloads tegra186-p3310: https://developer.nvidia.com/embedded/dlc/jetson-tx2-series-modules-oem-product-design-guide tegra186-p2771-0000: http://developer.nvidia.com/embedded/dlc/jetson-tx1-tx2-developer-kit-carrier-board-spec-20180618 Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-06-20arm64: tegra: Enable PWM on Jetson NanoThierry Reding
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-06-20dt-bindings: arm: Convert Atmel board/soc bindings to json-schemaRob Herring
Convert Atmel SoC bindings to DT schema format using json-schema. Cc: Mark Rutland <mark.rutland@arm.com> Cc: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2019-06-20ARM: dts: aspeed: Enable video engine on romulus and wtherspoonEddie James
Enable the video engine and add it's optional reserved memory region. Use 32MB for the reserved memory since the video engine could need up to two 1920x1200@32bpp source buffers. Source buffers: 2 * 1920 * 1200 * 4 = 18432000 bytes In addition, the V4L2 subsystem will allocate any number of compression buffers, each at most 1/8th the size of the source buffer. Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-06-20ARM: dts: aspeed: Add Inspur fp5280g2 BMC machineJohn Wang
The fp5280g2 is an OpenPower server platform with an ASPEED AST2500 BMC. Signed-off-by: John Wang <wangzqbj@inspur.com> Reviewed-by: Lei YU <mine260309@gmail.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-06-19arm64: dts: qcom: qcs404-evb: fix vdd_apc supplyJorge Ramirez-Ortiz
The invalid definition in the supply causes the Qualcomm's EVB-1000 and EVB-4000 not to boot. Fix the boot issue by correctly defining the supply: vdd_s3 (namely "vdd_apc") is actually connected to vph_pwr. Reported-by: Niklas Cassel <niklas.cassel@linaro.org> Tested-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
2019-06-19arm64: dts: meson: g12a: x96-max: add the Ethernet PHY interrupt lineMartin Blumenstingl
X96 Max has the PHY reset and interrupt lines are identical to the Odroid-N2: - GPIOZ_14 is the interrupt on X96 Max - GPIOZ_15 is the reset line on X96 Max Add GPIOZ_14 as PHY interrupt line on the X96 Max so we don't have to poll for the PHY status. Suggested-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-06-19arm64: dts: meson: g12b: odroid-n2: add the Ethernet PHY interrupt lineMartin Blumenstingl
The interrupt line of the RTL8211F PHY is routed to the GPIOZ_14 pad. Describe this in the device tree so the PHY framework doesn't have to poll the PHY status. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-06-19arm64: dts: meson: g12b: odroid-n2: add the Ethernet PHY reset lineMartin Blumenstingl
The reset line of the RTL8211F PHY is routed to the GPIOZ_15 pad. Describe this in the device tree so the PHY framework can bring the PHY into a known state when initializing it. GPIOZ_15 doesn't support driving the output HIGH (to take the PHY out of reset, only output LOW to reset the PHY is supported). The datasheet states it's an "3.3V input tolerant open drain (OD) output pin". Instead there's a pull-up resistor on the board to take the PHY out of reset. The GPIO itself will be set to INPUT mode to take the PHY out of reset and LOW to reset the PHY, which is achieved with the flags (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN). Acked-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-06-19arm64: dts: meson: use the generic Ethernet PHY reset GPIO bindingsMartin Blumenstingl
The snps,reset-gpio bindings are deprecated in favour of the generic "Ethernet PHY reset" bindings. Replace snps,reset-gpio from the &ethmac node with reset-gpios in the ethernet-phy node. The old snps,reset-active-low property is now encoded directly as GPIO flag inside the reset-gpios property. snps,reset-delays-us is converted to reset-assert-us and reset-deassert-us. reset-assert-us is the second cell from snps,reset-delays-us while reset-deassert-us was the third cell. Instead of blindly copying the old values (which seems strange since they gave the PHY one second to come out of reset) over this also updates the delays based on the datasheets: - the Realtek RTL8211F PHY needs a 10ms assert delay (the datasheet mentions: "For a complete PHY reset, this pin must be asserted low for at least 10ms") and a 30ms deassert delay (the datasheet mentions: "Wait for a further 30ms (for internal circuits settling time) before accessing the PHY register". This applies to the following boards: GXBB NanoPi K2, GXBB Odroid-C2, GXBB Vega S95 variants, GXBB Wetek variants, GXL P230, GXM Khadas VIM2, GXM Nexbox A1, GXM Q200, GXM RBox Pro boards. - the ICPlus IP101GR PHY needs a 10ms assert delay (the datasheet mentions: "Trst | Reset period | 10ms") and a deassert delay of 10ms as well (the datasheet mentions: "Tclk_MII_rdy | MII/RMII clock output ready after reset released | 10ms"). This applies to the GXBB Nexbox A95X board. - the Micrel KSZ9031 seems to require a 100us delay but use the same (seemingly safe) values from RTL8211F due to lack of a board to verify this. This applies to the GXBB P200 board. The GXBB P201 board is left out from this conversion because it doesn't have a dedicated PHY node (because it's not clear which PHY is used on that board). Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-06-19arm64: dts: meson: g12a: x96-max: fix the Ethernet PHY reset lineMartin Blumenstingl
The Odroid-N2 schematics show that the following pins are used for the reset and interrupt lines: - GPIOZ_14 is the PHY interrupt line - GPIOZ_15 is the PHY reset line The GPIOZ_14 and GPIOZ_15 pins are special. The datasheet describes that they are "3.3V input tolerant open drain (OD) output pins". This means the GPIO controller can drive the output LOW to reset the PHY. To release the reset it can only switch the pin to input mode. The output cannot be driven HIGH for these pins. This requires configuring the reset line as GPIO_OPEN_DRAIN because otherwise the PHY will be stuck in "reset" state (because driving the pin HIGH seems to result in the same signal as driving it LOW). The reset line works together with a pull-up resistor (R143 in the Odroid-N2 schematics). The SoC can drive GPIOZ_14 LOW to assert the PHY reset. However, since the SoC can't drive the pin HIGH (to release the reset) we switch the mode to INPUT and let the pull-up resistor take care of driving the reset line HIGH. Switch to GPIOZ_15 for the PHY reset line instead of using GPIOZ_14 (which actually is the interrupt line). Move from the "snps" specific resets to the MDIO framework's reset-gpios because only the latter honors the GPIO flags. Use the GPIO flags (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN) to match with the pull-up resistor because this will: - drive the output LOW to reset the PHY (= active low) - switch the pin to INPUT mode so the pull-up will take the PHY out of reset Fixes: 51d116557b2044 ("arm64: dts: meson-g12a-x96-max: Add Gigabit Ethernet Support") Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-06-19arm64: dts: meson: g12a: sort sdio nodes correctlyJerome Brunet
Fix sdio node order in the soc device tree Fixes: a1737347250e ("arm64: dts: meson: g12a: add SDIO controller") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-06-19ARM: dts: exynos: Add PMU interrupt affinity to Exynos4 boardsKrzysztof Kozlowski
Move SoC-specific PMU properties from exynos4.dtsi to respective SoC (4210 or 4412) so common DTSI would have only common properties. Define there also interrupt affinity to remove the boot warning message: hw perfevents: no interrupt-affinity property for /pmu, guessing. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2019-06-19ARM: dts: exynos: Add flash support to Galaxy S3 boardsSimon Shields
The Galaxy S3 boards use an aat1290 to control the flash LED. Add the relevant device tree configuration to use it. Signed-off-by: Simon Shields <simon@lineageos.org> Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@cyberdimension.org> [rebase] Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2019-06-19Merge tag 'ti-k3-soc-for-v5.3' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into arm/dt Texas Instruments K3 SoC family changes for 5.3 - Add support for the new J721e SoC, includes basic peripherals needed for booting up the device - New peripheral support added for AM654x: * TI SCI irqchip * GPIO * MCU SRAM * R5Fs * MSMC RAM * SERDES and PCIe * tag 'ti-k3-soc-for-v5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux: (26 commits) arm64: dts: ti: k3-j721e: Add the MCU SRAM node arm64: dts: ti: k3-j721e: Add interrupt controllers in wakeup domain arm64: dts: ti: k3-j721e: Add interrupt controllers in main domain arm64: dts: ti: k3-j721e-main: Add Main NavSS Interrupt controller node arm64: defconfig: Enable TI's J721E SoC platform arm64: dts: ti: Add support for J721E Common Processor Board soc: ti: Add Support for J721E SoC config option arm64: dts: ti: Add Support for J721E SoC dt-bindings: serial: 8250_omap: Add compatible for J721E UART controller dt-bindings: arm: ti: Add bindings for J721E SoC arm64: dts: ti: am654-base-board: Disable SERDES and PCIe arm64: dts: k3-am6: Add PCIe Endpoint DT node arm64: dts: k3-am6: Add PCIe Root Complex DT node arm64: dts: k3-am6: Add SERDES DT node arm64: dts: k3-am6: Add mux-controller DT node required for muxing SERDES arm64: dts: k3-am6: Add "socionext,synquacer-pre-its" property to gic_its arm64: dts: ti: k3-am65: Add MSMC RAM ranges in interconnect node arm64: dts: ti: k3-am65: Add R5F ranges in interconnect nodes arm64: dts: ti: k3-am65-mcu: Add the MCU RAM node arm64: dts: ti: k3-am65: Add MCU SRAM ranges in interconnect nodes ... Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-19Merge tag 'socfpga_dts_updates_for_v5.3' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt SoCFPGA DTS updates for v5.3 - Use the new "altr,socfpga-stmmac-a10-s10" for the EMAC controllers on Arria10/Stratix10 - Add the ltc2497 i2c entry on the Arria10 devkit - Add the EMAC OCP reset property on the Arria10 * tag 'socfpga_dts_updates_for_v5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: ARM: dts: arria10: Add EMAC OCP reset property ARM: dts: socfpga: add ltc2497 on arria10 devkit arm64: dts: stratix10: use the "altr,socfpga-stmmac-a10-s10" binding ARM: dts: socfpga: use the "altr,socfpga-stmmac-a10-s10" binding Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-19arm64: tegra: Enable CPU sleep on Jetson NanoThierry Reding
Jetson Nano implements CPU sleep via PSCI, much like any of the other Tegra X1 platforms. Enable the sleep states to allow the CPU to go into lower power states when idle. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-06-19arm64: tegra: Add ID EEPROMs on Jetson NanoThierry Reding
The Jetson Nano has two ID EEPROMs, one for the module and another for the carrier board. Add both to the device tree so that they can be read from at runtime. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-06-19arm64: tegra: Add ID EEPROM for Jetson TX2 Developer KitThierry Reding
There is an ID EEPROM on the Jetson TX2 carrier board, part of the Jetson TX2 Developer Kit, that exposes information that can be used to identify the carrier board. Add the device tree node so that operating systems can access this EEPROM. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-06-19arm64: tegra: Add ID EEPROM for Jetson TX2 moduleThierry Reding
There is an ID EEPROM in the Jetson TX2 module that stores various bits of information to indentify the module. Add the device tree node so that operating systems can access this EEPROM. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-06-19arm64: tegra: Add ID EEPROM for Jetson TX1 Developer KitThierry Reding
There is an ID EEPROM on the Jetson TX1 carrier board, part of the Jetson TX1 Developer Kit, that exposes information that can be used to identify the carrier board. Add the device tree node so that operating systems can access this EEPROM. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-06-19arm64: tegra: Add ID EEPROM for Jetson TX1 moduleThierry Reding
There is an ID EEPROM in the Jetson TX1 module that stores various bits of information to indentify the module. Add the device tree node so that operating systems can access this EEPROM. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-06-19ARM: dts: hip04: Update coresight DT bindingsLeo Yan
CoreSight DT bindings have been updated, thus the old compatible strings are obsolete and the drivers will report warning if DTS uses these obsolete strings. This patch switches to the new bindings for CoreSight dynamic funnel and static replicator, so can dismiss warning during initialisation. Cc: Wei Xu <xuwei5@hisilicon.com> Cc: Guodong Xu <guodong.xu@linaro.org> Cc: Zhangfei Gao <zhangfei.gao@linaro.org> Cc: Haojian Zhuang <haojian.zhuang@linaro.org> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Leo Yan <leo.yan@linaro.org> Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2019-06-19arm64: dts: hi3660: Add CoreSight supportWanglai Shi
This patch adds DT bindings for the CoreSight trace components on hi3660, which is used by 96boards Hikey960. Signed-off-by: Wanglai Shi <shiwanglai@hisilicon.com> Reviewed-and-tested-by: Leo Yan <leo.yan@linaro.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2019-06-19arm64: dts: hi6220: Update coresight DT bindingsLeo Yan
CoreSight DT bindings have been updated, thus the old compatible strings are obsolete and the drivers will report warning if DTS uses these obsolete strings. This patch switches to the new bindings for CoreSight dynamic funnel and static replicator, so can dismiss warning during initialisation. Cc: Wei Xu <xuwei5@hisilicon.com> Cc: Guodong Xu <guodong.xu@linaro.org> Cc: Zhangfei Gao <zhangfei.gao@linaro.org> Cc: Haojian Zhuang <haojian.zhuang@linaro.org> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Leo Yan <leo.yan@linaro.org> Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2019-06-19arm64: dts: renesas: hihope-common: Remove "label" from LEDsFabrizio Castro
Remove "label" properties from the LEDs device tree nodes, since we don't have nice labels on the PCB. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-19arm64: dts: renesas: hihope-common: Add HDMI supportFabrizio Castro
Add HDMI support to the HiHope RZ/G2[MN] mother board common dtsi. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-19arm64: dts: renesas: r8a774a1: Add HDMI encoder instanceFabrizio Castro
Add the HDMI encoder to the R8A774A1 DT in disabled state. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-19dt-bindings: display: renesas: Add r8a774a1 supportFabrizio Castro
Document RZ/G2M (R8A774A1) SoC bindings. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-19Merge tag 'samsung-dt-5.3' of ↵Olof Johansson
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt Samsung DTS ARM changes for v5.3 1. Fixes for minor warnings. 2. Enable ADC on Exynos5410 Odroid XU board. * tag 'samsung-dt-5.3' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: exynos: Add ADC node to Exynos5410 and Odroid XU ARM: dts: exynos: Raise maximum buck regulator voltages on Arndale Octa ARM: dts: exynos: Move CPU OPP tables out of SoC node on Exynos5420 Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-19Merge tag 'vexpress-updates-5.3' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/dt ARMv7 Vexpress updates for v5.3 1. Couple of updates switching to use new/updated bindings for CoreSight dynamic funnel components and NOR flash partition type 2. Disable NOR flash on Vexpress TC2 platform as it conflicts with CPU power management. This follows what we have on ARMv8 Juno platform and is required after recent commit that enabled CFI NOR FLASH in multi_v7 defconfig * tag 'vexpress-updates-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: ARM: dts: vexpress: set the right partition type for NOR flash arm: dts: vexpress-v2p-ca15_a7: disable NOR flash node by default ARM: dts: vexpress-v2p-ca15_a7: update coresight DT bindings Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-19Merge tag 'juno-updates-5.3' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/dt ARMv8 Juno updates for v5.3 Couple of updates switching to use new/updated bindings for CoreSight dynamic funnel components and NOR flash partition type * tag 'juno-updates-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: arm64: dts: juno: set the right partition type for NOR flash arm64: dts: juno: update coresight DT bindings Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-19Merge tag 'omap-for-v5.3/ti-sysc-dt-signed' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt ti-sysc dts changes for v5.3 We can now drop the custom dts property "ti,hwmods" for drivers that have the ti-sysc interconnect target module configured in dts. Let's start with a minimal changes to omap4 uart and mmc. We use omap4 as the starting point as it has runtime PM implemented and all the omap variants after that are based on it with similar clkctrl clock for the modules. More devices will be updated later on as they get tested. Note that these changes are based on the related ti-sysc driver changes. * tag 'omap-for-v5.3/ti-sysc-dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (21 commits) ARM: dts: Drop legacy custom hwmods property for omap4 mmc ARM: dts: Drop legacy custom hwmods property for omap4 uart bus: ti-sysc: Detect uarts also on omap34xx bus: ti-sysc: Do rstctrl reset handling in two phases bus: ti-sysc: Add support for disabling module without legacy mode bus: ti-sysc: Set ENAWAKEUP if available bus: ti-sysc: Handle swsup idle mode quirks bus: ti-sysc: Handle clockactivity for enable and disable bus: ti-sysc: Enable interconnect target module autoidle bit on enable bus: ti-sysc: Allow QUIRK_LEGACY_IDLE even if legacy_mode is not set bus: ti-sysc: Make OCP reset work for sysstatus and sysconfig reset bits bus: ti-sysc: Support 16-bit writes too bus: ti-sysc: Add support for missing clockdomain handling ARM: dts: dra71x: Disable usb4_tm target module ARM: dts: dra71x: Disable rtc target module ARM: dts: dra76x: Disable usb4_tm target module ARM: dts: dra76x: Disable rtc target module ARM: dts: dra76x: Update MMC2_HS200_MANUAL1 iodelay values ARM: dts: am57xx-idk: Remove support for voltage switching for SD card bus: ti-sysc: Handle devices with no control registers ... Signed-off-by: Olof Johansson <olof@lixom.net>
generated by cgit (git 2.34.1) at 2025-09-15 09:27:14 +0000