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2019-07-30drm/amd/powerplay: enable SW SMU routine support for arcturusEvan Quan
Enable arcturus SW SMU routines. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amd/powerplay: update arcturus_ppt.c/h V3Evan Quan
Arcturus ASIC specific powerplay interfaces. V2: correct SMU msg naming drop unnecessary debugs V3: rebase (Alex) Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amd/powerplay: update arcturus_ppsmc.hEvan Quan
Correct header and fix typo. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amd/powerplay: update smu11_driver_if_arcturus.hEvan Quan
It guides how driver should interface with SMU in arcturus. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amd/powerplay: add SW SMU interface for dumping pptable out (v2)Evan Quan
This is especially useful in early bring up phase. v2: disabled by default (Alex) Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amd/powerplay: add smcdpminfo table v4_6 supportEvan Quan
New smcdpminfo table used in arcturus. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdkfd: Save/restore vcc on gfx10Jay Cornwall
VCC moved out of user SGPR allocation in gfx10. It's now stored in SGPRs 106-107. Also fixes incorrect SGPR read offsets. Cc: Shaoyun Liu <shaoyun.liu@amd.com> Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: shaoyunl <shaoyun.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdkfd: Save/restore flat_scratch_lo/hi on gfx10Jay Cornwall
These moved from SGPRs in gfx9 to HWREG in gfx10. Cc: Shaoyun Liu <shaoyun.liu@amd.com> Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: shaoyunl <shaoyun.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdkfd: Fix gfx10 wave64 VGPR context restoreJay Cornwall
Copy/paste error, first 4 VGPRs are separated by 64 dwords (256 bytes). Cc: Shaoyun Liu <shaoyun.liu@amd.com> Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: shaoyunl <shaoyun.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amd/display: Support uclk switching for DCN2Nicholas Kazlauskas
[Why] We were previously forcing the uclk for every state to max and reducing the switch time to prevent uclk switching from occuring. This workaround was previously needed in order to avoid hangs + underflow under certain display configurations. Now that DC has the proper fix complete we can drop the hacks and improve power for most display configurations. [How] We still need the function pointers hooked up to grab the real uclk states from pplib. The rest of the prior hack can be reverted. The key requirements here are really just DC support, updated firmware, and support for disabling p-state support when needed in pplib/smu. When these requirements are met uclk switching works without underflow or hangs. Fixes: 02316e963a5a ("drm/amd/display: Force uclk to max for every state") Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amd/display: Embed DCN2 SOC bounding boxNicholas Kazlauskas
[Why] In order to support uclk switching on NV10 the SOC bounding box needs to be updated. [How] We currently read the constants from the gpu info FW, but supporting workarounds in DC for different versions of the FW adds additional complexity to the codebase. NV10 has been released so it's cleanest to keep the bounding box and source code in sync by embedding the bounding box like we do for other ASICs. Fixes: 02316e963a5a ("drm/amd/display: Force uclk to max for every state") Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu: fix a potential information leaking bugWang Xiayang
Coccinelle reports a path that the array "data" is never initialized. The path skips the checks in the conditional branches when either of callback functions, read_wave_vgprs and read_wave_sgprs, is not registered. Later, the uninitialized "data" array is read in the while-loop below and passed to put_user(). Fix the path by allocating the array with kcalloc(). The patch is simplier than adding a fall-back branch that explicitly calls memset(data, 0, ...). Also it does not need the multiplication 1024*sizeof(*data) as the size parameter for memset() though there is no risk of integer overflow. Signed-off-by: Wang Xiayang <xywang.sjtu@sjtu.edu.cn> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu: fix error handling in amdgpu_cs_process_fence_depChristian König
We always need to drop the ctx reference and should check for errors first and then dereference the fence pointer. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu/powerplay: provide the interface to disable uclk switch for DALKenneth Feng
provide the interface for DAL to disable uclk switch on navi10. in this case, the uclk will be fixed to maximum. this is a workaround when display configuration causes underflow issue. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amd/amdgpu/vcn_v2_0: Move VCN 2.0 specific dec ring test to vcn_v2_0Thong Thai
VCN 2.0 firmware now requires a packet start command to be sent before any other decode ring buffer command. Signed-off-by: Thong Thai <thong.thai@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu/gfx10: update golden settings for navi14Alex Deucher
Updated settings for hw team. Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amd/powerplay: implment sysfs feature status function in smuKevin Wang
1. Unified feature enable status format in sysfs 2. Rename ppfeature to pp_features to adapt other pp sysfs node name 3. this function support all asic, not asic related function. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Acked-by: Rui Huang <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amd/powerplay: move smu_feature_update_enable_state to up levelKevin Wang
this function is not ip or asic related function, so move it to top level as public api in smu. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amd/powerplay: add smu feature name supportKevin Wang
add smu_get_feature_name support in smu. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amd/powerplay: add smu message name supportKevin Wang
add smu_get_message_name support in smu. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amd/powerplay: move smu types to smu_types.hKevin Wang
move some enum type (message, feature, clock) to smu_types.h. these types is too long in amdgpu_smu.h, and not clearly. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu: Default disable GDS for compute+gfxJoseph Greathouse
Units in the GDS block default to allowing all VMIDs access to all entries. Disable shader access to the GDS, GWS, and OA blocks from all compute and gfx VMIDs by default. For compute, HWS firmware will set up the access bits for the appropriate VMID when a compute queue requires access to these blocks. The driver will handle enabling access on-demand for graphics VMIDs. Leaving VMID0 with full access because otherwise HWS cannot save or restore values during task switch. v2: Fixed code and comment styling. Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amd/amdgpu/vcn_v2_0: Mark RB commands as KMD commandsThong Thai
Sets the CMD_SOURCE bit for VCN 2.0 Decoder Ring Buffer commands. This bit was previously set by the RBC HW on older firmware. Newer firmware uses a SW RBC and this bit has to be set by the driver. Signed-off-by: Thong Thai <thong.thai@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu/display: fix the build without CONFIG_DRM_AMD_DC_DSC_SUPPORTAlex Deucher
Some code was missing the CONFIG_DRM_AMD_DC_DSC_SUPPORT guard. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu: Fix amdgpu_display_supported_domains logic.Andrey Grodzovsky
Add restriction to dissallow GTT domain if the relevant BO doesn't have USWC flag set to avoid the APU hang scenario. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu/powerplay: use proper revision id for naviAlex Deucher
The PCI revision id determines the sku. Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu: put the SMC into the proper state on reset/unloadAlex Deucher
When doing a GPU reset or unloading the driver, we need to put the SMU into the apprpriate state for the re-init after the reset or unload to reliably work. I don't think this is necessary for BACO because the SMU actually controls the BACO state to it needs to be active. For suspend (S3), the asic is put into D3 so the SMU would be powered down so I don't think we need to put the SMU into any special state. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu/powerplay: add set_mp1_state for vega12Alex Deucher
This sets the SMU into the proper state for various operations (shutdown, unload, GPU reset, etc.). Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu/powerplay: add set_mp1_state for vega10Alex Deucher
This sets the SMU into the proper state for various operations (shutdown, unload, GPU reset, etc.). Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu/powerplay: add set_mp1_state for vega20Alex Deucher
This sets the SMU into the proper state for various operations (shutdown, unload, GPU reset, etc.). Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu/powerplay: return success if set_mp1_state is not setAlex Deucher
Some asics (APUs) don't have this callback so we want to return success. Avoids spurious error messages on APUs. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu/powerplay: add a new interface to set the mp1 stateAlex Deucher
This is required for certain cases such as various GPU resets (mode1, mode2), BACO, shutdown, unload, etc. to put the SMU into the appropriate state for when the hw is re-initialized. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu: add reset_method asic callback for naviAlex Deucher
Navi uses either mode1 or baco depending on various conditions. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu: add reset_method asic callback for soc15Alex Deucher
APUs only support mode2 reset. dGPUs use either mode1 or baco depending on various conditions. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu: add reset_method asic callback for viAlex Deucher
VI always uses the legacy pci based reset. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu: add reset_method asic callback for cikAlex Deucher
CIK always uses the legacy pci based reset. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu: add reset_method asic callback for siAlex Deucher
SI always uses the legacy pci based reset. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu: add an asic callback to determine the reset methodAlex Deucher
Sometimes the driver may have to behave differently depending on the method we are using to reset the GPU. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amd/powerplay: enable SW SMU reset functionalityEvan Quan
Move SMU irq handler register to sw_init as that's totally software related. Otherwise, it will prevent SMU reset working. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amd/powerplay: fix null pointer dereference around dpm state relatesEvan Quan
DPM state relates are not supported on the new SW SMU ASICs. But still it's not OK to trigger null pointer dereference on accessing them. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amd/powerplay: minor fixes around SW SMU power and fan settingEvan Quan
Add checking for possible invalid input and null pointer. And drop redundant code. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amd/display: enable S/G for RAVEN chipShirish S
enables gpu_vm_support in dm and adds AMDGPU_GEM_DOMAIN_GTT as supported domain v2: Move BO placement logic into amdgpu_display_supported_domains v3: Use amdgpu_bo_validate_uswc in amdgpu_display_supported_domains. v4: amdgpu_bo_validate_uswc moved to sepperate patch. Signed-off-by: Shirish S <shirish.s@amd.com> Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu: Add check for USWC support for amdgpu_display_supported_domainsAndrey Grodzovsky
This verifies we don't add GTT as allowed domain for APUs when USWC is disabled. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Acked-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu: Create helper to clear AMDGPU_GEM_CREATE_CPU_GTT_USWCAndrey Grodzovsky
Move the logic to clear AMDGPU_GEM_CREATE_CPU_GTT_USWC in amdgpu_bo_do_create into standalone helper so it can be reused in other functions. v4: Switch to return bool. v5: Fix typos. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Acked-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu: Fix hard hang for S/G display BOs.Andrey Grodzovsky
HW requires for caching to be unset for scanout BO mappings when the BO placement is in GTT memory. Usually the flag to unset is passed from user mode but for FB mode this was missing. v2: Keep all BO placement logic in amdgpu_display_supported_domains Suggested-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Tested-by: Shirish S <shirish.s@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu: adding xgmi error monitoringJonathan Kim
monitor xgmi errors via mc pie status through fica registers. Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com> Reviewed-by: Kent Russell <Kent.Russell@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu: add perfmon and fica atomics for dfJonathan Kim
adding perfmon and fica atomic operations to adhere to data fabrics finite state machine requirements for indirect register access. Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com> Reviewed-by: Kent Russell <Kent.Russell@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdkfd: Remove dead code from gfx8/gfx9 trap handlersJay Cornwall
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdkfd: Replace gfx10 trap handler with correct branchJay Cornwall
Previously submitted code was taken from an incorrect branch and was non-functional. Cc: Oak Zeng <oak.zeng@amd.com> Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-By: Oak Zeng <oak.zeng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdkfd: Fix lost single step exceptions in gfx9 trap handlerJay Cornwall
If the trap is entered due to MODE.DEBUG_EN=1 and SAVECTX is raised concurrently the handler cannot identify the source of the exception. This causes the debugger to lose single step exception notification when a context save request arrives at the same time. When MODE.DEBUG_EN=1 and STATUS.HALT=0 (exception not already handled) jump to the second-level trap handler upon entering the trap. The second-level trap will set STATUS.HALT=1 and return to the shader. If SAVECTX was raised then control flow will return to the trap, which will then handle the context save request. Cc: Tony Tye <tony.tye@amd.com> Cc: Laurent Morichetti <laurent.morichetti@amd.com> Cc: Qingchuan Shi <qingchuan.shi@amd.com> Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Reviewed-by: Laurent Morichetti <laurent.morichetti@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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