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2019-06-21drm/amdgpu: bump smc firmware header version to v2 (v2)Huang Rui
This patch bumps smc firmware header version to v2 for storing soft pptable. v2: fix the typo, and add prints for v2 header Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: update smu11 driver if header for navi10 (v2)Huang Rui
This patch updates smu11 driver if header for navi10 to match 42.09.00 smu firmware. v2: clean up comments Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: enable backdoor smu fw loading (v2)Kenneth Feng
enable backdoor smu fw loading on navi10 v2: squash in define fix (Alex) Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: move bootup value before read pptable from vbiosHuang Rui
In navi10, we need read the pp_table_id from bootup value, then decide whether use load the soft pptable. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: add navi10 smc ucode init and navi10 ppt functions settingHuang Rui
This patch adds navi10 smc ucode init and ppt functions setting. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: set smu v11 funcs for navi10Huang Rui
Naiv10 also uses smu v11 functions. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: introduce the navi10 pptable implementationHuang Rui
This patch introduces the navi10 pptable implementation, so far it is already has firmware loading, pptable side loading, writing back to smc, and feature mask enabling. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: fix the mp/smuio header for navi10Huang Rui
SMU11 should use mp11 and smuio11 headers. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: update smu 11 driver if header for navi10Huang Rui
This patch updates smu 11 driver if header for navi10. UVD/VCE won't be used for navi10. Here, reverve them for vega20. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: update smu v11 ppsmc headerHuang Rui
This patch updates smu v11 ppsmc header for navi10. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: add to set navi ip blocksHuang Rui
Set the IPs for navi10 in early_init like other asics. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: add Navi10 pci idsAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdkfd: Add navi10 support to amdkfd. (v3)Philip Cox
KFD (kernel fusion driver) is the kernel driver for the compute backend for usermode compute stack. v2: squash in updates (Alex) v3: squash in rebase fixes (Alex) Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Signed-off-by: Philip Cox <Philip.Cox@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: update golden setting programming logicHawking Zhang
Since from soc15, make sure only AndMasked bit get changed when applied or_mask Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: Add navi10 kfd support for amdgpu (v3)Hawking Zhang
KFD (Kernel Fusion Driver) is the compute backend driver for AMD GPUs. v2: squash in updates (Alex) v3: fix warnings (Alex) Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Signed-off-by: Philip Cox <Philip.Cox@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: add navi10 common ip block (v3)Hawking Zhang
This adds the core SOC code for navi asics. v1: add place holder and initial basic function (Ray) v2: add new introduced functions to avoid reference NULL pointer (Hawking) v3L squash in updates (Alex) Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: avoid to use SOC15_REG_OFFSET in static array for navi10Hawking Zhang
Move to the header file. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: add gfx v10 implementation (v10)Hawking Zhang
GFX is the graphics and compute block on the GPU. v1: add initial gfx v10 implementation (Ray) v2: convert to new get_vm_pde function in emit_vm_flush (Hawking) v3: switch to new emit ib interfaces (Hawking) v4: squash in updates (Alex) v5: remove unused variables (Alex) v6: v6: some golden regs moved to vbios (Alex) v7: squash in some cleanups (Alex) v8: squash in golden settings update (Alex) v9: squash in whitespace fixes (Ernst Sjöstrand, Alex) v10: squash in GDS backup size fix and GDS/GWS/OA removal rebase fixes (Hawking) Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/mes10.1: add ip block mes10.1 (v2)Jack Xiao
MES takes over the scheduling capability of GFX and SDMA, add MES as a standalone ip. v2: squash in updates (Alex) Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/mes: enable mes on navi10 and later asicJack Xiao
When amdgpu_mes is enabled and asic family is navi10 and later asic, enable mes per device. Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/mes: add definitions of ip callback functionJack Xiao
Abstract mes ip independent function layer. Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/mes: add mes header file and definitionJack Xiao
Add dummy header file and definitions of mes. Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/mes: add amdgpu_mes driver parameterJack Xiao
amdgpu_mes, which is a driver scope parameter, is used to whether enable mes or not. MES (Micro Engine Scheduler) is the new on chip hw scheduling microcontroller. It can be used to handle queue scheduling and preemption and priorities. Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: add initial VCN2.0 support (v2)Leo Liu
VCN (Video Core Next) is the video encode/decode block. Porting over the same functions from VCN1.0 v2: squash in updates (Alex) Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: add JPEG2.0 decode ring ib testLeo Liu
Add internal register offset for registers involving in ib tests Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: add JPEG2.0 decode ring testLeo Liu
Use register from JPEG tile, the UVD tile reg won't work for JPEG Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: add VCN2.0 decode ib testLeo Liu
Add internal register offset for registers involving in ib tests Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: add VCN2.0 decode ring testLeo Liu
Add internal register offset for registers involving in ring tests Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: add Navi10 VCN firmware supportLeo Liu
Add Navi10 to VCN family Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: add initial support for sdma v5.0 (v6)Hawking Zhang
SDMA (System DMA) is a general purpose DMA engine usable by UMDs for transfers or the kernel for paging or GPUVM updates. v1: support basic funcitonalites includes rb, ib, vm, copy buffer and trap irq v2: convert to use new get_vm_pde in emit_vm_flush v3: retire amdgpu_ttm_set_active_vram_size from sdma v5 v4: retire the redundant hdp_invalidate implementation v5: squash in updates v6: some golden regs moved to vbios Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: set the default value of pa_sc_tile_steering_overrideHawking Zhang
So userspace can access it. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: add pa_sc_tile_steering_override to drm_amdgpu_info_deviceHawking Zhang
the initial/default value of pa_sc_tile_steering_override need to be exposed to user mode driver Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: disable concurrent flushes for Navi10 v2Christian König
Navi10 have a bug in the SDMA which can theoretically cause memory corruption with concurrent VMID flushes v2: explicitely check Navi10 Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/discovery: refactor ip list traversalXiaojie Yuan
for each ip, check whether it is needed by amdgpu driver, if yes, record its base addresses v2: change some DRM_INFO to DRM_DEBUG v3: remove unused variable (Alex) Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/discovery: add module param for ip discovery enablementXiaojie Yuan
to control enablement. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/discovery: stop converting the units of base addressesXiaojie Yuan
the unit is already in dword Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/discovery: update definition for struct die_headerXiaojie Yuan
Update to latest spec. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/discovery: stop taking psp header into accountXiaojie Yuan
psp will write a header to vram, but the value exposed in RCC_CONFIG_MEMSIZE does not include the memory that this header is written to. Therefore, the interpretation of the table does not need to take the psp header into account. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/discovery: fix hwid for nbioXiaojie Yuan
Properly set this. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/discovery: use hardcoded mmRCC_CONFIG_MEMSIZEXiaojie Yuan
register base offset of nbio is not known before IP Discovery table is parsed, so hardcode this value. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/discovery: add harvest info data tableXiaojie Yuan
Add support for the harvest tables. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/discovery: update definitions of table_info and binary_headerXiaojie Yuan
Use the proper definitions. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/discovery: fix calculations of some gfx infoXiaojie Yuan
fix gfx info table handling. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/discovery: add ip discovery initial supportXiaojie Yuan
The IP discovery table lists is populated by the psp at power on and includes all of the hw details on the board: - List of IPs and MMIO offsets - IP harvest details - IP configuration details v2: prefix struct and function names with 'amdgpu' v3: read table binary from vram using mmMM_INDEX and mmMM_DATA update TABLE_BINARY_MAX_SIZE to 64kb (1 TMR) add 'instance_number' field per ip info consider endianness and replace uint8/16/32_t with u8/16/32 initialize register base addresses initialize adev->gfx.config and adev->gfx.cu_info to replace gpu info fw get major and minor version using a single api don't expose internal data structures in amdgpu_discovery.h v4: RCC_CONFIG_MEMSIZE is in MB units hold mmio_idx_lock while reading ip discovery binary v5: pick out discovery.h as a cross-OS header do structure pointer cast directly consider endianness while using the member of structure convert base addresses to dword at boot up, PSP BL copies ip discovery binary from VBIOS(SPIROM) image to the top of the frame buffer (just below the reserved regions for PSP & SMU). ip discovery data table includes the collection of each ip's identification number, base addresses, version number, and harvest setting placeholder. gc data table includes gfx info structure. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: mark the partial job as preempted in mcbp unit testJack Xiao
In mcbp unit test, the test should detect the preempted job which may be a partial execution ib and mark it as preempted; so that the gfx block can correctly generate PM4 frame. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: add mcbp unit test in debugfs (v3)Jack Xiao
The MCBP unit test is used to test the functionality of MCBP. It emualtes to send preemption request and resubmit the unfinished jobs. v2: squash in fixes (Alex) v3: squash in memory leak fix (Jack) Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: program for resuming preempted ibJack Xiao
For new submission ib, CE/DE metadata should be programmed to 0; for partially execution ib, CE/DE metadata should be restored. Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/sdma: allocate CSA per sdma ringJack Xiao
Allocate CSA for the given sdma ring. Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: add ib preemption status in amdgpu_job (v2)Jack Xiao
Add ib preemption status in amdgpu_job, so that ring level function can detect preemption and program for resuming it. v2: squash in fix to restore job->preamble_status back to status value (Jack) Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: enable the static csa when mcbp enabledJack Xiao
CSA is the Context Save Area for preemption. Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit (git 2.34.1) at 2025-09-16 12:53:16 +0000