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2018-09-14ARM: dts: aspeed: quanta-q71l: Enable adc & ibt nodesPatrick Venture
This machine uses the ADC and iBT devices. Signed-off-by: Patrick Venture <venture@google.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-09-14ARM: dts: aspeed: quanta-q71l: Add four PSUsPatrick Venture
Enable the four PSUs via generic PMBUS. Signed-off-by: Patrick Venture <venture@google.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-09-14ARM: dts: aspeed: quanta-q71l: add aliases for i2cPatrick Venture
Provide aliases to each i2c bus per labels added for each PCIe slot, etc, that are downstream beyond a mux. Signed-off-by: Patrick Venture <venture@google.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-09-14ARM: dts: aspeed: Fix I2C bus warningsRob Herring
dtc has new checks for I2C buses. The ASpeed dts files have a node named 'i2c' which causes a false positive warning. As the node is a 'simple-bus', correct the node name to be 'bus' to fix the warnings. arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-bmc-opp-romulus.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-ast2500-evb.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-bmc-opp-zaius.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus Cc: Joel Stanley <joel@jms.id.au> Cc: Andrew Jeffery <andrew@aj.id.au> Cc: linux-aspeed@lists.ozlabs.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-09-13ARM: dts: bcm: Fix SPI bus warningsRob Herring
dtc has new checks for SPI buses. Fix the warnings in node names. arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dtb: Warning (spi_bus_bridge): /axi@18000000/qspi@27200: node name for SPI buses should be 'spi' arch/arm/boot/dts/bcm958525er.dtb: Warning (spi_bus_bridge): /axi/qspi@27200: node name for SPI buses should be 'spi' arch/arm/boot/dts/bcm958525xmc.dtb: Warning (spi_bus_bridge): /axi/qspi@27200: node name for SPI buses should be 'spi' arch/arm/boot/dts/bcm958622hr.dtb: Warning (spi_bus_bridge): /axi/qspi@27200: node name for SPI buses should be 'spi' arch/arm/boot/dts/bcm958625hr.dtb: Warning (spi_bus_bridge): /axi/qspi@27200: node name for SPI buses should be 'spi' arch/arm/boot/dts/bcm988312hr.dtb: Warning (spi_bus_bridge): /axi/qspi@27200: node name for SPI buses should be 'spi' Cc: Ray Jui <rjui@broadcom.com> Cc: Scott Branden <sbranden@broadcom.com> Cc: Jon Mason <jonmason@broadcom.com> Cc: bcm-kernel-feedback-list@broadcom.com Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2018-09-13arm64: dts: broadcom: Fix I2C and SPI bus warningsRob Herring
dtc has new checks for I2C and SPI buses. Fix the warnings in node names and unit-addresses. arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dtb: Warning (i2c_bus_reg): /hsls/i2c@e0000/pcf8574@20: I2C bus unit address format error, expected "27" arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dtb: Warning (i2c_bus_reg): /hsls/i2c@e0000/pcf8574@20: I2C bus unit address format error, expected "27" arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dtb: Warning (spi_bus_bridge): /hsls/ssp@180000: node name for SPI buses should be 'spi' arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dtb: Warning (spi_bus_bridge): /hsls/ssp@190000: node name for SPI buses should be 'spi' Cc: Ray Jui <rjui@broadcom.com> Cc: Scott Branden <sbranden@broadcom.com> Cc: Jon Mason <jonmason@broadcom.com> Cc: bcm-kernel-feedback-list@broadcom.com Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2018-09-13ARM: dts: qcom: ipq4019: fix space vs tab indenting inside qcom-ipq4019.dtsiJohn Crispin
There are various places inside this dtsi file where 8 spaces where used for indenting instead of tabs. Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom: ipq4019: fix PCI rangeMathias Kresin
The PCI range is invalid and PCI attached devices doen't work. Signed-off-by: Mathias Kresin <dev@kresin.me> Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom: ipq4019: fix cpu0's qcom,saw2 reg valueChristian Lamparter
while compiling an ipq4019 target, dtc will complain: regulator@b089000 unit address format error, expected "2089000" The saw0 regulator reg value seems to be copied and pasted from qcom-ipq8064.dtsi. This patch fixes the reg value to match that of the unit address which in turn silences the warning. (There is no driver for qcom,saw2 right now. So this went unnoticed) Signed-off-by: Christian Lamparter <chunkeey@gmail.com> Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom: ipq4019: add cpu operating points for cpufreq supportMatthew McClintock
This adds some operating points for cpu frequeny scaling Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom: ipq4019: use v2 of the kpss bringup mechanismMatthew McClintock
v1 was the incorrect choice here and sometimes the board would not come up properly. Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Signed-off-by: Christian Lamparter <chunkeey@gmail.com> Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom: msm8974-hammerhead: add device tree bindings for ALS / proximityBrian Masney
This patch adds device tree bindings for the tsl2772 ALS / proximity sensor for the LG Nexus 5 (hammerhead) phone. Signed-off-by: Brian Masney <masneyb@onstation.org> Signed-off-by: Jonathan Marek <jonathan@marek.ca> Acked-by: Jonathan Cameron <jonathan.cameron@huawei.com> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom: msm8974-hammerhead: add device tree bindings for mpu6515Brian Masney
This patch adds device tree bindings for the mpu6515 to the LG Nexus 5 (hammerhead) phone. Confirmed that the gyroscope / accelerometer (mpu6515), magnetometer (ak8963), and temperature / pressure (bmp280) sensors are available on the phone. Interrupts are not working properly on the ak8963 magnetometer so they are currently not configured. The bmp280 retuns temperature/pressure measurement skipped errors but will reliably work if I run: echo 1 > in_pressure_oversampling_ratio echo 1 > in_temp_oversampling_ratio Signed-off-by: Brian Masney <masneyb@onstation.org> Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom: Add led and gpio-button nodes to ipq8064 boardsSricharan R
Add the dt nodes for enabling the leds and gpio-buttons. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom: Move common nodes to ipq8064-v.1.0.dtsiSricharan R
The nodes in ipq8064-ap148.dts currently are common with boards that we will add next. So move the common data to ipq8064-v.1.0.dtsi. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom: Add sdcc nodes for ipq8064Sricharan R
The relevant data for sdcc. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom: Add pcie nodes for ipq8064Sricharan R
Adding the pcie nodes and pins. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom-msm8974: change invalid flag IRQ NONE to valid valueFrank Rowand
Change the third field of the "interrupts" property from IRQ_TYPE_NONE to the correct value. I do not have hardware documentation for these devices, so I followed a mail list suggestion to copy the flag values from the same type of node in arch/arm64/boot/dts/qcom/msm8916.dtsi Signed-off-by: Frank Rowand <frank.rowand@sony.com> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom-msm8974: use named constant for interrupt flag NONEFrank Rowand
Cosmetic change of integer value "0" in the third field of the "interrupts" property to the correct named constant. Signed-off-by: Frank Rowand <frank.rowand@sony.com> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom-msm8974: use named constant for interrupt flag LEVEL HIGHFrank Rowand
Cosmetic change of integer value "4" in the third field of the "interrupts" property to the correct named constant. Signed-off-by: Frank Rowand <frank.rowand@sony.com> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom-msm8974: use named constant for interrupt flag EDGE RISINGFrank Rowand
Cosmetic change of integer value "1" in the third field of the "interrupts" property to the correct named constant. Signed-off-by: Frank Rowand <frank.rowand@sony.com> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom-msm8974: use named constant for interrupt type GIC_SPIFrank Rowand
Cosmetic change of integer value "0" in the first field of the "interrupts" property to the correct named constant. Signed-off-by: Frank Rowand <frank.rowand@sony.com> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom-msm8974: use named constant for interrupt type GIC_PPIFrank Rowand
Cosmetic change of integer value "1" in the first field of the "interrupts" property to the correct named constant. Signed-off-by: Frank Rowand <frank.rowand@sony.com> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: msm8996: Transition smp2p and smd to mailboxBjorn Andersson
The smd and smp2p drivers now support accessing the APCS GLOBAL IPC register through the mailbox framework, so migrate the msm8996 dts to use this and remove the syscon based APCS node. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: pm8998: Add pm8998 thermal zoneMatthias Kaehlcke
The thermal zone uses spmi-temp-alarm as sensor, the trip points correspond to the PMIC thermal stages 1 and 2. The critical trip point at 125°C disables the partial PMIC shutdown at stage 2. Without an IIO input the sensor only reports a limited number of temperatures: - 37°C for temperatures below 105°C - 107°C for temperatures >= 105°C and < 125°C - 127°C for temperatures >= 125°C (the numbers correspond to a stage 1 threshold of 105°C) Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: pm8998: Add spmi-temp-alarm nodeMatthias Kaehlcke
This adds the spmi-temp-alarm node to pm8998 based on the examples in the bindings. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13dt-bindings: thermal: qcom-spmi-temp-alarm: Fix documentation of 'reg'Matthias Kaehlcke
The documentation claims that the 'reg' property consists of two values, the SPMI address and the length of the controller's registers. However the SPMI bus to which it is added specifies "#size-cells = <0>;". Remove the controller register length from the documentation of the field and the example. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: sdm845: Add dispcc nodeMatthias Kaehlcke
This adds the display clock controller node to sdm845 based on the examples in the bindings. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: sdm845: Add adsp, cdsp and slpi smp2pBjorn Andersson
Add the SMP2P nodes for the remoteproc states for adsp, cdsp and slpi. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: sdm845-mtp: Add nodes for USBDouglas Anderson
Set the various nodes to "okay" and hook up the regulators. NOTE: For now the main USB port (the one that goes out the Type C connector) is forced to host. Eventually someone will need to get the Type C detection hooked up and get this all integrated with the PMI8998 PMIC. The reason for forcing to "host" in the meantime is that this will leave us with one "host" and one "peripheral" port. In order for host mode this to work, we assume that the bootloader left things configured enough for us. Apparently the magic for that is is to do these writes on pmi8998: - pm_comm_write_byte(2, 0x1153, 0x2C, 0); - pm_comm_write_byte(2, 0x1152, 0x07, 0); - pm_comm_write_byte(2, 0x1140, 0x00, 0); - pm_comm_write_byte(2, 0x1140, 0x01, 0); Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: sdm845-mtp: Add RPMh VRM/XOB regulatorsDouglas Anderson
Add regulator devices for PMIC regulators managed via VRM and XOB RPMh accelerators. A few notes here: - Regulators are added directly to the board file. While it's true that this will mean a bunch of copy/pasting for other boards that are very similar, this is probably the right call since boards could make changes to the way these regulators are hooked up and trying to find a way to avoid duplication will result in some confusing node overrides. - Regulators that are hooked up to supply pins on the SoC are given an alias matching the name of that pin (pin name comes from the Qualcomm SoC "device specification" doc). - Other regulator labels are based on the schematic. If there is more than one logical name on the schematic for the same rail the secondary names are also listed and should be referred to as appropriate. - Regulators all default to HPM mode w/ no ability to switch modes. Future patches can switch things to LPM and possibly add dynamic load switching if we have determined there's a benefit. This should only be done for rails where we'll actually be able to take advantage of the lower power modes so we don't need to churn with lots of patches adding regulator_set_load() calls to drivers. NOTE: This patch is loosely based on one originally shared to me by David Collins. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: sdm845: Add USB-related nodesManu Gautam
This adds nodes for USB and related PHYs. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> [dianders: reworked quite a bit] Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: Add AOSS reset driver node for SDM845Sibi Sankar
This patch adds the node to support AOSS reset driver on SDM845 Signed-off-by: Sibi Sankar <sibis@codeaurora.org> [bjorn: Updated addresses to match the binding that was merged] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: msm8996: Drop modelNiklas Cassel
DTS board files should always specify model and compatible. All DTS board files that includes msm8996.dtsi already specifies model and compatible, and will thus override the model and compatible in msm8996.dtsi. Drop model from msm8916.dtsi, since it is only a source of confusion. Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: msm8916: Drop model and compatibleNiklas Cassel
DTS board files should always specify model and compatible. All DTS board files that includes msm8916.dtsi already specifies model and compatible, and will thus override the model and compatible in msm8916.dtsi. Drop model and compatible from msm8916.dtsi, since they are only a source of confusion. Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: db820c: Add qcom,apq8096 to compatible stringNiklas Cassel
Add qcom,apq8096 to compatible string. This compatible is defined in Documentation/devicetree/bindings/arm/qcom.txt and is needed for e.g. drivers/cpufreq/qcom-cpufreq-kryo.c to be probed correctly (and for drivers/cpufreq/cpufreq-dt-platdev.c to work properly). Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: Populate pm8998 with additional nodesBjorn Andersson
Add pon, coincell and rtc to the first pm8998 sid. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: msm8998: Add smp2p nodesBjorn Andersson
Add the adsp, modem and slpi smp2p nodes to msm8998. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: msm8998: Add the qfprom nodeBjorn Andersson
Add the QFPROM nvmem node to msm8998 Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: msm8998: Add firmware nodeBjorn Andersson
Add the firmware and scm nodes for msm8998 Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: msm8998: Add smem related nodesBjorn Andersson
Add reserve-memory nodes, tcsr-mutex nodes and the smem node. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: msm8998: Add pmi8998 fileBjorn Andersson
Add new dtsi file for the PMI8998, with its gpios and include all three PMICs in the MSM8998 MTP dts. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: msm8998: Add tsens and thermal-zonesBjorn Andersson
Add the two tsens instances and the thermal zones for CPUs, GPUs, battery and skin sensors. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: msm8998: Add RPM and regulators for MTPBjorn Andersson
Add nodes for RPM communication for MSM8998 and the regulator nodes for the MTP. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: Add msm8998 SoC and MTP board supportJoonwoo Park
Add initial device tree support for the Qualcomm MSM8998 SoC and MTP8998 evaluation board. Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org> Signed-off-by: Imran Khan <kimran@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> [bjorn: Restructured, removed its node and moved to SPDX headers] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: pm8998: Add adc nodeMatthias Kaehlcke
This adds the adc node to pm8998 based on the examples in the bindings. It also fixes the order of the included headers. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13dt-bindings: iio: vadc: Fix documentation of 'reg'Matthias Kaehlcke
The documentation of Qualcomm's SPMI PMIC voltage ADC claims that the 'reg' property consists of two values, the SPMI address and the length of the controller's registers. However the SPMI bus to which it is added specifies "#size-cells = <0>;". Remove the controller register length from the documentation of the field and the example. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: apq8096-db820c: Add resin nodeVinod Koul
Resin is board specific, so add the resin node in apq8096-db820c dtsi Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: apq8016-sbc: Add resin nodeVinod Koul
Resin is board specific so add the resin node in apq8016-sbc dtsi Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13arm64: dts: qcom: pm8994: Add PON nodeVinod Koul
Add PON and pwrkey as child nodes for PON driver. Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
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