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2023-07-27arm64: dts: renesas: rzg2ul-smarc: Add support for enabling MTU3Biju Das
Add support for PMOD_MTU3 macro to enable MTU3 node on RZ/G2UL SMARC EVK. The MTU3a PWM pins on PMOD0 are muxed with SPI1. Disable SPI1, when PMOD_MTU3 macro is enabled. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230727081848.100834-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-27arm64: dts: renesas: r9a07g043: Add MTU3a nodeBiju Das
Add MTU3a node to R9A07G043 (RZ/{G2UL,Five}) SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230727081848.100834-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-27ARM dts: renesas: armadillo800eva: Switch to enable-gpiosKrzysztof Kozlowski
The recommended name for enable GPIOs property in regulator-gpio is "enable-gpios". This is also required by bindings: r8a7740-armadillo800eva.dtb: regulator-vccq-sdhi0: Unevaluated properties are not allowed ('enable-gpio' was unexpected) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230726070241.103545-1-krzysztof.kozlowski@linaro.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-27arm64: zynqmp: Describe interrupts by using macrosMichal Simek
Use arm-gic.h and irq.h for interrupt description. It helps to improve readability of device tree file. Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/9d5bd17f37772be186cab17b06cc21351d36ff62.1688986332.git.michal.simek@amd.com
2023-07-26arm64: tegra: Adapt to LP855X bindings changesArtur Weber
Change underscores in ROM node names to dashes, and remove deprecated pwm-period property. Signed-off-by: Artur Weber <aweber.kernel@gmail.com> Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: Add PCIe and DP 3.3V suppliesShubhi Garg
Add the 3.3V supplies for PCIe C1 controller and Display Port controller for the NVIDIA IGX Orin platform. Signed-off-by: Shubhi Garg <shgarg@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: Add missing reset-names for Tegra HS UARTThierry Reding
The device tree bindings for the Tegra high-speed UART require the reset-names property, so add it whenever the compatible string for the serial port is overwritten. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: Remove current-speed for SBSA UARTThierry Reding
The SBSA UART device tree bindings don't define a current-speed property, so remove it. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: smaug: Remove reg-shift for high-speed UARTThierry Reding
The device tree bindings for the high-speed UART don't define a reg-shift property, so delete it. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: Remove dmas and dma-names for debug UARTThierry Reding
The debug UART doesn't support DMA and the DT bindings prohibit the use of the dmas and dma-names properties for it, so remove them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: Add 35°C trip point for Jetson Orin NX/NanoThierry Reding
It turns out that these devices can get quite hot to the touch with the standard cooling configuration, so add another trip point at 35°C along with a cooling map to help keep the system reasonably cool at very low system load. Reviewed-by: Yi-Wei Wang <yiweiw@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: Remove duplicate PCI nodesThierry Reding
The PCI nodes for Jetson Orin NX are already defined at the carrier board level, so the duplicates can be dropped at the platform level. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: Sort PCI nodes correctly on OrinThierry Reding
Recent changes to several Orin boards didn't order some device tree nodes correctly. Resort them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: Add audio support for IGX OrinMohan Kumar
Add audio support for the NVIDIA IGX Orin development kit having P3701 module with P3740 carrier board. Move the common device-tree nodes to a new file tegra234-p3701.dtsi and use this for Jetson AGX Orin and NVIDIA IGX Orin platforms Signed-off-by: Mohan Kumar <mkumard@nvidia.com> [treding@nvidia.com: properly sort nodes] Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26dt-bindings: firmware: Add support for tegra186-bpmp DRAM MRQ GSCsPeter De Schrijver
Add memory-region property to the tegra186-bpmp binding to support DRAM MRQ GSCs. Co-developed-by: Stefan Kristiansson <stefank@nvidia.com> Signed-off-by: Stefan Kristiansson <stefank@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26dt-bindings: reserved-memory: Add support for DRAM MRQ GSCsPeter De Schrijver
Add bindings for DRAM MRQ GSC support. Co-developed-by: Stefan Kristiansson <stefank@nvidia.com> Signed-off-by: Stefan Kristiansson <stefank@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26riscv: dts: starfive: jh7110: add the node and pins configuration for tdmWalker Chen
Add the tdm controller node and pins configuration of tdm for the StarFive JH7110 SoC. Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Walker Chen <walker.chen@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-07-26riscv: dts: starfive: jh7110: add dma controller nodeWalker Chen
Add the dma controller node for the Starfive JH7110 SoC. Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Walker Chen <walker.chen@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-07-26riscv: dts: starfive: Add spi node and pins configurationWilliam Qiu
Add StarFive JH7110 SPI controller node and pins configuration on VisionFive 2 board. Signed-off-by: William Qiu <william.qiu@starfivetech.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-07-26riscv: dts: starfive: Add USB dts node for JH7110Minda Chen
Add USB wrapper layer and Cadence USB3 controller dts configuration for StarFive JH7110 SoC and VisionFive2 Board. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-07-26riscv: dts: starfive: Add USB and PCIe PHY nodes for JH7110Minda Chen
Add USB and PCIe PHY dts nodes for the StarFive JH7110 SoC. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-07-26ARM: dts: samsung: exynos4412-midas: add USB connector and USB OTGKrzysztof Kozlowski
Add full description of USB-MUIC (MAX77693 MUIC) and MUIC-MHL connections, along with proper USB connector and OTG mode for DWC2 USB controller. This fixes dtc W=1 warnings: Warning (graph_child_address): /i2c-mhl/hdmi-bridge@39/ports: graph node has single child node 'port@0', #address-cells/#size-cells are not necessary Cc: Marek Szyprowski <m.szyprowski@samsung.com> Cc: replicant@osuosl.org Cc: phone-devel@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht Cc: Martin Jücker <martin.juecker@gmail.com> Cc: Henrik Grimler <henrik@grimler.se> Cc: Artur Weber <aweber.kernel@gmail.com> Tested-by: Henrik Grimler <henrik@grimler.se> Link: https://lore.kernel.org/r/20230723142417.97734-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-07-26ARM: dts: samsung: exynos5250-snow: switch i2c-arb to new child variantKrzysztof Kozlowski
Since commit e8813c15be0a ("dt-bindings: i2c: add support for 'i2c-arb' subnode") the i2c-arbitrator subnode should not have unit address. Link: https://lore.kernel.org/r/20230721133246.15752-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-07-26ARM: dts: samsung: exynos5250-snow: use 'gpios' suffix for i2c-arbKrzysztof Kozlowski
Linux drivers support both variants - gpios and gpio - but first is preferred. Link: https://lore.kernel.org/r/20230721133246.15752-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-07-25dt-bindings: thermal: tegra: Convert to json-schemaThierry Reding
Convert the Tegra thermal bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-25dt-bindings: arm: tegra: nvec: Convert to json-schemaThierry Reding
Convert the NVIDIA embedded controller bindings from the free-form text format to json-schema. Acked-by: Marc Dietrich <marvin24@gmx.de> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-25dt-bindings: clock: tegra: Document Tegra132 compatibleThierry Reding
The Tegra132 clock and reset controller is largely compatible with the version found on Tegra124 but it does have slight differences in what clocks it exposes, so a separate compatible string is needed. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-25arm64: dts: renesas: rzg2lc-smarc-som: Enable PMIC and built-in RTCBiju Das
Enable PMIC RAA215300 and the built-in RTC on the RZ/G2LC SMARC EVK. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230712151342.82690-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-25arm64: dts: renesas: rzg2lc-smarc-som: Add PHY interrupt support for ETH0Biju Das
The PHY interrupt (INT_N) pin is connected to IRQ0 for ETH0. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230712151153.81965-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-25riscv: dts: renesas: Clean up dtbs_check W=1 warning due to empty phy nodeConor Dooley
dtbs_check w/ W=1 complains: Warning (unit_address_vs_reg): /soc/ethernet@11c20000/ethernet-phy@7: node has a unit name, but no reg or ranges property Warning (avoid_unnecessary_addr_size): /soc/ethernet@11c20000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property The ethernet@11c20000 node is guarded by an `#if (!SW_ET0_EN_N)` in rzg2ul-smarc-som.dtsi, where the phy child node is added. In rzfive-smarc-som.dtsi, the ethernet node is marked disabled & the interrupt properties are deleted from the phy child node. As a result, the produced dts looks like: ethernet@11c20000 { compatible = "renesas,r9a07g043-gbeth", "renesas,rzg2l-gbeth"; /* snip */ #address-cells = <1>; #size-cells = <0>; status = "disabled"; ethernet-phy@7 { }; }; Adding a corresponding `#if (!SW_ET0_EN_N)` around the node in rzfive-smarc-som.dtsi avoids the complaint, as the empty child node is not added: ethernet@11c20000 { compatible = "renesas,r9a07g043-gbeth", "renesas,rzg2l-gbeth"; /* snip */ #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230712-squealer-walmart-9587342ddec1@wendy Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-25arm64: dts: renesas: rzg2lc-smarc: Add support for enabling MTU3Biju Das
Add support for PMOD_MTU3 macro to enable MTU3 node on RZ/G2LC SMARC EVK. The MTU3a PWM pins on PMOD0 are muxed with SPI1. Disable SPI1, when PMOD_MTU3 macro is enabled. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230707155849.86649-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-25arm64: dts: renesas: rzg2l-smarc: Add support for enabling MTU3Biju Das
Add support for PMOD_MTU3 macro to enable MTU3 node on RZ/{G2,V2}L SMARC EVK. The MTU3a PWM pins are muxed with spi1 pins and counter external input phase clock pins are muxed with scif2 pins. Disable these IPs when PMOD_MTU3 macro is enabled. Apart from this, the counter Z phase clock signal is muxed with the SDHI1 cd signal. So disable SDHI1 IP, when the counter Z phase signal is enabled. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230706153047.368993-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-25arm64: dts: renesas: Add missing space before {Krzysztof Kozlowski
Add missing whitespace between node name/label and opening {. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230705145912.293315-2-krzysztof.kozlowski@linaro.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-25ARM: dts: renesas: Add missing space before {Krzysztof Kozlowski
Add missing whitespace between node name/label and opening {. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230705145912.293315-1-krzysztof.kozlowski@linaro.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-25arm64: dts: renesas: Minor whitespace cleanup around '='Krzysztof Kozlowski
The DTS code coding style expects exactly one space before and after '=' sign. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230702185252.44462-1-krzysztof.kozlowski@linaro.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-25arm64: dts: renesas: rzg2l-smarc-som: Enable PMIC and built-in RTCBiju Das
Enable PMIC RAA215300 and the built-in RTC on the RZ/{G2L,V2L} SMARC EVK. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230623140948.384762-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-25arm64: dts: renesas: r9a09g011: Add CSI nodesFabrizio Castro
The Renesas RZ/V2M comes with 6 Clocked Serial Interface (CSI) IPs (CSI0, CSI1, CSI2, CSI3, CSI4, CSI5), but Linux is only allowed access to CSI0 and CSI4. This commit adds SoC specific device tree support for CSI0 and CSI4. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230622113341.657842-5-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-25arm64: dts: renesas: rzg2l: Fix txdv-skew-psec typosChris Paterson
It looks like txdv-skew-psec is a typo from a copy+paste. txdv-skew-psec is not present in the PHY bindings nor is it in the driver. Correct to txen-skew-psec which is clearly what it was meant to be. Given that the default for txen-skew-psec is 0, and the device tree is only trying to set it to 0 anyway, there should not be any functional change from this fix. Fixes: 361b0dcbd7f9 ("arm64: dts: renesas: rzg2l-smarc-som: Enable Ethernet") Fixes: 6494e4f90503 ("arm64: dts: renesas: rzg2ul-smarc-som: Enable Ethernet on SMARC platform") Fixes: ce0c63b6a5ef ("arm64: dts: renesas: Add initial device tree for RZ/G2LC SMARC EVK") Cc: stable@vger.kernel.org # 6.1.y Reported-by: Tomohiro Komagata <tomohiro.komagata.aj@renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230609221136.7431-1-chris.paterson2@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-25arm64: dts: renesas: rzg2l: Update overfow/underflow IRQ names for MTU3 channelsBiju Das
As per R01UH0914EJ0130 Rev.1.30 HW manual the MTU3 overflow/underflow interrupt names start with 'tci' instead of 'tgi'. Replace the below overflow/underflow interrupt names: - tgiv0->tciv0 - tgiv1->tciv1 - tgiu1->tciu1 - tgiv2->tciv2 - tgiu2->tciu2 - tgiv3->tciv3 - tgiv4->tciv4 - tgiv6->tciv6 - tgiv7->tciv7 - tgiv8->tciv8 - tgiu8->tciu8 Fixes: 26336d66d021 ("arm64: dts: renesas: r9a07g044: Add MTU3a node") Fixes: dd123dd01def ("arm64: dts: renesas: r9a07g054: Add MTU3a node") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230724091927.123847-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-25riscv: dts: starfive: jh7110: Add temperature sensor node and thermal-zonesHal Feng
Add temperature sensor and thermal-zones support for the StarFive JH7110 SoC. CPUFreq cooling is supported in thermal-zones. Co-developed-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-07-25riscv: dts: starfive: jh7100: Add temperature sensor node and thermal-zonesHal Feng
Add temperature sensor and thermal-zones support for the StarFive JH7100 SoC. Co-developed-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-07-25riscv: dts: starfive: visionfive 2: Add configuration of gmac and phySamin Guo
v1.3B: v1.3B uses motorcomm YT8531(rgmii-id phy) x2, need delay and inverse configurations. The tx_clk of v1.3B uses an external clock and needs to be switched to an external clock source. v1.2A: v1.2A gmac0 uses motorcomm YT8531(rgmii-id) PHY, and needs delay configurations. v1.2A gmac1 uses motorcomm YT8512(rmii) PHY, and needs to switch rx and rx to external clock sources. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Signed-off-by: Samin Guo <samin.guo@starfivetech.com> [conor: squashed a fix from Samin to use the actual properties] Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-07-24dt-bindings: cpu: Document NVIDIA Tegra186 CCPLEX clusterThierry Reding
Add device tree bindings for the CCPLEX cluster found on NVIDIA Tegra186 SoCs. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-21ARM: tegra: Add missing reset-names for Tegra HS UARTThierry Reding
The device tree bindings for the Tegra high-speed UART require the reset-names property, so add it whenever the compatible string for the serial port is overwritten. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-21ARM: tegra: Remove reset-names for UART devicesThierry Reding
The UART devices found on Tegra chips have a single reset connected to them, so a reset-names property isn't needed. In fact, the device tree bindings don't allow this property, so remove them to allow the nodes to be properly validated. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-21ARM: tegra: Remove dmas and dma-names for debug UARTThierry Reding
The debug UART doesn't support DMA and the DT bindings prohibit the use of the dmas and dma-names properties for it, so remove them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-21dt-bindings: serial: tegra-hsuart: Convert to json-schemaThierry Reding
Convert the Tegra High-Speed UART bindings from the free-form text format to json-schema. While at it, also fix fix the example to reflect the correct compatible string for Tegra30 chips. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-21dt-bindings: arm: tegra: ahb: Convert to json-schemaThierry Reding
Convert the NVIDIA Tegra AHB bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-21dt-bindings: arm: tegra: flowctrl: Convert to json-schemaThierry Reding
Convert the Tegra flow controller bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-20ARM: dts: samsung: fix Exynos4212 Tab3 makefile entriesKrzysztof Kozlowski
Makefile targets are DTB, not DTS. Reported-by: Linux Kernel Functional Testing <lkft@linaro.org> Reported-by: Naresh Kamboju <naresh.kamboju@linaro.org> Closes: https://lore.kernel.org/linux-arm-kernel/CA+G9fYsfziBmQGQMGAKojhemCXssFyiNgk6aNjVXpJNNFh_5mg@mail.gmail.com/ Fixes: ee37a457af1d ("ARM: dts: exynos: Add Samsung Galaxy Tab 3 8.0 boards") Reviewed-by: Artur Weber <aweber.kernel@gmail.com> Link: https://lore.kernel.org/r/20230720141537.188869-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
generated by cgit (git 2.34.1) at 2025-09-12 11:50:07 +0000