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2021-08-04arm64: dts: qcom: sdm630: Raise tcsr_mutex_regs sizeKonrad Dybcio
Enlarge the size to make sure all relevant registers can be reached. This will be required to support the modem. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-19-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Add ADSP remoteproc configurationKonrad Dybcio
Configure the ADSP remote processor and add a simple sound{} node to make way for future development. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-18-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Add thermal-zones configurationKonrad Dybcio
Add a basic thermal-zones configuration to make sure the SoC doesn't overheat itself to death. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-17-konrad.dybcio@somainline.org [bjorn: Sorted thermal-zones below "soc"] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Add modem/ADSP SMP2P nodesKonrad Dybcio
Add SMP2P nodes that are required for ADSP and modem bringup. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-16-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Add TSENS nodeKonrad Dybcio
This will enable temperature reporting for various SoC components. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-15-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Add qcom,adreno-smmu compatibleAngeloGioacchino Del Regno
The Adreno SMMU in SDM630 needs this compatible string for proper context handling and split pagetables support. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-14-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Add clocks and power domains to SMMU nodesAngeloGioacchino Del Regno
Add the required clocks and power domains for the SMMUs to work. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-13-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Add GPU Clock Controller nodeAngeloGioacchino Del Regno
Add the GPU Clock Controller in SDM630 and keep it disabled by default. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-12-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Add interconnect and opp table to sdhc_1AngeloGioacchino Del Regno
The SDHC port 1 has interconnects and can make use of DVFS: define the interconnections and the OPP table in order to optimize performance and power consumption. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-11-konrad.dybcio@somainline.org [bjorn: Dropped "sdhc1-" prefix from opp-table node] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Add SDHCI2 nodeAngeloGioacchino Del Regno
This will enable usage of (generally) uSD cards. While at it, add accompanying OPP table for DVFS. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-10-konrad.dybcio@somainline.org [bjorn: Dropped "sdhci1-" prefix from opp-table node] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Fix TLMM node and pinctrl configurationAngeloGioacchino Del Regno
Previous pinctrl configuration was wrong. Fix it and clean up how multi-pin states are described. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-9-konrad.dybcio@somainline.org [bjorn: Polished the commit message] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Add USB configurationKonrad Dybcio
This will let us use USB2 on our devices. The SoC supposedly supports USB3, but there are no known cases of devices that actually have USB3 wired up in hardware. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-8-konrad.dybcio@somainline.org [bjorn: Changes dwc3 node name to "usb"] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Add qfprom subnodesAngeloGioacchino Del Regno
These will be required for USB and Adreno support. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-7-konrad.dybcio@somainline.org [bjorn: y/_/-/ in gpu_speed_bin] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Add MDSS nodesKonrad Dybcio
Add MDSS node along with its children to enable display functionality. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-6-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Add interconnect provider nodesKonrad Dybcio
Add interconnect provider nodes to allow for NoC bus scaling. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-5-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Add MMCC nodeKonrad Dybcio
Add MultiMedia Clock Controller node to allow for accessing and controlling Multimedia Subsystem clocks by their respective users. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-4-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Add RPMPD nodesKonrad Dybcio
Add the rpmpd node on the sdm630 and define the available levels. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-3-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sdm630: Rewrite memory mapAngeloGioacchino Del Regno
The memory map was wrong. Fix it. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210728222542.54269-2-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sm8150: Fix incorrect cpu opp table entryThara Gopinath
CPU0 frequency 768MHz is wrongly modeled as 576000000 hz in cpu0_opp_table. Use the correct value 768000000 hz. Fixes: 2b6187abafea ("arm64: dts: qcom: sm8150: Add CPU opp tables") Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210804132847.2503269-1-thara.gopinath@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm64: dts: qcom: sm8150-mtp: Add 8150 compatible stringThara Gopinath
Add "qcom,sm8150" as one of the platform compatible strings. This will be later used by cpufreq-dt-platdev to exclude using cpufreq-dt cpufreq driver. Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210804133223.2503517-1-thara.gopinath@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-04arm: dts: mt7623: increase passive cooling tripFrank Wunderlich
MT7623/BPI-R2 has idle temperature after bootup from 48 degrees celsius increase the passive trip temp threshold to not trottle CPU frequency at this temperature Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Link: https://lore.kernel.org/r/20210725163451.217610-1-linux@fw-web.de Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-08-04Merge tag 'at91-dt-5.15' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/dt AT91 dt for 5.15: - add sama7g5 SoC and associated evaluation kit, the sama7g5-ek - adaptation of some DT for sama5d27 som1 ek, sama5d4 xplained and sama5d2 icp boards - fixes to gpio and shutdown controller nodes for all boards * tag 'at91-dt-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: ARM: dts: at91: use the right property for shutdown controller ARM: dts: at91: sama5d2_icp: enable digital filter for I2C nodes ARM: dts: at91: sama5d4_xplained: change the key code of the gpio key ARM: dts: at91: add conflict note for d3 ARM: dts: at91: add pinctrl-{names, 0} for all gpios ARM: dts: at91: sama5d27_som1_ek: enable ADC node ARM: dts: at91: sama5d4_xplained: Remove spi0 node dt-bindings: atmel-sysreg: add bindings for sama7g5 ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek dt-bindings: ARM: at91: document sama7g5ek board Link: https://lore.kernel.org/r/20210804085000.13233-1-nicolas.ferre@microchip.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-08-04Merge tag 'ux500-dts-v5.15-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into arm/dt Ux500 Device Tree updates for the v5.15 kernel cycle: - New device trees for these mobile phones: - Samsung Gavini - Samsung Codina - Samsung Kyle - Flag eMMC cards as non-SD non-SDIO to save time - Link USB PHY to USB controller in the device tree - Fix up the operating points to the actual clock frequencies * tag 'ux500-dts-v5.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik: ARM: dts: ux500: Adjust operating points to reality ARM: dts: ux500: Add a device tree for Kyle ARM: dts: ux500: Add devicetree for Codina ARM: dts: ux500: ab8500: Link USB PHY to USB controller node ARM: dts: ux500: Flag eMMCs as non-SDIO/SD ARM: dts: ux500: Add device tree for Samsung Gavini Link: https://lore.kernel.org/r/CACRpkdbjBv5ywZZD8rK07d5sLcHsG8o4iYD-3jHO=HLg6-nKnA@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-08-03arm64: dts: qcom: Add support for SONY Xperia X Performance / XZ / XZs ↵AngeloGioacchino Del Regno
(msm8996, Tone platform) Add support for following boards: - Xperia X Performance (dora) - Xperia XZ (kagura) - Xperia XZs (keyaki) They are all based on the SONY Tone platform and feature largely similar hardware with the most obvious differences being lack of USB-C and ToF sensor on Dora and different camera sensor on Keyaki. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210608202143.247427-4-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-03arm64: dts: qcom: msm8996-*: Disable HDMI by defaultKonrad Dybcio
Most phones ship without HDMI and leaving it enabled wrecks havoc. Disable it in msm8996.dtsi and re-enable it on the boards that did not disable it previously. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210608202143.247427-3-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-03arm64: dts: qcom: Add MSM8996v3.0 DTSI fileKonrad Dybcio
Add an overlay for MSM8996v3.0, which is a pre-final revision of the said SoC. It has some stark differences with regards to GPU, or more specifically its power delivery path. Oh, and of course a different msm-id. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210608202143.247427-2-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-03arm64: dts: qcom: Add PMI8996 DTSI fileKonrad Dybcio
PMI8996 is *almost* the same hardware as PMI8994, say for some annoyances: - Boards equipped with PMI8996 now have to include pmic-id (which wasn't the case before) - Different qpnp-ibb-discharge-resistor value (will be addressed after LABIBB is introduced) - Different inhibit-derating-ua value (will be addressed after BCL is introduced) - Different ramp_up_step value (will be addressed after [if?] QPNP Flash LED is introduced) This DTSI is supposed to be included >>ON TOP OF<< pmi8994.dtsi, like this: -- msm8996-nice-device.dts -- \#include "pmi8994.dtsi" \#include "pmi8996.dtsi" or more likely like this: -- msm8996-some-phone.dts -- \#include "msm8996.dtsi" ... \#include "pmi8994.dtsi" -- msm8996-pmi8996-some-phone.dts -- \#include "msm8996-some-phone.dts" \#include "pmi8996.dtsi" So that we only have to keep 2 DTs for devices that were shipped with both ones, instead of what would be three (device base + pmi8994 + pmi8996) Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210608202143.247427-1-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-08-03ARM: dts: am57xx: Add PRUSS MDIO controller nodesSuman Anna
The PRUSSs on AM57xx SoCs contain an MDIO controller that can be used to control external PHYs associated with the Industrial Ethernet peripherals within each PRUSS. The MDIO module used within the PRU-ICSS is an instance of the MDIO Controller used in TI Davinci SoCs. The same bus frequency of 1 MHz is chosen as the regular MDIO node. The nodes are added in the common am57-pruss.dtsi file and enabled by default, but are disabled in all the existing AM57xx board dts files. These nodes need pinctrl lines, and so should be enabled only on boards where they are actually wired and pinned out for PRUSS Ethernet. Any new board dts file should disable these if they are not sure. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-08-03ARM: dts: am57xx: Add PRU-ICSS nodesSuman Anna
Add the DT nodes for the PRU-ICSS1 and PRU-ICSS2 processor subsystems that are present on AM57xx family of SoCs. Each PRU-ICSS instance is represented by a pruss node and other child nodes. The two PRU-ICSSs are identical to each other. They are not supported on DRA7xx SoCs in general, so the nodes are added under the respective interconnect target module nodes in a common am57-pruss.dtsi file. The file is already included only in the AM57xx related board files. The PRU-ICSSs on AM57xx are very similar to the PRUSS in AM33xx and AM437x except for variations in the RAM sizes and the number of interrupts coming into the MPU INTC. The interrupt events into the PRU-ICSS also requires programming of the corresponding crossbars properly. The PRUSS subsystem node contains the entire address space. The various sub-modules of the PRU-ICSS are represented as individual child nodes (so platform devices themselves) of the PRUSS subsystem node. These include the two PRU cores and the interrupt controller. All the Data RAMs are represented within a child node of its own named 'memories' without any compatible. The Real Time Media Independent Interface controller (MII_RT), and the CFG sub-module are represented as syscon nodes. The PRUSS CFG module has a clock mux for IEP clock, this clk node is added under the CFG child node 'clocks'. The default source for this mux clock is the ICSS_IEP_CLK clock. The DT nodes use all standard properties. The regs property in the PRU nodes define the addresses for the Instruction RAM, the Debug and Control sub-modules for that PRU core. The firmware for each PRU core is defined through a 'firmware-name' property. The default names for the firmware images for each PRU core are defined as follows (these can be adjusted either in derivative board dts files or through sysfs at runtime if required): PRU-ICSS1 PRU0 Core: am57xx-pru1_0-fw PRU-ICSS1 PRU1 Core: am57xx-pru1_1-fw PRU-ICSS2 PRU0 Core: am57xx-pru2_0-fw PRU-ICSS2 PRU1 Core: am57xx-pru2_1-fw Note: 1. There are few more sub-modules like the Industrial Ethernet Peripheral (IEPs), MDIO, UART, eCAP that do not have bindings and so will be added in the future. 2. The PRUSS INTC on AM57xx SoCs also connect the host interrupts 6 and 7 as possible DMA events, so use the 'ti,irqs-reserved' property in derivative board dts files _if_ any of them should not be handled by the host OS. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-08-03ARM: dts: am4372: Add PRUSS MDIO controller nodeAndrew F. Davis
The PRU-ICSS1 instance on AM437x SoCs has a MDIO sub-module that can be used to control external PHYs associated with the Industrial Ethernet peripherals within the PRUSS. The MDIO module used within this PRU-ICSS is an instance of the MDIO Controller used in TI Davinci SoCs. The same bus frequency of 1 MHz is chosen as the regular MDIO node. Note that there is no MDIO node added to the smaller PRU-ICSS0 instance as the MDIO pins are not pinned out. The node is added and enabled in the common am4372.dtsi file by default, and disabled in all the existing AM437x board dts files. This node needs pinctrl lines, and so should be enabled only on boards where they are actually wired and pinned out for PRUSS Ethernet. Any new board dts file should disable these if they are not sure. Signed-off-by: Andrew F. Davis <afd@ti.com> [s-anna@ti.com: fix reg address, add commit description] Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-08-03ARM: dts: am4372: Add the PRU-ICSS0 DT nodeSuman Anna
The AM4376+ SoCs have a second smaller PRU-ICSS subsystem (PRUSS0) in addition to the primary PRUSS1 instance. The PRUSS0 has less DRAM per PRU, and no Shared DRAM among other minor differences. The IEP and MII_RT modules even though present within the IP are not pinned out. This PRUSS0 instance has a weird SoC integration. It shares the same L3 OCP interconnect interface with PRUSS1, and also shares its reset line and clocks. Any external accesses from PRUSS0 requires the PRUSS1's PRUSS_SYSCFG register to be programmed properly. That said, it is its own IP instance (a cut-down version), and so it has been added as an independent node (sibling node to PRUSS1 node) and a child node of the corresponding PRUSS target module interconnect node. This allows the PRUSS0 instance to be enabled/disabled independently of the PRUSS1 instance. The nodes are added under the corresponding interconnect target module node in the common am4372 dtsi file. The PRU-ICSS instances are not supported on AM4372 SoC though in the AM437x family, so the interconnect target module node should be disabled in any derivative board dts file that uses AM4372 SoCs. The individual PRUSS node can be disabled in the corresponding board dts file if desired. The default names for the firmware images for each PRU core are defined as follows (these can be adjusted either in derivative board dts files or through sysfs at runtime if required): PRU-ICSS0 PRU0 Core: am437x-pru0_0-fw PRU-ICSS0 PRU1 Core: am437x-pru0_1-fw Note: 1. There are few more sub-modules like the Industrial Ethernet Peripheral (IEP), eCAP, UART, that do not have bindings and so will be added in the future. Only UART is pinned out, so others should be added in disabled state if added. 2. The PRUSS0 INTC on AM437x SoCs routes the host interrupt 5 to the other PRUSS1, so it is already marked reserved through the 'ti,irqs-reserved' property. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-08-03ARM: dts: am4372: Add the PRU-ICSS1 DT nodeSuman Anna
Add the DT node for the PRU-ICSS1 instance on the AM437x family of SoCs. Each PRU-ICSS instance is represented by a pruss node and other child nodes. The nodes are added under the interconnect target module node in the common am4372 dtsi file. The PRU-ICSS instances are supported only on AM4376+ SoCs though in the AM437x family, so the interconnect target module node should be disabled in any derivative board dts file that uses AM4372 SoCs. The PRU-ICSS1 on AM437x is very similar to the PRUSS in AM33xx, except for variations in the RAM sizes, bus addresses and the number of interrupts coming into the MPU INTC (host interrupt 5 is routed to the other PRUSS instead of MPU). The PRUSS subsystem node contains the entire address space. The various sub-modules of the PRU-ICSS are represented as individual child nodes (so platform devices themselves) of the PRUSS subsystem node. These include the two PRU cores and the interrupt controller. All the Data RAMs are represented within a child node of its own named 'memories' without any compatible. The Real Time Media Independent Interface controller (MII_RT), and the CFG sub-module are represented as syscon nodes. The PRUSS CFG module has a clock mux for IEP clock, this clk node is added under the CFG child node 'clocks'. The default source for this mux clock is the PRU_ICSS_IEP_GCLK clock. The DT nodes use all standard properties. The regs property in the PRU nodes define the addresses for the Instruction RAM, the Debug and Control sub-modules for that PRU core. The firmware for each PRU core is defined through a 'firmware-name' property. The default names for the firmware images for each PRU core are defined as follows (these can be adjusted either in derivative board dts files or through sysfs at runtime if required): PRU-ICSS1 PRU0 Core: am437x-pru1_0-fw PRU-ICSS1 PRU1 Core: am437x-pru1_1-fw Note: 1. There are few more sub-modules like the Industrial Ethernet Peripheral (IEP), MDIO, UART, eCAP that do not have bindings and so will be added in the future. 2. The PRUSS INTC on AM437x SoCs also connect the host interrupt 0 to ADC0 and ADC1; 6 and 7 as possible DMA events, so use the 'ti,irqs-reserved' property in derivative board dts files _if_ any of them should not be handled by the host OS. Host interrupt 5 is already marked reserved as it is connected to the other PRUSS instance. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-08-03ARM: dts: am335x-icev2: Enable PRU-ICSS moduleSuman Anna
The PRU-ICSS target module node was left in disabled state in the base am33xx-l4.dtsi file. PRU-ICSS is supported on the AM335x ICEv2 board, so enable this node to support PRUSS on this board. The PRUSS node and most of its child nodes are already enabled in the base dts file, and so become effective automatically with the enabling of this PRU-ICSS target module node. The corresponding PRU nodes can be disabled later on if there are no use-cases defined to use a particular PRU core or the whole PRU-ICSS subsystem itself if both its PRU cores are unused. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-08-03ARM: dts: am335x-evmsk: Enable PRU-ICSS moduleSuman Anna
The PRU-ICSS target module node was left in disabled state in the base am33xx-l4.dtsi file. PRU-ICSS is supported on the AM335x SK EVM board, so enable this node to support PRUSS on this board. The PRUSS node and most of its child nodes are already enabled in the base dts file, and so become effective automatically with the enabling of this PRU-ICSS target module node. The corresponding PRU nodes can be disabled later on if there are no use-cases defined to use a particular PRU core or the whole PRU-ICSS subsystem itself if both its PRU cores are unused. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-08-03ARM: dts: am335x-evm: Enable PRU-ICSS moduleSuman Anna
The PRU-ICSS target module node was left in disabled state in the base am33xx-l4.dtsi file. PRU-ICSS is supported on the AM335x EVM, so enable this node on the AM335x EVM. The PRUSS node and most of its child nodes are already enabled in the base dts file, and so become effective automatically with the enabling of this PRU-ICSS target module node. The corresponding PRU nodes can be disabled later on if there are no use-cases defined to use a particular PRU core or the whole PRU-ICSS subsystem itself if both its PRU cores are unused. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-08-03ARM: dts: am335x-bone-common: Enable PRU-ICSS nodeSuman Anna
The PRU-ICSS target module node was left in disabled state in the base am33xx-l4.dtsi file. Enable this node on all the AM335x beaglebone boards as they mostly use a AM3358 or a AM3359 SoC which do contain the PRU-ICSS IP. The PRUSS node and most of its child nodes are already enabled in the base dts file, and so become effective automatically with the enabling of this PRU-ICSS target-module node. The corresponding PRU nodes can be disabled later on if there are no use-cases defined to use a particular PRU core or the whole PRU-ICSS subsystem itself if both its PRU cores are unused. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-08-03ARM: dts: am33xx-l4: Add PRUSS MDIO controller nodeSuman Anna
The PRUSS on AM335x SoCs has a MDIO sub-module that can be used to control external PHYs associated with the Industrial Ethernet peripherals within the PRUSS. The MDIO module used within the PRU-ICSS is an instance of the MDIO Controller used in TI Davinci SoCs. The same bus frequency of 1 MHz is chosen as the regular MDIO node. The node is added to the common am33xx-l4.dtsi file and is disabled. This needs to be enabled in the respective board files using the relevant AM335x SoCs supporting PRUSS and where the ethernet is pinned out and connected properly. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-08-03ARM: dts: am33xx-l4: Add PRUSS nodeSuman Anna
Add the DT nodes for the PRU-ICSS on AM33xx family of SoCs. The AM33xx SoCs contain a single PRU-ICSS instance and is represented by a pruss node and other child nodes. PRU-ICSS is supported only on AM3356+ SoCs though in the AM33xx family, so the nodes are added under the corresponding disabled interconnect target module node in the common am33xx-l4 dtsi file. The target module node should be enabled in only those derivative board files that use a SoC containing PRU-ICSS. The PRUSS subsystem node contains the entire address space. The various sub-modules of the PRU-ICSS are represented as individual child nodes (so platform devices themselves) of the PRUSS subsystem node. These include the two PRU cores and the interrupt controller. All the Data RAMs are represented within a child node of its own named 'memories' without any compatible. The Real Time Media Independent Interface controller (MII_RT), and the CFG sub-module are represented as syscon nodes. The PRUSS CFG module has a clock mux for IEP clock, this clk node is added under the CFG child node 'clocks'. The default source for this mux clock is the PRU_ICSS_IEP_GCLK clock. The DT nodes use all standard properties. The regs property in the PRU nodes define the addresses for the Instruction RAM, the Debug and Control sub-modules for that PRU core. The firmware for each PRU core is defined through a 'firmware-name' property. The default names for the firmware images for each PRU core are defined as follows (these can be adjusted either in derivative board dts files or through sysfs at runtime if required): PRU-ICSS PRU0 Core: am335x-pru1_0-fw PRU-ICSS PRU1 Core: am335x-pru1_1-fw Note: 1. There are few more sub-modules like the Industrial Ethernet Peripheral (IEP), MDIO, UART, eCAP that do not have bindings and so will be added in the future. 2. The PRUSS INTC on AM335x SoCs also connect the host interrupts 0 to TSC_ADC; 6 and 7 as possible DMA events, so use the 'ti,irqs-reserved' property in derivative board dts files _if_ any of them should not be handled by the host OS. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-08-03ARM: dts: aspeed-g5: Remove ngpios from sgpio node.Steven Lee
Remove ngpios property from sgpio node as it should be defined in the platform dts. Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20210712100317.23298-5-steven_lee@aspeedtech.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-08-03ARM: dts: aspeed-g6: Add SGPIO node.Steven Lee
AST2600 supports 2 SGPIO master interfaces one with 128 pins another one with 80 pins. Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> Link: https://lore.kernel.org/r/20210712100317.23298-4-steven_lee@aspeedtech.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-08-03dt-bindings: aspeed-sgpio: Add ast2600 sgpioSteven Lee
AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one with 80 pins. Add ast2600-sgpiom compatibles and update descriptions to introduce the max number of available gpio pins that AST2600 supported. Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210712100317.23298-3-steven_lee@aspeedtech.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-08-03dt-bindings: aspeed-sgpio: Convert txt bindings to yaml.Steven Lee
sgpio-aspeed bindings should be converted to yaml format. Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20210712100317.23298-2-steven_lee@aspeedtech.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-08-02arm64: tegra: Fix Tegra194 PCIe EP compatible stringVidya Sagar
The initialization sequence performed by the generic platform driver pcie-designware-plat.c for a DWC based implementation doesn't work for Tegra194. Tegra194 has a different initialization sequence requirement which can only be satisfied by the Tegra194 specific platform driver pcie-tegra194.c. So, remove the generic compatible string "snps,dw-pcie-ep" from Tegra194's endpoint controller nodes. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-02Merge tag 'renesas-dt-bindings-for-v5.15-tag1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt Renesas DT binding updates for v5.15 - Document support for the new R-Car H3e-2G and M3e-2G SoCs and boards. * tag 'renesas-dt-bindings-for-v5.15-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: dt-bindings: arm: renesas: Document R-Car H3e-2G and M3e-2G SoCs and boards Link: https://lore.kernel.org/r/cover.1627650706.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-08-02Merge tag 'renesas-arm-dt-for-v5.15-tag1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt Renesas ARM DT updates for v5.15 - Switches support for the Draak and Ebisu development boards, - I2C support on RZ/G2L, - I2C EEPROM support on the Ebisu development board, - Sound support for the R-Car D3 SoC and the Draak development board, - Support for the new R-Car H3e-2G and M3e-2G SoCs on the Salvator-XS and ULCB development boards, - IOMMU support for DMAC, EtherAVB, and SDHI on the R-Car M3-W+ SoC, - Miscellaneous fixes and improvements. * tag 'renesas-arm-dt-for-v5.15-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (29 commits) arm64: dts: renesas: r8a77961: Add iommus to ipmmu_ds[01] related nodes arm64: dts: renesas: Add support for M3ULCB+Kingfisher with R-Car M3e-2G arm64: dts: renesas: Add support for M3ULCB with R-Car M3e-2G arm64: dts: renesas: Add support for Salvator-XS with R-Car M3e-2G arm64: dts: renesas: Add support for H3ULCB+Kingfisher with R-Car H3e-2G arm64: dts: renesas: Add support for H3ULCB with R-Car H3e-2G arm64: dts: renesas: Add support for Salvator-XS with R-Car H3e-2G arm64: dts: renesas: Add Renesas R8A779M3 SoC support arm64: dts: renesas: Add Renesas R8A779M1 SoC support arm64: dts: renesas: hihope-rzg2-ex: Add EtherAVB internal rx delay arm64: dts: renesas: r8a77995: draak: Add R-Car Sound support arm64: dts: renesas: r8a77995: Add R-Car Sound support arm64: dts: renesas: rcar-gen3: Add SoC model to comment headers arm64: dts: renesas: r8a77990: ebisu: Add I2C EEPROM for PMIC arm64: dts: renesas: r8a77995: draak: Remove bogus adv7511w properties arm64: dts: renesas: beacon: Enable micbias arm64: dts: renesas: r9a07g044: Add I2C nodes arm64: dts: renesas: r8a779a0: Restore sort order arm64: dts: renesas: r8a77990: ebisu: Add SW4 support arm64: dts: renesas: r8a77995: draak: Add SW56 support ... Link: https://lore.kernel.org/r/cover.1627650696.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-08-02ARM: dts: owl-s500-roseapplepi: Add ethernet supportCristian Ciocaltea
Add pinctrl configuration for enabling the Ethernet MAC on RoseapplePi SBC. Additionally, provide the necessary properties for the generic S500 ethernet node in order to setup PHY and MDIO. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/d0e1fbf81984127f0352eb740c7129424b5e40f9.1623401998.git.cristian.ciocaltea@gmail.com Link: https://lore.kernel.org/r/20210628072817.8269-3-mani@kernel.org' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-08-02ARM: dts: owl-s500: Add ethernet supportCristian Ciocaltea
Add Ethernet MAC device tree node for Actions Semi S500 SoC. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/222ee0c2cb431619f558dce9726585ac92f65e00.1623401998.git.cristian.ciocaltea@gmail.com Link: https://lore.kernel.org/r/20210628072817.8269-2-mani@kernel.org' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-08-02ARM: dts: at91: use the right property for shutdown controllerNicolas Ferre
The wrong property "atmel,shdwc-debouncer" was used to specify the debounce delay for the shutdown controler. Replace it with the documented and implemented property "debounce-delay-us", as mentioned in v4 driver submission. See: https://lore.kernel.org/r/1458134390-23847-3-git-send-email-nicolas.ferre@atmel.com/ Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Reported-by: Clément Léger <clement.leger@bootlin.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20210730172729.28093-1-nicolas.ferre@microchip.com/
2021-08-01Linux 5.14-rc4v5.14-rc4Linus Torvalds
2021-08-02ARM: dts: ux500: Adjust operating points to realityLinus Walleij
The operating points should correspond to the actual frequencies supported for the CPU. Other patches have fixed so these are rounded and reported properly, this fixes the device trees to match. The Codina variant has a lower frequency than other devices so indicate this in the device tree. Cc: phone-devel@vger.kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit (git 2.34.1) at 2025-09-29 08:08:29 +0000