Age | Commit message (Collapse) | Author |
|
This patch also fix the balance of braces.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
|
|
R8A66597 has the pin of WR0 and WR1. So, if one write-pin of CPU
connects to the pins, we have to change the setting of FIFOSEL
register in the controller. If we don't change the setting,
the controller cannot send the data of odd length.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
|
|
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
|
|
Given that we want the default to not have any <mach/memory.h> and given
that there are now fewer cases where it is still provided than the cases
where it is not at this point, this makes sense to invert the logic and
just identify the exception cases.
The word "need" instead of "have" was chosen to construct the config
symbol so not to suggest that having a mach/memory.h file is actually
a feature that one should aim for.
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
|
Allow processes that share the same XRC domain to open an existing
shareable QP. This permits those processes to receive events on the
shared QP and transfer ownership, so that any process may modify the
QP. The latter allows the creating process to exit, while a remaining
process can still transition it for path migration purposes.
Signed-off-by: Sean Hefty <sean.hefty@intel.com>
Signed-off-by: Roland Dreier <roland@purestorage.com>
|
|
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
|
XRC TGT QPs are shared resources among multiple processes. Since the
creating process may exit, allow other processes which share the same
XRC domain to open an existing QP. This allows us to transfer
ownership of an XRC TGT QP to another process.
Signed-off-by: Sean Hefty <sean.hefty@intel.com>
Signed-off-by: Roland Dreier <roland@purestorage.com>
|
|
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
|
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
|
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
|
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
|
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
|
Move some DDR2 related defines into a private <mach/ddr2.h> beforehand.
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
|
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
|
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
|
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
|
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
|
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
|
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
|
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
|
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
|
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
|
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
|
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
|
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
|
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
|
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
|
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
|
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
|
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
|
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
|
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
|
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
|
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
|
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
|
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
|
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
|
This also removes the mach/s3c2400 version which was probably never used
due to the fact that we have this line in arch/arm/Makefile:
machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 [...]
This is later used to construct the search path for:
The compiler would be looking into mach-s3c2410 and picking up this
version first. Any config that was actually expecting the mach-s3c2400
version was therefore producing a broken kernel binary. Not relying on
any of them anymore would fix that issue.
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
|
Support the creation of XRC INI and TGT QPs. To handle the case where
a CQ or PD is not provided, we allocate them internally with the xrcd.
Signed-off-by: Sean Hefty <sean.hefty@intel.com>
Signed-off-by: Roland Dreier <roland@purestorage.com>
|
|
Allow the user to create XRC SRQs. This patch is based on a patch
from Jack Morgenstrein <jackm@dev.mellanox.co.il>.
Signed-off-by: Sean Hefty <sean.hefty@intel.com>
Signed-off-by: Roland Dreier <roland@purestorage.com>
|
|
Support creating and destroying XRC domains. Any sharing of the XRCD
is managed above the low-level driver.
Signed-off-by: Sean Hefty <sean.hefty@intel.com>
Signed-off-by: Roland Dreier <roland@purestorage.com>
|
|
Because an XRC TGT QP can end up being shared among multiple
processes, don't have the ib_cm automatically send a DREQ when the
userspace process that owns the ib_cm_id exits. Disconnect can be
initiated by the user directly; otherwise, the owner of the XRC INI QP
controls the connection.
Note that as a result of the process exiting, the ib_cm will stop
tracking the XRC connection on the target side. For the purposes of
disconnecting, this isn't a big deal. The ib_cm will respond to the
DREQ appropriately. For other messages, mainly LAP, the CM will
reject the request, since there's no one available to route the
request to.
Signed-off-by: Sean Hefty <sean.hefty@intel.com>
Signed-off-by: Roland Dreier <roland@purestorage.com>
|
|
Allow users to connect XRC QPs through the rdma_cm.
Signed-off-by: Sean Hefty <sean.hefty@intel.com>
Signed-off-by: Roland Dreier <roland@purestorage.com>
|
|
Allow the user to indicate the QP type separately from the port space
when allocating an rdma_cm_id. With RDMA_PS_IB, there is no longer a
1:1 relationship between the QP type and port space, so we need to
switch on the QP type to select between UD and connected QPs.
Signed-off-by: Sean Hefty <sean.hefty@intel.com>
Signed-off-by: Roland Dreier <roland@purestorage.com>
|
|
Add RDMA_PS_IB. XRC QP types will use the IB port space when operating
over the RDMA CM. For the 'IP protocol' field value, we select 0x3F,
which is listed as being for 'any local network'.
Signed-off-by: Sean Hefty <sean.hefty@intel.com>
Signed-off-by: Roland Dreier <roland@purestorage.com>
|
|
Use snd_soc_update_bits for read-modify-write register access instead of
open-coding it using snd_soc_read and snd_soc_write.
Signed-off-by: Axel Lin <axel.lin@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
|
The XRC annex was updated to have XRC behave more like RD. Specifically,
the XRC TGT QPN moves from the local QPN to local EECN field. Lookup of
SRQN is done using the REQ/REP protocol.
Signed-off-by: Sean Hefty <sean.hefty@intel.com>
Signed-off-by: Roland Dreier <roland@purestorage.com>
|
|
Update the REQ and REP messages to support XRC connection setup
according to the XRC Annex. Several existing fields must be set to 0 or
1 when connecting XRC QPs, and a reserved field is changed to an
extended transport type.
Signed-off-by: Sean Hefty <sean.hefty@intel.com>
Signed-off-by: Roland Dreier <roland@purestorage.com>
|
|
Allow user space to operate on XRC TGT QPs the same way as other types
of QPs, with one notable exception: since XRC TGT QPs may be shared
among multiple processes, the XRC TGT QP is allowed to exist beyond the
lifetime of the creating process.
The process that creates the QP is allowed to destroy it, but if the
process exits without destroying the QP, then the QP will be left bound
to the lifetime of the XRCD.
TGT QPs are not associated with CQs or a PD.
Signed-off-by: Sean Hefty <sean.hefty@intel.com>
Signed-off-by: Roland Dreier <roland@purestorage.com>
|
|
XRC INI QPs are similar to send only RC QPs. Allow user space to create
INI QPs. Note that INI QPs do not require receive CQs.
Signed-off-by: Sean Hefty <sean.hefty@intel.com>
Signed-off-by: Roland Dreier <roland@purestorage.com>
|