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2024-07-06clk: qcom: lpasscc-sc8280xp: Constify struct regmap_configJavier Carrasco
`lpass_audiocc_sc8280xp_regmap_config` and `lpasscc_sc8280x_regmap_config` are not modified and can be declared as const to move their data to a read-only section. Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240703-clk-const-regmap-v1-8-7d15a0671d6f@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-07-01clk: qcom: gcc-x1e80100: Fix halt_check for all pipe clocksAbel Vesa
In case of all pipe clocks, there is a QMP PHY clock that is feeding them. If, for whatever reason, the clock from the PHY is not enabled, halt bit will not get set, and the clock controller driver will assume the clock is stuck in a specific state. The way this is supposed to be properly fixed is to defer the checking of the halt bit until after the PHY clock has been initialized, but doing so complicates the clock controller driver. In fact, since these pipe clocks are consumed by the PHY, while the PHY is also the one providing the source, if clock gets stuck, the PHY driver would be to blame. So instead of checking the halt bit in here, just skip it and assume the PHY driver is handling the source clock correctly. Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100") Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20240628-x1e80100-clk-gcc-fix-halt-check-for-usb-phy-pipe-clks-v2-1-db3be54b1143@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-25clk: qcom: gcc-ipq6018: update sdcc max clock frequencyChukun Pan
The mmc controller of the IPQ6018 does not support HS400 mode. So adjust the maximum clock frequency of sdcc to 200 MHz (HS200). Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Link: https://lore.kernel.org/r/20240620150122.1406631-2-amadeus@jmu.edu.cn Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-25Merge branch '20240602114439.1611-1-quic_jkona@quicinc.com' into clk-for-6.11Bjorn Andersson
Merge SM8650 video and camera clock drivers through topic branch, to make available the DeviceTree binding includes to the DeviceTree source branches as well.
2024-06-25clk: qcom: camcc-sm8650: Add SM8650 camera clock controller driverJagadeesh Kona
Add support for the camera clock controller for camera clients to be able to request for camcc clocks on SM8650 platform. Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Tested-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Link: https://lore.kernel.org/r/20240602114439.1611-8-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-25dt-bindings: clock: qcom: Add SM8650 camera clock controllerJagadeesh Kona
Add device tree bindings for the camera clock controller on Qualcomm SM8650 platform. Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Link: https://lore.kernel.org/r/20240602114439.1611-7-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-25dt-bindings: clock: qcom: Update the order of SC8280XP camcc headerJagadeesh Kona
Update the order of SC8280XP camcc header file in SM8450 camcc bindings. Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20240602114439.1611-6-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-25clk: qcom: videocc-sm8550: Add SM8650 video clock controllerJagadeesh Kona
Add support to the SM8650 video clock controller by extending the SM8550 video clock controller, which is mostly identical but SM8650 has few additional clocks and minor differences. Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240602114439.1611-5-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-25clk: qcom: videocc-sm8550: Add support for videocc XO clk aresJagadeesh Kona
Add support for videocc XO clk ares for consumer drivers to be able to request this reset. Fixes: f53153a37969 ("clk: qcom: videocc-sm8550: Add video clock controller driver for SM8550") Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240602114439.1611-4-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-25dt-bindings: clock: qcom: Add SM8650 video clock controllerJagadeesh Kona
SM8650 video clock controller has most clocks same as SM8450, but it also has few additional clocks and resets. Add device tree bindings for the video clock controller on Qualcomm SM8650 platform by defining these additional clocks and resets on top of SM8450. Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Link: https://lore.kernel.org/r/20240602114439.1611-3-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-25dt-bindings: clock: qcom: Update SM8450 videocc header file nameJagadeesh Kona
Correct the videocc header file name in SM8450 videocc bindings. Fixes: 1e910b2ba0ed ("dt-bindings: clock: qcom: Add SM8450 video clock controller") Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240602114439.1611-2-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-23clk: qcom: gpucc-sa8775p: Update wait_val fields for GPU GDSC'sTaniya Das
Update wait_val fields as per the default hardware values of the GDSC as otherwise it would lead to GDSC FSM state stuck causing power on/off failures of the GSDC. Fixes: 0afa16afc36d ("clk: qcom: add the GPUCC driver for sa8775p") Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240612-sa8775p-v2-gcc-gpucc-fixes-v2-6-adcc756a23df@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-23clk: qcom: gpucc-sa8775p: Park RCG's clk source at XO during disableTaniya Das
The RCG's clk src has to be parked at XO while disabling as per the HW recommendation, hence use clk_rcg2_shared_ops to achieve the same. Also gpu_cc_cb_clk is recommended to be kept always ON, hence use clk_branch2_aon_ops to keep the clock always ON. Fixes: 0afa16afc36d ("clk: qcom: add the GPUCC driver for sa8775p") Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240612-sa8775p-v2-gcc-gpucc-fixes-v2-5-adcc756a23df@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-23clk: qcom: gpucc-sa8775p: Remove the CLK_IS_CRITICAL and ALWAYS_ON flagsTaniya Das
The GPU clocks/GDSCs have been marked critical from the clock driver but the GPU driver votes on these resources as per the HW requirement. In the case where these clocks & GDSCs are left enabled, would have power impact and also cause GPU stability/corruptions. Fix the same by removing the CLK_IS_CRITICAL for clocks and ALWAYS_ON flags for the GPU GDSCs. Fixes: 0afa16afc36d ("clk: qcom: add the GPUCC driver for sa8775p") Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20240612-sa8775p-v2-gcc-gpucc-fixes-v2-4-adcc756a23df@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-23clk: qcom: gcc-sa8775p: Set FORCE_MEM_CORE_ON for gcc_ufs_phy_ice_core_clkTaniya Das
Update the force mem core bit for UFS ICE clock to force the core on signal to remain active during halt state of the clk. If force mem core bit of the clock is not set, the memories of the subsystem will not retain the logic across power states. Fixes: 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p") Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240612-sa8775p-v2-gcc-gpucc-fixes-v2-3-adcc756a23df@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-23clk: qcom: gcc-sa8775p: Update the GDSC wait_val fields and flagsTaniya Das
Update the GDSC wait_val fields as per the default hardware values as otherwise they would lead to GDSC FSM state to be stuck and causing failures to power on/off. Also add the GDSC flags as applicable and add support to control PCIE GDSC's using collapse vote registers. Fixes: 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p") Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20240612-sa8775p-v2-gcc-gpucc-fixes-v2-2-adcc756a23df@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-23clk: qcom: gcc-sa8775p: Remove support for UFS hw ctl clocksTaniya Das
The UFS hw ctl clocks are not used by any consumers on SA8775P, and these clocks are not using the correct clock ops to manage the hw ctl of the branch clock, hence remove these clocks. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20240612-sa8775p-v2-gcc-gpucc-fixes-v2-1-adcc756a23df@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-23clk: qcom: gpucc-sm8350: Park RCG's clk source at XO during disableTaniya Das
The RCG's clk src has to be parked at XO while disabling as per the HW recommendation, hence use clk_rcg2_shared_ops to achieve the same. Fixes: 160758b05ab1 ("clk: qcom: add support for SM8350 GPUCC") Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8350-HDK Link: https://lore.kernel.org/r/20240621-sm8350-gpucc-fixes-v1-1-22db60c7c5d3@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-21clk: qcom: nsscc-qca8k: Fix the MDIO functions undefined issueLuo Jie
The clock controller driver of QCA8K depends on MDIO_BUS because of mdio_module_driver used to register the driver. This patch fixes the following undefined symbols. ERROR: modpost: "mdio_driver_register" [drivers/clk/qcom/nsscc-qca8k.ko] undefined! ERROR: modpost: "mdio_driver_unregister" [drivers/clk/qcom/nsscc-qca8k.ko] undefined! ERROR: modpost: "__mdiobus_write" [drivers/clk/qcom/nsscc-qca8k.ko] undefined! ERROR: modpost: "__mdiobus_read" [drivers/clk/qcom/nsscc-qca8k.ko] undefined! Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202406161634.B27sOs8B-lkp@intel.com/ Closes: https://lore.kernel.org/oe-kbuild-all/202406162047.QkUMa2fG-lkp@intel.com/ Signed-off-by: Luo Jie <quic_luoj@quicinc.com> Link: https://lore.kernel.org/r/20240617093806.3461165-1-quic_luoj@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-21clk: qcom: select right config in CLK_QCM2290_GPUCC definitionLukas Bulwahn
Commit 8cab033628b1 ("clk: qcom: Add QCM2290 GPU clock controller driver") adds the config CLK_QCM2290_GPUCC, which intends to select the support for the QCM2290 Global Clock Controller. It however selects the non-existing config CLK_QCM2290_GCC, whereas the config for the QCM2290 Global Clock Controller is named QCM_GCC_2290. Adjust the config to the intended one. Signed-off-by: Lukas Bulwahn <lukas.bulwahn@redhat.com> Fixes: 8cab033628b1 ("clk: qcom: Add QCM2290 GPU clock controller driver") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240620201431.93254-1-lukas.bulwahn@redhat.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-21clk: qcom: Remove QCOM_RPMCC symbolElliot Berman
This symbol is selected by a couple drivers, but isn't used by anyone and hasn't been for years now. Drop it. No functional change intended. Signed-off-by: Elliot Berman <quic_eberman@quicinc.com> Reviewed-by: Mike Tipton <quic_mdtipton@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240619-drop-qcom-rpmcc-v1-1-b487c95162ef@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-13clk: qcom: Add QCM2290 GPU clock controller driverKonrad Dybcio
Add a driver for the GPU clock controller block found on the QCM2290 SoC. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240606-topic-rb1_gpu-v4-3-4bc0c19da4af@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-12clk: qcom: clk-alpha-pll: Add HUAYRA_2290 supportKonrad Dybcio
Commit 134b55b7e19f ("clk: qcom: support Huayra type Alpha PLL") introduced an entry to the alpha offsets array, but diving into QCM2290 downstream and some documentation, it turned out that the name Huayra apparently has been used quite liberally across many chips, even with noticeably different hardware. Introduce another set of offsets and a new configure function for the Huayra PLL found on QCM2290. This is required e.g. for the consumers of GPUCC_PLL0 to properly start. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240606-topic-rb1_gpu-v4-2-4bc0c19da4af@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-12Merge branch '20240606-topic-rb1_gpu-v4-1-4bc0c19da4af@linaro.org' into ↵Bjorn Andersson
clk-for-6.11 Merge the QCM2290 GPUCC binding through a topic branch to allow for it to also be merged into the DeviceTree branch.
2024-06-12dt-bindings: clock: Add Qcom QCM2290 GPUCCKonrad Dybcio
Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's QCM2290 SoCs. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240606-topic-rb1_gpu-v4-1-4bc0c19da4af@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-12clk: qcom: add clock controller driver for qca8386/qca8084Luo Jie
The clock controller driver of qca8386/qca8084 is registered as the MDIO device, the hardware register is accessed by MDIO bus that is normally used to access general PHY device, which is different from the current existed qcom clock controller drivers using ioremap to access hardware clock registers, nsscc-qca8k is accessed via an MDIO bus. MDIO bus is commonly utilized by both qca8386/qca8084 and other PHY devices, so the mutex lock mdio_bus->mdio_lock should be used instead of using the mutex lock of remap. To access the hardware clock registers of qca8386/qca8084, there is a special MDIO frame sequence, which needs to be sent to the device. Enable the reference clock before resetting the clock controller, the reference clock rate is fixed to 50MHZ. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Luo Jie <quic_luoj@quicinc.com> Link: https://lore.kernel.org/r/20240605124541.2711467-5-quic_luoj@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-12clk: qcom: common: commonize qcom_cc_really_probeLuo Jie
The previous wrapper qcom_cc_really_probe takes the platform device as parameter, which is limited to platform driver. As for qca8k clock controller driver, which is registered as the MDIO device, which also follows the qcom clock framework. To commonize qcom_cc_really_probe, updating it to take the struct device as parameter, so that the qcom_cc_really_probe can be utilized by the previous platform device and the new added MDIO device. Also update the current clock controller drivers to take &pdev->dev as parameter when calling qcom_cc_really_probe. Reviewed-by: Stephen Boyd <sboyd@kernel.org> Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Luo Jie <quic_luoj@quicinc.com> Link: https://lore.kernel.org/r/20240605124541.2711467-4-quic_luoj@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-12dt-bindings: clock: add qca8386/qca8084 clock and reset definitionsLuo Jie
QCA8386/QCA8084 includes the clock & reset controller that is accessed by MDIO bus. Two work modes are supported, qca8386 works as switch mode, qca8084 works as PHY mode. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Luo Jie <quic_luoj@quicinc.com> Link: https://lore.kernel.org/r/20240605124541.2711467-3-quic_luoj@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-12clk: qcom: branch: Add clk_branch2_prepare_opsLuo Jie
Add the clk_branch2_prepare_ops for supporting clock controller where the hardware register is accessed by MDIO bus, and the spin lock can't be used because of sleep during the MDIO operation. The clock is enabled by the .prepare instead of .enable when the clk_branch2_prepare_ops is used. Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Luo Jie <quic_luoj@quicinc.com> Link: https://lore.kernel.org/r/20240605124541.2711467-2-quic_luoj@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-12dt-bindings: clock: qcom,sm8450-gpucc: reference qcom,gcc.yamlKrzysztof Kozlowski
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-16-f947b24f1283@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-12dt-bindings: clock: qcom,sm8550-dispcc: reference qcom,gcc.yamlKrzysztof Kozlowski
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-15-f947b24f1283@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-12dt-bindings: clock: qcom,sm8450-dispcc: reference qcom,gcc.yamlKrzysztof Kozlowski
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-14-f947b24f1283@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-12dt-bindings: clock: qcom,sm6115-dispcc: reference qcom,gcc.yamlKrzysztof Kozlowski
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-13-f947b24f1283@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-12dt-bindings: clock: qcom,sdm845-dispcc: reference qcom,gcc.yamlKrzysztof Kozlowski
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-12-f947b24f1283@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-12dt-bindings: clock: qcom,sc7280-dispcc: reference qcom,gcc.yamlKrzysztof Kozlowski
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-11-f947b24f1283@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-12dt-bindings: clock: qcom,sc7180-dispcc: reference qcom,gcc.yamlKrzysztof Kozlowski
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-10-f947b24f1283@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-12dt-bindings: clock: qcom,qcm2290-dispcc: reference qcom,gcc.yamlKrzysztof Kozlowski
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-9-f947b24f1283@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-12dt-bindings: clock: qcom,msm8998-gpucc: reference qcom,gcc.yamlKrzysztof Kozlowski
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-8-f947b24f1283@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-12dt-bindings: clock: qcom,gpucc: reference qcom,gcc.yamlKrzysztof Kozlowski
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-7-f947b24f1283@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-12dt-bindings: clock: qcom,gpucc-sdm660: reference qcom,gcc.yamlKrzysztof Kozlowski
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-6-f947b24f1283@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-12dt-bindings: clock: qcom,dispcc-sm8x50: reference qcom,gcc.yamlKrzysztof Kozlowski
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-5-f947b24f1283@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-12dt-bindings: clock: qcom,dispcc-sm6350: reference qcom,gcc.yamlKrzysztof Kozlowski
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-4-f947b24f1283@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-12dt-bindings: clock: qcom,dispcc-sc8280xp: reference qcom,gcc.yamlKrzysztof Kozlowski
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-3-f947b24f1283@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-12dt-bindings: clock: qcom,videocc: reference qcom,gcc.yamlKrzysztof Kozlowski
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-2-f947b24f1283@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-06-12dt-bindings: clock: qcom,sm8450-videocc: reference qcom,gcc.yamlKrzysztof Kozlowski
Just like most of Qualcomm clock controllers, we can reference common qcom,gcc.yaml schema to unify the common parts of the binding. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240605-dt-bindings-qcom-gcc-v2-1-f947b24f1283@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-31dt-bindings: clock: add schema for qcom,gcc-mdm9615Dmitry Baryshkov
Add schema for the Global Clock Controller (GCC) present on the Qualcomm MDM9615 platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240529-qcom-gdscs-v2-3-69c63d0ae1e7@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-31dt-bindings: clock: qcom,gcc: sort out power-domains supportDmitry Baryshkov
On some of Qualcomm platforms the Global Clock Controller (GCC) doesn't provide power domains. Move requirement for the '#power-domain-cells' out of the common qcom,gcc.yaml into individual schema files. For the platforms that do not provide power-domains, explicitly forbid having the '#power-domain-cells' property. Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240529-qcom-gdscs-v2-2-69c63d0ae1e7@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-31dt-bindings: clock: qcom,gcc-other: rename to qcom,mdm-mdm9607Dmitry Baryshkov
The only platform remaining in qcom,gcc-other.yaml is MDM9607. Drop the stale mentioning of gcc-msm8953.h include and rename the schema file accordingly. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240529-qcom-gdscs-v2-1-69c63d0ae1e7@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-31clk: qcom: camcc-sc7280: Add parent dependency to all camera GDSCsTaniya Das
Camera titan top GDSC is a parent supply to all other camera GDSCs. Titan top GDSC is required to be enabled before enabling any other camera GDSCs and it should be disabled only after all other camera GDSCs are disabled. Ensure this behavior by marking titan top GDSC as parent of all other camera GDSCs. Fixes: 1daec8cfebc2 ("clk: qcom: camcc: Add camera clock controller driver for SC7280") Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240531095142.9688-4-quic_tdas@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-05-31clk: qcom: gcc-sc7280: Update force mem core bit for UFS ICE clockTaniya Das
Update the force mem core bit for UFS ICE clock to force the core on signal to remain active during halt state of the clk. When retention bit of the clock is set the memories of the subsystem will retain the logic across power states. Fixes: a3cc092196ef ("clk: qcom: Add Global Clock controller (GCC) driver for SC7280") Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240531095142.9688-3-quic_tdas@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
generated by cgit (git 2.34.1) at 2025-09-09 13:59:49 +0000