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According to the device tree specification, any bus should have a 'bus'
node name.
Since it isn't the case for us on the DE2 bus, fix that.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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We try to keep the PIO nodes ordered alphabetically, but this doesn't
always work out. Let's fix it.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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The I7 DTS uses an spdif-out property with an "okay" value. However, that
property isn't documented anywhere, and isn't used anywhere either.
Remove it.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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While the USB PHY Device Tree mandates that the name of the ID detect pin
should be usb0_id_det-gpios, a significant number of device tree use
usb0_id_det-gpio instead.
This was functional because the GPIO framework falls back to the gpio
suffix that is legacy, but we should fix this. Commit 2c515b0d05a9
("ARM: sunxi: Fix the USB PHY ID detect GPIO properties") was supposed to
fix this, but one fell through the cracks.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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Some nodes still have pinctrl-names entry, yet they don't have any pinctrl
group anymore. Drop them.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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Various regulators were marked as always-on for Jetson TX2. At this
point, all of the regulators are properly hooked up, so this workaround
is no longer required.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Enable the relevant pads for XUSB support on P2771-0000 and hook up the
USB supply voltage regulators to the ports.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Adds the XUSB pad and XUSB controllers on Tegra186.
Reviewed-by: JC Kuo <jckuo@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The XUSB pad controller is responsible for supplying power to the PLLs
used to drive the various USB, PCI and SATA pads. Move the PLL power
supplies from the PCIe and XUSB controllers to the XUSB pad controller
to make sure they are available when needed.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The XUSB pad controller is responsible for supplying power to the PLLs
used to drive the various USB, PCI and SATA pads. Move the PLL power
supplies from the XUSB controller to the XUSB pad controller to make
sure they are available when needed.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The XUSB pad controller is responsible for supplying power to the PLLs
used to drive the various USB, PCI and SATA pads. Move the PLL power
supplies from the PCIe and XUSB controllers to the XUSB pad controller
to make sure they are available when needed.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The XUSB pad controller is responsible for supplying power to the PLLs
used to drive the various USB, PCI and SATA pads. Move the PLL power
supplies from the PCIe and XUSB controllers to the XUSB pad controller
to make sure they are available when needed.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Parentheses in the SPDX license identifier are only used to group sub-
expressions. If there's no need for such grouping, the parentheses can
be omitted.
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Replace boiler plate licenses texts with the SPDX license identifiers in
Colibri/Apalis DTS files.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
[treding@nvidia.com: drop unneeded parentheses, keep license at X11]
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The Jetson Nano Developer Kit is a Tegra X1 based development board. It
is similar to Jetson TX1 but it is not pin compatible. It features 4 GB
of LPDDR4, an SPI NOR flash for early boot firmware and an SD card slot
used for storage.
HDMI 2.0 or DP 1.2 are available for display, four USB ports (3 USB 2.0
and 1 USB 3.0) can be used to attach a variety of peripherals and a PCI
Ethernet controller provides onboard network connectivity. An M.2 Key-E
slot with PCIe x1 adds additional possibilities.
A 40-pin header on the board can be used to extend the capabilities and
exposed interfaces of the Jetson Nano.
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The XUSB pad controller is responsible for supplying power to the PLLs
used to drive the various USB, PCI and SATA pads. Move the PLL power
supplies from the PCIe and XUSB controllers to the XUSB pad controller
to make sure they are available when needed.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The XUSB pad controller is responsible for supplying power to the PLLs
used to drive the various USB, PCI and SATA pads. Move the PLL power
supplies from the PCIe and XUSB controllers to the XUSB pad controller
to make sure they are available when needed.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Neither the OHCI or EHCI bindings are using the phy-names property, so we
can just drop it.
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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Neither the OHCI or EHCI bindings are using the phy-names property, so we
can just drop it.
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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Neither the OHCI or EHCI bindings are using the phy-names property, so we
can just drop it.
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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The Odroid-C1 has the 32.768 kHz oscillator (X3 in the schematics) which
is required for the RTC. A battery can be connected separately (to the
BT1 header) - then the "rtc" node can be enabled manually. By default
the RTC is disabled because the boards typically come without the RTC
battery.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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The RTC is always enabled on this board since the battery is already
connected in the factory.
According to the schematics the VCC_RTC regulator (which is either
powered by the internal 3.3V or a battery) is connected to the 0.9V
RTC_VDD input of the SoCs.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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The 32-bit Meson SoCs have an RTC block in the AO (always on) area. The
RTC requires an external 32.768 kHz oscillator to work properly. Whether
or not this crystal exists depends on the board, so it has to be added
for each board.dts (instead of adding it somewhere in a generic .dtsi).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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This patch adds the HDMI, CVBS and CEC attributes and nodes to support
full display on the U200 Reference Design.
AO-CEC-B is used by default and AO-CEC-A is disabled.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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This patch adds the HDMI, CVBS and CEC attributes and nodes to support
full display on the SEI510 STB.
AO-CEC-B is used by default and AO-CEC-A is disabled.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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This patch adds the HDMI, CVBS and CEC attributes and nodes to support
full display on the X96 Max STB.
AO-CEC-B is used by default and AO-CEC-A is disabled.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Amlogic G12A embeds 2 CEC controllers :
- AO-CEC-A the same controller as in GXBB, GXL & GXM SoCs
- AO-CEC-B is a new controller
Note, the two controller can work simultanously since 2 Pads can
handle CEC, thus this SoC can handle 2 distinct CEC busses.
This patch adds the nodes for the AO-CEC-A and AO-CEC-B controllers.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Add VPU and HDMI display support.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Enable the USB2 and USB3 Host ports on the X96 Max Set-Top-Box.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Enable the USB2 OTG and USB3 Host ports on the S905D2 Reference Design.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Enable the USB2 and USB3 Host ports on the SEI520 Set-Top-Box.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Add support for the :
- ADC Touch key
- Bluetooth Module on UART A
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Add system regulators for the S905D U200 reference design.
Add some regulators. Still missing
* VDD_EE (0.8V - PWM controlled)
* VDD_CPU (PWM controlled)
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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This patch adds the ARM Mali G31 GPU node.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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This patch adds the nodes for the USB Complex found in the Amlogic
G12A SoC.
It includes the :
- 2 USB2 PHYs
- 1 USB3 + PCIE Combo PHY
- the USB Glue with it's DWC2 and DWC3 sub-nodes
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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This patch adds the SAR ADC controller node.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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v5.2/dt64
* 'reset/meson-g12a' of git://git.pengutronix.de/pza/linux:
dt-bindings: reset: meson-g12a: Add missing USB2 PHY resets
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into v5.2/dt64
- Adds VPU and Video Decoder clocks IDs on Meson8b
- Finally remove the wrong ABP Meson8b clock id
- Adds Video Decoder, PCIe PLL & CPU Clock IDs on G12A
- Re-expose SAR_ADC_SEL and CTS_OSCIN on G12A AO clock controller
- Unexpose some AXG-Audio input clocks IDs
* tag 'meson-clk-headers-5.2' of git://github.com/BayLibre/clk-meson:
dt-bindings: clock: meson8b: export the video decoder clocks
dt-bindings: clock: meson8b: export the VPU clock
dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCIN
dt-bindings: clock: meson8b: drop the "ABP" clock definition
dt-bindings: clk: g12a-clkc: add VDEC clock IDs
dt-bindings: clock: axg-audio: unexpose controller inputs
dt-bindings: clk: g12a-clkc: add PCIE PLL clock ID
clk: g12a-aoclk: re-export CLKID_AO_SAR_ADC_SEL clock id
clk: meson-g12a: add cpu clock bindings
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The Amlogic G12A has a slighly different Power Control, but uses the
same address space and sysctrl registers.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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The defines are taken from dt-bindings/pinctrl/am33xx.h
Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The defines are taken from dt-bindings/pinctrl/am33xx.h
Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The defines are taken from dt-bindings/pinctrl/am33xx.h
Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The defines are taken from dt-bindings/pinctrl/am33xx.h
Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The defines are taken from dt-bindings/pinctrl/am33xx.h
Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The defines are taken from dt-bindings/pinctrl/am33xx.h
Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The defines are taken from dt-bindings/pinctrl/am33xx.h
Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The defines are taken from dt-bindings/pinctrl/am33xx.h
Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The defines are taken from dt-bindings/pinctrl/am33xx.h
Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The defines are taken from dt-bindings/pinctrl/am33xx.h
Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The defines are taken from dt-bindings/pinctrl/am33xx.h
Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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