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2019-04-12arm64: tegra: Enable CPU idle support for ShieldJoseph Lo
Enable CPU idle support for Shield platform. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-12arm64: tegra: Enable CPU idle support for SmaugJoseph Lo
Enable CPU idle support for Smaug platform. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-12arm64: tegra: Enable CPU idle support for Jetson TX1Joseph Lo
Enable CPU idle support for Jetson TX1 platform. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-12arm64: tegra: Add CPU idle states properties for Tegra210Joseph Lo
Add idle states properties for generic ARM CPU idle driver. This includes a cpu-sleep state which is the power down state of CPU cores. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-12arm64: tegra: Fix timer node for Tegra210Joseph Lo
Fix timer node to make it work with Tegra210 timer driver. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-12ARM: dts: iwg23s-sbc: Enable HS-USBBiju Das
Enable HS-USB device for the iWave SBC based on RZ/G1C. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12ARM: dts: r8a77470: Add HSUSB device nodesBiju Das
Define the r8a77470 generic part of the HSUSB0/1 device nodes. Currently the renesas_usbhs driver doesn't handle multiple phys and we don't have a proper hardware to validate such driver changes. So for hsusb1 it is assumed that usbphy0 will be enabled by either channel0 host or device. In future, if any boards support hsusb1, we will need to add multiple phy support in the renesas_usbhs driver and override the board dts to enable the same. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12ARM: dts: iwg23s-sbc: Enable USB USB2.0 HostBiju Das
Enable USB2.0 host on the iwg23s sbc. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12ARM: dts: r8a77470: Add USB2.0 Host (EHCI/OHCI) deviceBiju Das
Define the r8a77470 generic part of the USB2.0 Host Controller device nodes (ehci[01]/ohci[01]). Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12ARM: dts: iwg23s-sbc: Enable USB Phy[01]Biju Das
Enable USB phy[01] on iWave iwg23s sbc based on RZ/G1C SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12ARM: dts: r8a77470: Add USB PHY DT supportBiju Das
Define the r8a77470 generic part of the USB PHY device node. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12ARM: dts: r8a77470: Add VIN supportCao Van Dong
Add vin{0|1} nodes to dtsi for VIN support on the RZ/G1C (r8a77470) SoC. Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12ARM: dts: r8a77470: Add PWM supportCao Van Dong
Add pwm{0|1|2|3|4|5|6} nodes to dtsi for PWM support on the RZ/G1C (r8a77470) SoC. Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12ARM: dts: r8a77470: Add HSCIF supportCao Van Dong
Add hscif{0|1|2} nodes to dtsi for HSCIF support on the RZ/G1C (r8a77470) SoC. Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-11ARM: dts: stm32: enable cec on stm32mp157a-dk1 boardYannick Fertré
Enable CEC (Consumer Electronics Control) device. Signed-off-by: Yannick Fertré <yannick.fertre@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: add cec pins muxing on stm32mp157Yannick Fertré
Add a new pin muxing for cec. Signed-off-by: Yannick Fertré <yannick.fertre@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: add ltdc pins muxing on stm32mp157Yannick Fertré
Add ltdc pins muxing on stm32mp157. Signed-off-by: Yannick Fertré <yannick.fertre@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: add I2C sleep pins muxing on stm32mp157Yannick Fertré
Add I2C sleep pins muxing for low power mode. Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com> Signed-off-by: Yannick Fertré <yannick.fertre@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: add power supply of otm8009a on stm32mp157c-dk2Yannick Fertré
This patch adds a new property (power-supply) to panel otm8009a (orisetech) on stm32mp157c-dk2 & regulator v3v3. Signed-off-by: Yannick Fertré <yannick.fertre@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: Enable STM32F769 clock driverGabriel Fernandez
This patch enables clocks for STM32F769 boards. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: add stpmic1 support on stm32mp157a dk1 boardPascal Paillet
This patch adds stpmic1 support on stm32mp157a dk1 board. The STPMIC1 is a PMIC from STMicroelectronics. The STPMIC1 integrates 10 regulators, 3 power switches, a watchdog and an input for a power on key. The DMAs are disabled because the PMIC generates a very few traffic and DMA channels may lack for other usage. Signed-off-by: Pascal Paillet <p.paillet@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: add stpmic1 support on stm32mp157c ed1 boardPascal Paillet
This patch adds stpmic1 support on stm32mp157c ed1 board. The STPMIC1 is a PMIC from STMicroelectronics. The STPMIC1 integrates 10 regulators, 3 power switches, a watchdog and an input for a power on key. The DMAs are disabled because the PMIC generates a very few traffic and DMA channels may lack for other usage. Signed-off-by: Pascal Paillet <p.paillet@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: add spdfirx pins to stm32mp157cOlivier Moysan
This patch adds spdifrx support on stm32mp157c eval board. Signed-off-by: Olivier Moysan <olivier.moysan@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: add spdifrx support on stm32mp157cOlivier Moysan
This patch adds support of STM32 SPDIFRX on stm32mp157c. Signed-off-by: Olivier Moysan <olivier.moysan@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: Add romem and temperature calibration on stm32f429Fabrice Gasnier
Add & enable stm32 factory-programmed memory. Describe temperature sensor calibration cells. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: Add romem and temperature calibration on stm32mp157cFabrice Gasnier
Add & enable stm32 factory-programmed memory. Describe temperature sensor calibration cells. Non-volatile calibration data is made available by stm32mp157c bootrom in bsec_dataX registers. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: Add clock on stm32mp157c syscfgFabrice Gasnier
STM32 syscfg needs a clock to access registers. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: enable IPCC mailbox support on STM32MP157a-dk1Fabien Dessenne
Enable STM32 IPCC mailbox driver for STM32MP157a-dk1 board. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: enable IPCC mailbox support on STM32MP157c-ed1Fabien Dessenne
Enable STM32 IPCC mailbox driver for STM32MP157c-ed1 board. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: add IPCC mailbox support on STM32MP157cFabien Dessenne
Add configuration on DT for IPCC mailbox driver. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: add sdmmc1 support on stm32mp157a dk1 boardLudovic Barre
This patch adds sdmmc1 support on stm32mp157a dk1 board. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: add sdmmc1 support on stm32mp157c ed1 boardLudovic Barre
This patch adds sdmmc1 support on stm32mp157c ed1 board. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: add sdmmc1 support on stm32mp157cLudovic Barre
This patch adds support of sdmmc1 on stm32mp157c. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: add sdmmc1 support on stm32h743i disco boardLudovic Barre
This patch adds sdmmc1 support on stm32h743i disco board. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: add sdmmc1 support on stm32h743i eval boardLudovic Barre
This patch adds sdmmc1 support on stm32h743i eval board. This board has an external driver to control signal direction polarity. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11ARM: dts: stm32: add sdmmc1 support on stm32h743Ludovic Barre
This patch adds support of sdmmc1 on stm32h743. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-10ARM: dts: exynos: Remove console argument from bootargsKrzysztof Kozlowski
Remove the "console=ttySAC..." argument from DTSes having a proper stdout-path property. To make the code functionally equivalent, add the serial port baud rate and parity. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2019-04-10ARM: dts: exynos: Use stdout-path property instead of console in bootargsKrzysztof Kozlowski
Replacing bootargs with stdout-path property in chosen node allows using early console by adding just 'earlycon' parameter to the kernel command line. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2019-04-10ARM: dts: sun5i: Add the MBUS controllerMaxime Ripard
The MBUS (and its associated controller) is the bus in the Allwinner SoCs that DMA devices use in the system to access the memory. Among other things (and depending on the SoC generation), it can also enforce priorities or report bandwidth usages on a per-master basis. One of the most notable thing is that instead of having the same mapping for the RAM than the CPU, it maps it at address 0, which means we'll have to do address translation thanks to the dma-ranges property. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-10arm64: dts: renesas: r8a77990: Add CMT device nodesCao Van Dong
This patch adds CMT{0|1|2|3} device nodes for r8a77990 SoC. Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-10arm64: dts: renesas: r8a77965: Add CMT device nodesCao Van Dong
This patch adds CMT{0|1|2|3} device nodes for r8a77965 SoC. Tested-by: Cao Van Dong <cv-dong@jinso.co.jp> Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-10arm64: dts: renesas: r8a7795: Add CMT device nodesCao Van Dong
This patch adds CMT{0|1|2|3} device nodes for r8a7795 SoC. Tested-by: Cao Van Dong <cv-dong@jinso.co.jp> Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-09ARM: dts: Add l4 abe interconnect hierarchy and ti-sysc data for omap5Tony Lindgren
We can now add l4 abe interconnect hierarchy and ti-sysc data with ti-sysc driver supporting external optional clocks needed by mcpdm. This data is generated based on platform data from a booted system and the interconnect acces protection registers for ranges. To avoid regressions, we initially validate the device tree provided data against the existing platform data on boot. Note that mcpdm we now need to enable at module level only for devices that have the external pdmclk wired from the PMIC as the clock is needed for the module to be accessible. Also note that abe seems to be the same as on omap4 except for domains and clocks and we may be able to combine the l4 abe data later on. But let's play it safe and just initially use what we have already defined in the platform data. Cc: devicetree@vger.kernel.org Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-09ARM: dts: Add l4 abe interconnect hierarchy and ti-sysc data for omap4Tony Lindgren
We can now add l4 abe interconnect hierarchy and ti-sysc data with ti-sysc driver supporting external optional clocks needed by mcpdm. This data is generated based on platform data from a booted system and the interconnect acces protection registers for ranges. To avoid regressions, we initially validate the device tree provided data against the existing platform data on boot. Note that mcpdm we now need to enable at module level only for devices that have the external pdmclk wired from the PMIC as the clock is needed for the module to be accessible. Cc: devicetree@vger.kernel.org Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-09ARM: dts: Add common mcpdm dts file for omap4Tony Lindgren
The mcpdm module found on omap4 and 5 needs pdmclk clock from the pmic that may or may not be wired. Without this clock we cannot read the registers for mcpdm at all. For the external mcpdm clock to work, it needs to be muxed at the module level for ti-sysc driver probe to mux it early enough for probe. Let's set up a common file for it to make things a bit easier to make l4 abe interconnect to probe with ti-sysc driver. Note that this is not needed for omap5 as we can just update mcpdm muxing in omap5-board-common.dtsi in later patches. Cc: devicetree@vger.kernel.org Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-09bus: ti-sysc: Add generic enable/disable functionsRoger Quadros
For non legacy cases, add generic sysc_enable_module() and sysc_disable_module() functions. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-09ARM: dts: omap2420-n810: Use new CODEC reset pin nameAndrew F. Davis
The correct DT property for specifying a GPIO used for reset is "reset-gpios", the driver now accepts this name, use it here. Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-09ARM: dts: am43xx-epos-evm: Add matrix keypad as wakeup sourceAndrew F. Davis
Mark matrix-keypad as a wakeup source. Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-09ARM: dts: am43xx-epos-evm: Keep DCDC3 regulator on in suspend to memoryMike Erdahl
When going to suspend to ram mode (or rtc-only mode), the DDR regulator must be told to stay on, else this rail will go down when the PMIC_EN signal is deasserted. Signed-off-by: Mike Erdahl <m-erdahl@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-09ARM: dts: am43xx-epos-evm: Keep DCDC5 and DCDC6 always onKabir Sahane
These regulator outputs are needed even in deep sleep modes to prevent low-voltage detection events. Make these always ON to avoid this. Signed-off-by: Kabir Sahane <x0153567@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
generated by cgit (git 2.34.1) at 2025-09-11 04:20:56 +0000