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2015-06-01ARM: dts: AM35xx: fix system control module clocksTero Kristo
New system control module layout for omap3 overlooked parts of the am35xx configuration. Basically the am35xx clocks were not converted to use the changed offsets, which caused weird boot warnings. The errors were not fatal so far, so they were not caught earlier. Fixed by applying the proper offsets for the AM35xx scm clocks. Fixes: b8845074cf ("ARM: dts: omap3: add minimal l4 bus layout with...") Signed-off-by: Tero Kristo <t-kristo@ti.com> Reported-by: Jeroen Hofstee <linux-arm@myspectrum.nl> Cc: Paul Walmsley <paul@pwsan.com> Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-06-01Merge tag 'v4.1-next-arm64-fixes' of https://github.com/mbgg/linux-mediatek ↵Arnd Bergmann
into fixes - dts: mt8173: fix compatible string * tag 'v4.1-next-arm64-fixes' of https://github.com/mbgg/linux-mediatek: arm64: dts: mt8173-evb: fix model name
2015-06-01Merge tag 'samsung-fixes-4.1-4' of https://github.com/krzk/linux into fixesArnd Bergmann
Merge "ARM: EXYNOS: Fix for 4.1, 4th" from Krzysztof Kozlowski: Fix for Exynos3250 RTC wake-up interrupts after converting PMU wakeup to stacked domains. This allows waking up the device from suspend to RAM using S3C RTC driver (the RTC on SoC). The patch should be applied some time ago, unfortunately it seems it slipped through fingers. * tag 'samsung-fixes-4.1-4' of https://github.com/krzk/linux: ARM: exynos: Fix wake-up interrupts for Exynos3250
2015-06-01Merge tag 'mvebu-fixes-4.1-3' of git://git.infradead.org/linux-mvebu into fixesArnd Bergmann
Merge "mvebu fixes for 4.1 (part 3)" from Gregory CLEMENT: Disable unused internal RTC for Mamba from linksys (Armada XP) And 2 commits fixing regressions on mvebu-mbus: - the first one for Kirkwood or Orion SoC - the second one for DMA when the platform have more than 4GB (only possible on Armada XP as far as I know) * tag 'mvebu-fixes-4.1-3' of git://git.infradead.org/linux-mvebu: Revert "bus: mvebu-mbus: make sure SDRAM CS for DMA don't overlap the MBus bridge window" bus: mvebu-mbus: do not set WIN_CTRL_SYNCBARRIER on non io-coherent platforms. ARM: mvebu: armada-xp-linksys-mamba: Disable internal RTC
2015-06-01Merge tag 'v4.1-next-soc' of https://github.com/mbgg/linux-mediatek into fixesArnd Bergmann
These are bug fixes for mediatek, fixing code that was recently introduced. - pmic wrapper: fix clock handling - pmic wrapper: fix state machine - pmic wrapper: fix compile dependency * tag 'v4.1-next-soc' of https://github.com/mbgg/linux-mediatek: soc: mediatek: Add compile dependency to pmic-wrapper soc: mediatek: PMIC wrap: Fix register state machine handling soc: mediatek: PMIC wrap: Fix clock rate handling
2015-06-01gpio: pcf857x: Check for irq_set_irq_wake() failuresGeert Uytterhoeven
If an interrupt controller doesn't support wake-up configuration, irq_set_irq_wake() returns an error code. Then any subsequent call trying to deconfigure wake-up will cause an imbalance, and a warning will be printed: WARNING: CPU: 1 PID: 1341 at kernel/irq/manage.c:540 irq_set_irq_wake+0x Unbalanced IRQ 26 wake disable To fix this, refrain from any further parent interrupt controller (de)configuration if irq_set_irq_wake() failed. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-01gpio-stp-xway: Fix enabling the highest bit of the PHY LEDsMartin Blumenstingl
0x3 only masks two bits, but three bits have to be allowed. This fixes GPHY0 LED2 (which is the highest bit of phy2) on my board. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: John Crispin <blogic@openwrt.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-01gpio: Prevent an integer overflow in the pca953x driverJoshua Scott
Interrupts were missed if an 8-bit integer overflow occurred. This was observed when bank0,pin7 and bank1,pin7 changed simultaniously. As the 8-bit totals were only checked against zero, replace them with booleans. Name the booleans so that their purpose is clear. Signed-off-by: Joshua Scott <joshua.scott@alliedtelesis.co.nz> Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-01gpio: omap: rework omap_gpio_irq_startup to handle current pin state properlyGrygorii Strashko
The omap_gpio_irq_startup() can be called at time when: - corresponding GPIO has been requested already and in this case it has to be configured as input already. If not - return with -EINVAL and do not try to re-configure it as it could be unsafe. - corresponding GPIO is free: reconfigure GPIO as input. In addition, call omap_enable_gpio_module directly as all needed checks are already present inside it. Signed-off-by: Grygorii Strashko <grygorii.strashko@linaro.org> Tested-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-01gpio: omap: rework omap_gpio_request to touch only gpio specific registersGrygorii Strashko
The GPIO Chip and GPIO IRQ Chip functionality are essentially orthogonal, so GPIO Chip implementation shouldn't touch GPIO IRQ specific registers and vise versa. Hence, rework omap_gpio_request: - don't reset GPIO IRQ triggering type to IRQ_TYPE_NONE, because GPIO irqchip should be responsible for that; - call directly omap_enable_gpio_module as all needed checks are already present inside it. Signed-off-by: Grygorii Strashko <grygorii.strashko@linaro.org> Tested-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-01gpio: omap: rework omap_x_irq_shutdown to touch only irqs specific registersGrygorii Strashko
The GPIO Chip and GPIO IRQ Chip functionality are essentially orthogonal, so GPIO IRQ Chip implementation shouldn't touch GPIO specific registers and vise versa. Hence, rework omap_gpio_irq_shutdown and try to touch only irqs specific registers: - don't configure GPIO as input (it, actually, should be already configured as input). - don't clear debounce configuration if GPIO is still used as GPIO. We need to take in to account here commit c9c55d921115 ("gpio/omap: fix off-mode bug: clear debounce settings on free/reset"). Also remove omap_reset_gpio() function as it is not used any more. Signed-off-by: Grygorii Strashko <grygorii.strashko@linaro.org> Tested-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-01gpio: omap: fix error handling in omap_gpio_irq_typeGrygorii Strashko
The GPIO bank will be kept powered in case if input parameters are invalid or error occurred in omap_gpio_irq_type. Hence, fix it by ensuring that GPIO bank will be unpowered in case of errors and add additional check of value returned from omap_set_gpio_triggering(). Signed-off-by: Grygorii Strashko <grygorii.strashko@linaro.org> Tested-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-01gpio: omap: fix omap_gpio_free to not clean up irq configurationGrygorii Strashko
This patch fixes following issue: - GPIOn is used as IRQ by some dev, for example PCF8575.INT -> gpio6.11 - PCFx driver knows nothing about type of IRQ line (GPIO or not) so it doesn't request gpio and just do request_irq() - If gpio6.11 will be exported through the sysfs and then un-xeported then IRQs from PCFx will not be received any more, because IRQ configuration for gpio6.11 will be cleaned up unconditionally in omap_gpio_free. Fix this by removing all GPIO IRQ specific code from omap_gpio_free() and also do GPIO clean up (change direction to 'in' and disable debounce) only if corresponding GPIO is not used as IRQ too. GPIO IRQ will be properly cleaned up by GPIO irqchip code. Signed-off-by: Grygorii Strashko <grygorii.strashko@linaro.org> Tested-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-01include/uapi/linux/virtio_balloon.h: include linux/virtio_types.hMikko Rapeli
Fixes userspace compilation error: error: unknown type name ‘__virtio16’ __virtio16 tag; Signed-off-by: Mikko Rapeli <mikko.rapeli@iki.fi> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2015-06-01perf tools: Remove newline char when reading event scale and unitMadhavan Srinivasan
The <fd979c013207> commit intruduced the perf_event_sysfs_show function to display the event_str value of an attr in kernel/event/core.c. But the function returns the value with a newline char. So, if a event also carries a event.unit file, when printing the counter data perf tool formatting goes for a spin. That is, because of the event unit, event name is printed in the newline because of perf_event_sysfs_show returns with a newline char. Now fixing perf core will break API, hencing proposing a fix in the perf tool. Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Link: http://lkml.kernel.org/r/1433052383-21802-1-git-send-email-maddy@linux.vnet.ibm.com [ Add spaces around operators ] Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2015-06-01gpio: rcar: Check for irq_set_irq_wake() failuresGeert Uytterhoeven
If an interrupt controller doesn't support wake-up configuration, irq_set_irq_wake() returns an error code. Then any subsequent call trying to deconfigure wake-up will cause an imbalance, and a warning will be printed: WARNING: CPU: 1 PID: 1341 at kernel/irq/manage.c:540 irq_set_irq_wake+0x9c/0xf8() Unbalanced IRQ 26 wake disable To fix this, refrain from any further parent interrupt controller (de)configuration if irq_set_irq_wake() failed. Alternative fixes would be: - calling "gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE)" from the platform code, - setting "gic_chip.flags = IRQCHIP_SKIP_SET_WAKE" in the GIC driver code, but these were withheld as the GIC hardware doesn't really support wake-up interrupts. Fixes: ab82fa7da4dce5c7 ("gpio: rcar: Prevent module clock disable when wake-up is enabled") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-01gpiolib: rename gpiod_set_array to gpiod_set_array_valueRojhalat Ibrahim
There have been concerns that the function names gpiod_set_array() and gpiod_get_array() might be confusing to users. One might expect gpiod_get_array() to return array values, while it is actually the array counterpart of gpiod_get(). To be consistent with the single descriptor API we could rename gpiod_set_array() to gpiod_set_array_value(). This makes some function names a bit lengthy: gpiod_set_raw_array_value_cansleep(). Signed-off-by: Rojhalat Ibrahim <imr@rtschenk.de> Acked-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-01arm64: dts: mt8173-evb: fix model nameYingjoe Chen
Model name in mt8173-evb.dts doesn't follow dts convention (it should be human readable model name). Fix it. Fixes: b3a372484157 ("arm64: dts: Add mediatek MT8173 SoC and evaluation board dts and Makefile") Cc: <stable@vger.kernel.org> # v4.0+ Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-06-01MIPS: ralink: Fix clearing the illegal access interruptJonas Gorski
Due to a typo the illegal access interrupt is never cleared in by the interupt handler, causing an effective deadlock on the first illegal access. This was broken since the code was introduced in 5433acd81e87 ("MIPS: ralink: add illegal access driver"), but only exposed when the Kconfig symbol was added, thus enabling the code. Cc: <stable@vger.kernel.org> [3.18+] Fixes: a7b7aad383c ("MIPS: ralink: add missing symbol for RALINK_ILL_ACC") Signed-off-by: Jonas Gorski <jogo@openwrt.org> Cc: linux-mips@linux-mips.org Cc: John Crispin <blogic@openwrt.org> Patchwork: https://patchwork.linux-mips.org/patch/10172/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-01m68k: Use for_each_sg()Akinobu Mita
This replaces the plain loop over the sglist array with for_each_sg() macro which consists of sg_next() function calls. Since m68k doesn't select ARCH_HAS_SG_CHAIN, it is not necessary to use for_each_sg() in order to loop over each sg element. But this can help find problems with drivers that do not properly initialize their sg tables when CONFIG_DEBUG_SG is enabled. Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: linux-m68k@lists.linux-m68k.org Cc: linux-arch@vger.kernel.org Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2015-06-01m68k/defconfig: Update defconfigs for v4.1-rc6Geert Uytterhoeven
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2015-06-01mmc: sdhci-bcm2835: Actually enable the clockEric Anholt
We're currently using a fixed frequency clock specified in the DT, so enabling is a no-op. However, the RPi firmware-based clocks driver can actually disable unused clocks, so when switching to use it we ended up losing our MMC clock once all devices were probed. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-06-01mmc: sdhci-bcm2835: Clean up platform allocations if sdhci init fails.Eric Anholt
Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-06-01drm/i915: Don't skip request retirement if the active list is emptyVille Syrjälä
Apparently we can have requests even if though the active list is empty, so do the request retirement regardless of whether there's anything on the active list. The way it happened here is that during suspend intel_ring_idle() notices the olr hanging around and then proceeds to get rid of it by adding a request. However since there was nothing on the active lists i915_gem_retire_requests() didn't clean those up, and so the idle work never runs, and we leave the GPU "busy" during suspend resulting in a WARN later. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@vger.kernel.org Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2015-06-01drm/i915/hsw: Fix workaround for server AUX channel clock divisorJim Bride
According to the HSW b-spec we need to try clock divisors of 63 and 72, each 3 or more times, when attempting DP AUX channel communication on a server chipset. This actually wasn't happening due to a short-circuit that only checked the DP_AUX_CH_CTL_DONE bit in status rather than checking that the operation was done and that DP_AUX_CH_CTL_TIME_OUT_ERROR was not set. [v2] Implemented alternate solution suggested by Jani Nikula. Cc: stable@vger.kernel.org Signed-off-by: Jim Bride <jim.bride@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2015-06-01mmc: sdhci-of-esdhc: enable interrupt mode to detect cardYangbo Lu
Enable interrupt mode to detect card instead of polling mode for P1020/P4080/P5020/P5040/T1040 by removing the quirk SDHCI_QUIRK_BROKEN_CARD_DETECTION. This could improve data transferring performance and avoid the call trace caused by polling card status sometime. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-06-01mmc: sdhci-esdhc-imx: add quirk SDHCI_QUIRK2_BROKEN_HS200 for imx6qdlDong Aisheng
The iMX6Q/DL can not support HS200 mode while iMX6SL and iMX6SX can, so introduce a new flag to distinguish them. Signed-off-by: Dong Aisheng <aisheng.dong@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-06-01mmc: sdhci-esdhc-imx: add imx6sx supportDong Aisheng
The imx6sx usdhc is derived from imx6sl, the difference is minor. imx6sx have the errata ESDHC_FLAG_ERR004536 fixed. So introduce a new compatible string for imx6sx to distinguish them. Signed-off-by: Dong Aisheng <b29396@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-06-01mmc: sdhci-esdhc-imx: using specific compatible string in binding docDong Aisheng
Using specific compatible string in binding doc to make the binding more clear. It's also used to avoid checkpatch warning in the future like follows: WARNING: DT compatible string "fsl,imx6sx-usdhc" appears un-documented -- check ./Documentation/devicetree/bindings/ + { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, }, total: 0 errors, 1 warnings, 18 lines checked Signed-off-by: Dong Aisheng <b29396@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-06-01mmc: sdhci-esdhc-imx: add ADMA Length Mismatch errata fixDong Aisheng
The uSDHC has an ADMA Length Mismatch errata ERR004536 which may cause ADMA work abnormally. The errata has already been fixed for i.MX6Q TO1.2 and i.MX6DL TO1.1 by enable the bit 7 in 0x6c register. Unfortunately this fix is not included in i.MX6SL. So we disable ADMA for i.MX6SL and use SDMA instead. Signed-off-by: Dong Aisheng <aisheng.dong@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-06-01mmc: sdhci-esdhc-imx: usdhc does not have missing card interrupt issueDong Aisheng
The usdhc does not have missing card interrupt issue, so don't execute workaround for usdhc. Signed-off-by: Dong Aisheng <aisheng.dong@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-06-01mmc: sdhci-esdhc-imx: merge the same register check into one placeDong Aisheng
In esdhc_writel_le() function, there's duplicated checking of the same register as follows: "if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE))". Merge them into one and remove the duplicated one. Signed-off-by: Dong Aisheng <aisheng.dong@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-06-01mmc: sdhci-pci: Enable HS400 for some Intel host controllersAdrian Hunter
Enable detection of HS400 support via capability bit-63 for some Intel host controllers. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-06-01mmc: sdhci-pci: Add support for drive strength selection for SPTAdrian Hunter
Implement the select_drive_strength callback to provide drive strength selection for Intel SPT. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-06-01mmc: sdhci: Add a callback to select drive strengthAdrian Hunter
Add a callbak to let host drivers select drive strength. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-06-01mmc: mmc: Add driver strength selectionAdrian Hunter
Add the ability to set eMMC driver strength for HS200 and HS400. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-06-01mmc: mmc: Read card's valid driver strength maskAdrian Hunter
In preparation for supporing drive strength selection for eMMC, read the card's valid driver strengths. Note that though the SD spec uses the term "drive strength", the JEDEC eMMC spec uses the term "driver strength". Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-06-01mmc: core: Record card drive strengthAdrian Hunter
In preparation for adding drive strength support for eMMC, add drive_strength to struct mmc_card to record the card drive strength for UHS-I modes and HS200 / HS400. For eMMC this will be needed when switching between HS200 and HS400. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-06-01mmc: core: Factor out common code in drive strength selectionAdrian Hunter
Make a new function out of common code used for drive strength selection. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-06-01mmc: core: Add 'card' to drive strength selection callbackAdrian Hunter
In preparation for supporting also eMMC drive strength, add the 'card' as a parameter so that the callback can distinguish different types of cards if necessary. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-06-01mmc: core: Simplify card drive strength maskAdrian Hunter
Card drive strength selection uses a callback to which a mask of supported drive strengths is passed. Currently, the bits are checked against the values in the SD specifications. That is not necessary because the callback will anyway match the mask against a valid value. Simplify by taking the mask as is but still ensuring that the default mandatory value (type B) is always supported. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-06-01mmc: core: Allow card drive strength to be different to hostAdrian Hunter
Initialization of UHS-I modes for SD and SDIO cards employs a callback to allow the host driver to choose a drive strength value. Currently that assumes the card drive strength and host driver type must be the same value. Change to let the callback make that decision and return both the card drive strength and host driver type. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-06-01mmc: core: Reset driver type to defaultAdrian Hunter
IO state variable drv_type could be set during card initialization. Consequently, it must be reset to the default value when setting the initial state. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-06-01mmc: sh_mmcif: calculate best clock with parent clockKuninori Morimoto
MMCIF IP on R-Car series has parent clock which can be set several rate, and it was not implemented on old SH-Mobile series (= SH-Mobile series parent clock was fixed rate) R-Car series MMCIF can use more high speed access if it setups parent clock. This patch adds parent clock setup method. It will be used if DT has "max-frequency", and then, this driver assumes it is booted on R-Car Gen2 or later SoC. Because SH-Mobile series (which doesn't boot from DT) and R-Car series (which boots from DT) have different divider. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> [Ulf: Silence compiler warning]
2015-06-01mmc: sh_mmcif: use sh_mmcif_xxx prefix for all functionsKuninori Morimoto
Current sh_mmcif driver is using sh_mmcif_xxx and mmcif_xxx for functions. This patch used sh_mmcif_xxx for all functions. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-06-01mmc: sh_mmcif: add sh_mmcif_host_to_dev() macro and use it.Kuninori Morimoto
Current sh_mmcif driver is directly using &host->pd->dev in all place. It is not big problem, but it is unreadable, and it can be cause of future bug. This patch adds new sh_mmcif_host_to_dev() and use it. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-06-01mmc: sdhci: fix driver type B and D handling in sdhci_do_set_ios()Petri Gynther
sdhci_do_set_ios() doesn't currently program SDHCI_HOST_CONTROL2 register correctly when host->preset_enabled == false. Add code to handle the missing cases MMC_SET_DRIVER_TYPE_B and MMC_SET_DRIVER_TYPE_D. Signed-off-by: Petri Gynther <pgynther@google.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-06-01powerpc/dts: add eSDHC compatible listYangbo Lu
Add eSDHC compatible list for P2041/P3041/P4080/P5020/P5040. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-06-01mmc: mmc-test: use swap() in mmc_test_nonblock_transfer()Fabian Frederick
Use kernel.h macro definition. Signed-off-by: Fabian Frederick <fabf@skynet.be> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-06-01mmc: core: Increase delay for voltage to stabilize from 3.3V to 1.8VDoug Anderson
Since the regulator used for the SDMMC IO voltage is not expected to draw a lot of current, most systems will probably use an inexpensive LDO for it. LDO regulators apparently have the feature that they don't actively drive the voltage down--they wait for other components in the system to drag the voltage down. Thus they will transition faster under heavy loads and slower under light loads. During an SDMMC voltage change from 3.3V to 1.8V, we are almost certainly under a light load. To be specific: * The regulator is hooked through pulls to CMD0-3 and DAT. Probably the CMD pulls are something like 47K and the DAT is something like 10K. * The card is supposed to be driving DAT0-3 low during voltage change which will draw _some_ current, but not a lot. * The regulator is also provided to the SDMMC host controller, but the SDMMC host controller is in open drain mode during the voltage change and so shouldn't be drawing much current. In order to keep the SDMMC host working properly (or for noise reasons), there might also be a capacitor attached to the SDMMC IO regulator. This also will have the effect of slowing down transitions of the regulator, especially under light loads. From experimental evidence, we've seen the voltage change fail if the card doesn't detect that the voltage fell to less than about 2.3V when we turn on the clock. On one device (that admittedly had a 47K CMD pullup instead of a 10K CMD pullup) we saw that the voltage was just about 2.3V after 5ms and thus the voltage change would sometimes fail. Doubling the delay gave margin and made the voltage change work 100% of the time, despite the slightly weaker CMD pull. At the moment submitting this as an RFC patch since my problem _could_ be fixed by increasing the pull strength (or using a smaller capacitor). However being a little bit more lenient to strange hardware could also be a good thing. Signed-off-by: Doug Anderson <dianders@chromium.org> Acked-by: Mark Brown <broonie@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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