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2025-05-09arm64: dts: ti: k3-am62-phycore-som: Enable Co-processorsDaniel Schultz
For every remote processor, set up dedicated memory regions and associate the required mailbox channels. Allocate two memory areas per remote core: one 1MB region for vring shared buffers, and another for external memory used by the remote processor for its resource table and trace buffer. Signed-off-by: Daniel Schultz <d.schultz@phytec.de> Reviewed-by: Wadim Egorov <w.egorov@phytec.de> Reviewed-by: Andrew Davis <afd@ti.com> Reviewed-by: Judith Mendez <jm@ti.com> Link: https://lore.kernel.org/r/20250507070008.1231611-2-d.schultz@phytec.de Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-09arm64: dts: ti: k3-am62x-phyboard-lyra-gpio-fan: Update cooling mapsDaniel Schultz
Rename 'main0_thermal_trip0' to a more descriptive name that includes 'fan', as the current name is too generic for a fan control trip point. Move the fan to a new cooling map to avoid overwriting the passive trip point used for CPU frequency throttling when this overlay is enabled. Also, add the fan to the existing cooling map. Signed-off-by: Daniel Schultz <d.schultz@phytec.de> Reviewed-by: Wadim Egorov <w.egorov@phytec.de> Link: https://lore.kernel.org/r/20250506114134.3514899-2-d.schultz@phytec.de Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-09arm64: dts: ti: k3-am62a: Enable CPU freq throttling on thermal alertDaniel Schultz
Enable throttling down the CPU frequency when an alert temperature threshold (lower than the critical threshold) is reached. Signed-off-by: Daniel Schultz <d.schultz@phytec.de> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20250506114134.3514899-1-d.schultz@phytec.de Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-09arm64: dts: ti: k3-j721e-common-proc-board: Enable OSPI1 on J721EPrasanth Babu Mantena
J721E SoM has MT25QU512AB Serial NOR flash connected to OSPI1 controller. Enable ospi1 node in device tree. Fixes: 73676c480b72 ("arm64: dts: ti: k3-j721e: Enable OSPI nodes at the board level") Signed-off-by: Prasanth Babu Mantena <p-mantena@ti.com> Link: https://lore.kernel.org/r/20250507050701.3007209-1-p-mantena@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-j721s2: Add GPU nodeMatt Coster
The J721S2 binding is based on the TI downstream binding in commit 54b0f2a00d92 ("arm64: dts: ti: k3-j721s2-main: add gpu node") from [1] but with updated compatible strings. The clock[2] and power[3] indices were verified from HTML docs, while the interrupt index comes from the TRM[4] (appendix "J721S2_Appendix_20241106_Public.xlsx", "Interrupts (inputs)", "GPU_BXS464_WRAP0_GPU_SS_0_OS_IRQ_OUT_0"). [1]: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel [2]: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/j721s2/clocks.html [3]: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/j721s2/devices.html [4]: https://www.ti.com/lit/zip/spruj28 (revision E) Reviewed-by: Randolph Sapp <rs@ti.com> Signed-off-by: Matt Coster <matt.coster@imgtec.com> Link: https://lore.kernel.org/r/20250428-bxs-4-64-dts-v4-2-eddafb4ae19f@imgtec.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am62: New GPU binding detailsMatt Coster
Use the new compatible string and power domain name as introduced in commit 2c01d9099859 ("dt-bindings: gpu: img: Future-proofing enhancements"). Reviewed-by: Randolph Sapp <rs@ti.com> Signed-off-by: Matt Coster <matt.coster@imgtec.com> Link: https://lore.kernel.org/r/20250428-bxs-4-64-dts-v4-1-eddafb4ae19f@imgtec.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am62-main: Add PRUSS-M nodeKishon Vijay Abraham I
Add the DT node for the PRUSS-M processor subsystem that is present on the K3 AM62x SoCs. The K3 AM62x family of SoC has one PRUSS-M instance and it has two Programmable Real-Time Units (PRU0 and PRU1). Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> [ Judith: Fix pruss_iclk id for pruss_coreclk_mux ] Signed-off-by: Judith Mendez <jm@ti.com> Tested-by: Daniel Schultz <d.schultz@phytec.de> Reviewed-by: Beleswar Padhi <b-padhi@ti.com> Acked-by: Hari Nagalla <hnagalla@ti.com> Link: https://lore.kernel.org/r/20250430144343.972234-1-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am64: Reserve timers used by MCU FWHari Nagalla
AM64x device has 4 R5F cores in the main domain. TI MCU firmware uses main domain timers as tick timers in these firmwares. Hence keep them as reserved in the Linux device tree. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20250502220325.3230653-12-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am62a7-sk: Reserve main_rti4 for C7x DSPHari Nagalla
The main rti4 watchdog timer is used by the C7x DSP, so reserve the timer in the linux device tree. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20250502220325.3230653-11-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am62a7-sk: Reserve main_timer2 for C7x DSPHari Nagalla
C7x DSP uses main_timer2, so mark it as reserved in linux DT. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20250502220325.3230653-10-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am62x-sk-common: Enable IPC with remote processorsHari Nagalla
For each remote proc, reserve memory for IPC and bind the mailbox assignments. Two memory regions are reserved for each remote processor. The first region of 1MB of memory is used for Vring shared buffers and the second region is used as external memory to the remote processor for the resource table and for tracebuffer allocations. Signed-off-by: Devarsh Thakkar <devarsht@ti.com> Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Judith Mendez <jm@ti.com> Acked-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20250502220325.3230653-9-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am62p5-sk: Enable IPC with remote processorsDevarsh Thakkar
For each remote proc, reserve memory for IPC and bind the mailbox assignments. Two memory regions are reserved for each remote processor. The first region of 1MB of memory is used for Vring shared buffers and the second region is used as external memory to the remote processor for the resource table and for tracebuffer allocations. Signed-off-by: Devarsh Thakkar <devarsht@ti.com> Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20250502220325.3230653-8-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am62a7-sk: Enable IPC with remote processorsDevarsh Thakkar
For each remote proc, reserve memory for IPC and bind the mailbox assignments. Two memory regions are reserved for each remote processor. The first region of 1MB of memory is used for Vring shared buffers and the second region is used as external memory to the remote processor for the resource table and for tracebuffer allocations. Signed-off-by: Devarsh Thakkar <devarsht@ti.com> Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Beleswar Padhi <b-padhi@ti.com> Reviewed-by: Jai Luthra <jai.luthra@ideasonboard.com> Acked-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20250502220325.3230653-7-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am62a-main: Add C7xv device nodeJai Luthra
AM62A SoCs have a C7xv DSP subsystem with Analytics engine capability. This subsystem is intended for deep learning purposes. Define the device node for C7xv DSP. Signed-off-by: Jai Luthra <j-luthra@ti.com> Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Judith Mendez <jm@ti.com> Tested-by: Daniel Schultz <d.schultz@phytec.de> Acked-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20250502220325.3230653-6-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am62a-wakeup: Add R5F device nodeDevarsh Thakkar
AM62A SoCs have a single R5F core in wakeup domain. This core is also used as a device manager for the SoC. Signed-off-by: Devarsh Thakkar <devarsht@ti.com> Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Judith Mendez <jm@ti.com> Tested-by: Daniel Schultz <d.schultz@phytec.de> Acked-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20250502220325.3230653-5-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am62a-mcu: Add R5F remote proc nodeHari Nagalla
AM62A SoCs have a single R5F core in the MCU voltage domain. Add the R5FSS node with the child node for core0 in MCU voltage domain .dtsi file. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Judith Mendez <jm@ti.com> Tested-by: Daniel Schultz <d.schultz@phytec.de> Acked-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20250502220325.3230653-4-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am62-wakeup: Add wakeup R5F nodeHari Nagalla
AM62 SoC devices have a single core R5F processor in wakeup domain. The R5F processor in wakeup domain is used as a device manager for the SoC. Signed-off-by: Devarsh Thakkar <devarsht@ti.com> Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Judith Mendez <jm@ti.com> Tested-by: Daniel Schultz <d.schultz@phytec.de> Acked-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20250502220325.3230653-3-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am62: Add ATCM and BTCM cbass rangesJudith Mendez
Add cbass ranges for ATCM and BTCM on am62x device, without these, remoteproc driver fails to probe and attach to the DM r5 core and IPC communication is broken. Signed-off-by: Judith Mendez <jm@ti.com> Acked-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20250502220325.3230653-2-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am625-beagleplay: Add required voltage supplies for ↵Rishikesh Donadkar
TEVI-OV5640 The device tree overlay for TEVI-OV5640 requires following voltage supplies: AVDD-supply: Analog voltage supply, 2.8 volts DOVDD-supply: Digital I/O voltage supply, 1.8 volts DVDD-supply: Digital core voltage supply, 3.3 volts Add them in the overlay. Signed-off-by: Rishikesh Donadkar <r-donadkar@ti.com> Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Link: https://lore.kernel.org/r/20250506045225.1246873-3-r-donadkar@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am625-beagleplay: Add required voltage supplies for OV5640Rishikesh Donadkar
The device tree overlay for OV5640 requires following voltage supplies: AVDD-supply: Analog voltage supply, 2.8 volts DOVDD-supply: Digital I/O voltage supply, 1.8 volts DVDD-supply: Digital core voltage supply, 1.5 volts Add them in the overlay. Signed-off-by: Rishikesh Donadkar <r-donadkar@ti.com> Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Link: https://lore.kernel.org/r/20250506045225.1246873-2-r-donadkar@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am62x: Add required voltage supplies for TEVI-OV5640Rishikesh Donadkar
The device tree overlay for TEVI-OV5640 requires following voltage supplies as mentioned in the power section [1] AVDD-supply: Analog voltage supply, 2.8 volts DOVDD-supply: Digital I/O voltage supply, 1.8 volts DVDD-supply: Digital core voltage supply, 3.3 volts Add them in the DT overlay. Link: https://www.technexion.com/wp-content/uploads/2023/09/product-brief_tevi-ov5640.pdf Signed-off-by: Rishikesh Donadkar <r-donadkar@ti.com> Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Link: https://lore.kernel.org/r/20250502162539.322091-5-r-donadkar@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am62x: Add required voltage supplies for OV5640Rishikesh Donadkar
The device tree overlay for OV5640 requires following voltage supplies as mentioned in the table 8-3 of the data-sheet [1]. AVDD-supply: Analog voltage supply, 2.8 volts DOVDD-supply: Digital I/O voltage supply, 1.8 volts DVDD-supply: Digital core voltage supply, 1.5 volts Add them in the overlay. Link: https://cdn.sparkfun.com/datasheets/Sensors/LightImaging/OV5640_datasheet.pdf Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Signed-off-by: Rishikesh Donadkar <r-donadkar@ti.com> Link: https://lore.kernel.org/r/20250502162539.322091-4-r-donadkar@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am62x: Add required voltage supplies for IMX219Rishikesh Donadkar
The device tree overlay for the IMX219 sensor requires three voltage supplies to be defined: VANA (analog), VDIG (digital core), and VDDL (digital I/O) [1]. Add the corresponding voltage supply definitions in the overlay so that the same topography as dt-bindings is present in the DT overlay. Link: https://datasheets.raspberrypi.com/camera/camera-module-2-schematics.pdf [1] Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Signed-off-by: Rishikesh Donadkar <r-donadkar@ti.com> Link: https://lore.kernel.org/r/20250502162539.322091-3-r-donadkar@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-06arm64: dts: ti: k3-am62p5-sk: Add regulator nodes for AM62PRishikesh Donadkar
Add regulator node for AM62P-SK VCC_3V3_MAIN is the output of LM5141-Q1, and it serves as an input to TPS22965DSGT which produces VCC_3V3_SYS [1] VCC_3V3_SYS servers as vin-supply for peripherals like CSI [1]. Link: https://www.ti.com/lit/zip/sprr487 [1] Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Signed-off-by: Rishikesh Donadkar <r-donadkar@ti.com> Link: https://lore.kernel.org/r/20250502162539.322091-2-r-donadkar@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: k3-am65-main: Add missing taps to sdhci0Judith Mendez
For am65x, add missing ITAPDLYSEL values for Default Speed and High Speed SDR modes to sdhci0 node according to the device datasheet [0]. [0] https://www.ti.com/lit/gpn/am6548 Fixes: eac99d38f861 ("arm64: dts: ti: k3-am654-main: Update otap-del-sel values") Cc: stable@vger.kernel.org Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Moteen Shah <m-shah@ti.com> Link: https://lore.kernel.org/r/20250429173009.33994-1-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: k3-am62p-j722s-common-main: Set eMMC clock parent to defaultJudith Mendez
Set eMMC clock parents to the defaults which is MAIN_PLL0_HSDIV5_CLKOUT for eMMC. This change is necessary since DM is not implementing the correct procedure to switch PLL clock source for eMMC and MMC CLK mux is not glich-free. As a preventative action, lets switch back to the defaults. Fixes: b5080c7c1f7e ("arm64: dts: ti: k3-am62p: Add nodes for more IPs") Cc: stable@vger.kernel.org Signed-off-by: Judith Mendez <jm@ti.com> Acked-by: Udit Kumar <u-kumar1@ti.com> Acked-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20250429163337.15634-4-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: k3-am62a-main: Set eMMC clock parent to defaultJudith Mendez
Set eMMC clock parents to the defaults which is MAIN_PLL0_HSDIV5_CLKOUT for eMMC. This change is necessary since DM is not implementing the correct procedure to switch PLL clock source for eMMC and MMC CLK mux is not glich-free. As a preventative action, lets switch back to the defaults. Fixes: d3ae4e8d8b6a ("arm64: dts: ti: k3-am62a-main: Add sdhci0 instance") Cc: stable@vger.kernel.org Signed-off-by: Judith Mendez <jm@ti.com> Acked-by: Udit Kumar <u-kumar1@ti.com> Acked-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20250429163337.15634-3-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: k3-am62-main: Set eMMC clock parent to defaultJudith Mendez
Set eMMC clock parents to the defaults which is MAIN_PLL0_HSDIV5_CLKOUT for eMMC. This change is necessary since DM is not implementing the correct procedure to switch PLL clock source for eMMC and MMC CLK mux is not glich-free. As a preventative action, lets switch back to the defaults. Fixes: c37c58fdeb8a ("arm64: dts: ti: k3-am62: Add more peripheral nodes") Cc: stable@vger.kernel.org Signed-off-by: Judith Mendez <jm@ti.com> Acked-by: Udit Kumar <u-kumar1@ti.com> Acked-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20250429163337.15634-2-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: am62p-verdin: Add ivyFrancesco Dolcini
Add support for Verdin AM62P mated with Verdin Ivy carrier board. Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p Link: https://www.toradex.com/products/carrier-board/ivy-carrier-board Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://lore.kernel.org/r/20250430102815.149162-7-francesco@dolcini.it Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: am62p-verdin: Add yaviaFrancesco Dolcini
Add support for Verdin AM62P mated with Verdin Yavia carrier board. Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p Link: https://www.toradex.com/products/carrier-board/yavia Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://lore.kernel.org/r/20250430102815.149162-6-francesco@dolcini.it Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: am62p-verdin: Add mallowFrancesco Dolcini
Add support for Verdin AM62P mated with Verdin Mallow carrier board. Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p Link: https://www.toradex.com/products/carrier-board/mallow-carrier-board Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://lore.kernel.org/r/20250430102815.149162-5-francesco@dolcini.it Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: am62p-verdin: Add dahliaFrancesco Dolcini
Add support for Verdin AM62P mated with Verdin Dahlia carrier board. Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p Link: https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://lore.kernel.org/r/20250430102815.149162-4-francesco@dolcini.it Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: Add Toradex Verdin AM62PFrancesco Dolcini
Add support for Toradex Verdin AM62P computer on module which can be used on different carrier boards and for the Toradex Verdin Development Board carrier board. The module consists of an TI AM62P family SoC, a TPS65219 PMIC, a Gigabit Ethernet PHY, up to 8GB of LPDDR4 RAM, an eMMC, a TLA2024 ADC, an I2C EEPROM, an RX8130 RTC, plus an optional Bluetooth/Wi-Fi module. Anything that is not self-contained on the module is disabled by default. Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p Link: https://www.toradex.com/products/carrier-board/verdin-development-board-kit Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://lore.kernel.org/r/20250430102815.149162-3-francesco@dolcini.it Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02dt-bindings: arm: ti: Add Toradex Verdin AM62PFrancesco Dolcini
Add toradex,verdin-am62p for Toradex Verdin AM62 SoM, its nonwifi and wifi variants, and the Toradex carrier board they may be mated in. Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250430102815.149162-2-francesco@dolcini.it Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: k3-j784s4-j742s2-evm-common: Enable ACSPCIE0 output for PCIe1Siddharth Vadapalli
The PCIe reference clock required by the PCIe Endpoints connected to the PCIe connector corresponding to the PCIe1 instance of PCIe on J784S4-EVM and J742S2-EVM is driven by the ACSPCIE0 module. Add the device-tree support for enabling the same. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250422123218.3788223-3-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: k3-j784s4-j742s2-main-common: Add ACSPCIE0 nodeSiddharth Vadapalli
The ACSPCIE0 module on TI's J784S4 SoC is capable of driving the reference clock required by the PCIe Endpoint device. It is an alternative to on-board and external reference clock generators. Add the device-tree node for the same. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250422123218.3788223-2-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: k3-j784s4-j742s2-main-common: Switch to 64-bit address space ↵Siddharth Vadapalli
for PCIe0 and PCIe1 The PCIe0 and PCIe1 instances of PCIe in J742S2 and J784S4 SoCs support: 1. 128 MB address region in the 32-bit address space 2. 4 GB address region in the 64-bit address space The default configuration is that of a 128 MB address region in the 32-bit address space. While this might be sufficient for most use-cases, it is insufficient for supporting use-cases which require larger address spaces. Therefore, switch to using the 64-bit address space with a 4 GB address region. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250422120042.3746004-8-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: k3-j722s-main: Switch to 64-bit address space for PCIe0Siddharth Vadapalli
The PCIe0 instance of PCIe in J722S SoC supports: 1. 128 MB address region in the 32-bit address space 2. 4 GB address region in the 64-bit address space The default configuration is that of a 128 MB address region in the 32-bit address space. While this might be sufficient for most use-cases, it is insufficient for supporting use-cases which require larger address spaces. Therefore, switch to using the 64-bit address space with a 4 GB address region. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250422120042.3746004-7-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: k3-j721s2-main: Switch to 64-bit address space for PCIe1Siddharth Vadapalli
The PCIe1 instance of PCIe in J721S2 SoC supports: 1. 128 MB address region in the 32-bit address space 2. 4 GB address region in the 64-bit address space The default configuration is that of a 128 MB address region in the 32-bit address space. While this might be sufficient for most use-cases, it is insufficient for supporting use-cases which require larger address spaces. Therefore, switch to using the 64-bit address space with a 4 GB address region. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250422120042.3746004-6-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: k3-j721e-main: Switch to 64-bit address space for PCIe0 and ↵Siddharth Vadapalli
PCIe1 The PCIe0 and PCIe1 instances of PCIe in J721E SoC support: 1. 128 MB address region in the 32-bit address space 2. 4 GB address region in the 64-bit address space The default configuration is that of a 128 MB address region in the 32-bit address space. While this might be sufficient for most use-cases, it is insufficient for supporting use-cases which require larger address spaces. Therefore, switch to using the 64-bit address space with a 4 GB address region. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250422120042.3746004-5-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: k3-j721e: Add ranges for PCIe0 DAT1 and PCIe1 DAT1Siddharth Vadapalli
The PCIe0 DAT1 and PCIe1 DAT1 are 4 GB address regions in the 64-bit address space of the respective PCIe Controllers. Hence, update the ranges to include them. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250422120042.3746004-4-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: k3-j7200-main: Switch to 64-bit address space for PCIe1Siddharth Vadapalli
The PCIe0 instance of PCIe in J7200 SoC supports: 1. 128 MB address region in the 32-bit address space 2. 4 GB address region in the 64-bit address space The default configuration is that of a 128 MB address region in the 32-bit address space. While this might be sufficient for most use-cases, it is insufficient for supporting use-cases which require larger address spaces. Therefore, switch to using the 64-bit address space with a 4 GB address region. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250422120042.3746004-3-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: k3-am64-main: Switch to 64-bit address space for PCIe0Siddharth Vadapalli
The PCIe0 instance of PCIe in AM64 SoC supports: 1. 128 MB address region in the 32-bit address space 2. 4 GB address region in the 64-bit address space The default configuration is that of a 128 MB address region in the 32-bit address space. While this might be sufficient for most use-cases, it is insufficient for supporting use-cases which require larger address spaces. Therefore, switch to using the 64-bit address space with a 4 GB address region. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250422120042.3746004-2-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: k3-am6*: Remove disable-wp for eMMCJudith Mendez
Remove disable-wp flag for eMMC nodes since this flag is only applicable to SD according to the binding doc (mmc/mmc-controller-common.yaml). For eMMC, this flag should be ignored but lets remove anyways to cleanup sdhci nodes. Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Moteen Shah <m-shah@ti.com> Link: https://lore.kernel.org/r/20250429151454.4160506-4-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: k3-am62*: Add non-removable flag for eMMCJudith Mendez
EMMC device is non-removable so add 'non-removable' DT property to avoid having to redetect the eMMC after suspend/resume. Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20250429151454.4160506-3-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-05-02arm64: dts: ti: k3-am6*: Add boot phase flag to support MMC bootJudith Mendez
The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. For eMMC and SD boot modes, voltage regulator nodes, io-expander nodes, gpio nodes, and MMC nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot and eMMC boot. Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Moteen Shah <m-shah@ti.com> Link: https://lore.kernel.org/r/20250429151454.4160506-2-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-04-25arm64: dts: ti: k3-am625-sk: Enable PWMJudith Mendez
PWM signals can be routed to the user expansion header on am625 SK and am62 lp sk. Enable eCAP0, eCAP1, eHRPWM1, and route the output PWM signals to pins on J3 header. Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20250422000851.4118545-4-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-04-25arm64: dts: ti: k3-am62a7-sk: Enable PWMJudith Mendez
PWM signals can be routed to the user expansion header on am62a7 SK. Enable eCAP0, eCAP1, eHRPWM1, and route the output PWM signals to pins on J3 header. Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20250422000851.4118545-3-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-04-25arm64: dts: ti: k3-am62p5-sk: Enable PWMJudith Mendez
PWM signals can be routed to the user expansion header on am62p5 SK. Enable eCAP0, eCAP1, eHRPWM0, eHRPWM1 and route the output PWM signals to pins on J4 header. Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20250422000851.4118545-2-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2025-04-25arm64: dts: ti: Add basic support for phyBOARD-Izar-AM68xDominik Haller
The phyCORE-AM68x/TDA4x [1] is a SoM (System on Module) featuring TI's AM68x/TDA4x SoC. It can be used in combination with different carrier boards. This module can come with different sizes and models for DDR, eMMC, SPI NOR Flash and various SoCs from the AM68x/TDA4x (J721S2) family. A reference carrier board design, called phyBOARD-Izar is used for the phyCORE-AM68x/TDA4x development kit [2]. Supported features: * Debug UART * 2x SPI NOR Flash * eMMC * 2x Ethernet * Micro SD card * I2C EEPROM * I2C RTC * 2x I2C GPIO Expander * LEDs * USB 5 Gbit/s * PCIe For more details see the product pages for the SoM and the development kit: [1] https://www.phytec.eu/en/produkte/system-on-modules/phycore-am68x-tda4x/ [2] https://www.phytec.eu/en/produkte/development-kits/phyboard-izar/ Signed-off-by: Dominik Haller <d.haller@phytec.de> Reviewed-by: Wadim Egorov <w.egorov@phytec.de> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Acked-by: Moteen Shah <m-shah@ti.com> Link: https://lore.kernel.org/r/20250423133635.29897-2-d.haller@phytec.de Signed-off-by: Nishanth Menon <nm@ti.com>
generated by cgit (git 2.34.1) at 2025-09-09 20:56:14 +0000