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2019-02-06ARM: dts: qcom: ipq4019: Fix MSI IRQ typeNiklas Cassel
The databook clearly states that the MSI IRQ (msi_ctrl_int) is a level triggered interrupt. The msi_ctrl_int will be high for as long as any MSI status bit is set, thus the IRQ type should be set to IRQ_TYPE_LEVEL_HIGH, causing the IRQ handler to keep getting called, as long as any MSI status bit is set. A git grep shows that ipq4019 is the only SoC using snps,dw-pcie that has configured this IRQ incorrectly. Not having the correct IRQ type defined will cause us to lose interrupts, which in turn causes timeouts in the PCIe endpoint drivers. Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-02-06arm64: dts: msm8916: remove bogus argument to the cpu clockNiklas Cassel
The apcs node has #clock-cells = <0>, which means that those who references it should specify 0 arguments. The apcs reference in the cpu node incorrectly specifies an argument, remove this bogus argument. Fixes: 65afdf458360 ("arm64: dts: qcom: msm8916: Add CPU frequency scaling support") Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-02-06dt-bindings: cpufreq: tegra124: remove cpu_lp clock from required propertiesJoseph Lo
The cpu_lp clock property is only needed when the CPUfreq driver supports CPU cluster switching. But it was not a design for this driver and it didn't handle that as well. So removing this property. Cc: devicetree@vger.kernel.org Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-06dt-bindings: cpufreq: tegra124: remove vdd-cpu-supply from required propertiesJoseph Lo
The Tegra124 cpufreq driver works only with DFLL clock, which is a hardware-based frequency/voltage controller. The driver doesn't need to control the regulator itself. Hence remove that. Cc: devicetree@vger.kernel.org Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-06dt-bindings: clock: tegra124-dfll: add Tegra210 supportJoseph Lo
Add Tegra210 support for DFLL clock. Cc: devicetree@vger.kernel.org Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-06dt-bindings: clock: tegra124-dfll: Update DFLL binding for PWM regulatorPeter De Schrijver
Add new properties to configure the DFLL PWM regulator support. Cc: devicetree@vger.kernel.org Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-06ARM: tegra: add "jedec,spi-nor" flash compatible bindingRafał Miłecki
Starting with commit 8947e396a829 ("Documentation: dt: mtd: replace "nor-jedec" binding with "jedec, spi-nor"") we have "jedec,spi-nor" binding indicating support for JEDEC identification. Use it for all flashes that are supposed to support READ ID op according to the datasheets. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Acked-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-06arm64: dts: allwinner: h5: libretech-all-h3-cc: Mark eMMC HS-DDR 3.3V capableChen-Yu Tsai
The Libre Computer ALL-H3-CC H5 is one of the few boards that can have its eMMC run at HS-DDR speed mode. Mark it as such. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-02-06arm64: dts: allwinner: a64: Enable PMIC power supplies on various boardsChen-Yu Tsai
On these A64 devices, the DC input jacks are wired to the ACIN pins of the PMIC, which is represented by the AC power supply. With the exception of the Nanopi A64, all devices include LiPo batteries or have connectors for them, which are represented by the battery power supply. Enable these power supplies in the device tree. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-02-06arm64: dts: marvell: armada-3720-espressobin: declare PCIe warm reset pinMiquel Raynal
Ensure the PCIe endpoint card reset that is toggled by the PCIe controller itself is muxed correctly on the EspressoBin. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-02-06arm64: dts: marvell: armada-37xx: declare PCIe reset pinMiquel Raynal
One pin can be muxed as PCIe endpoint card reset. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-02-06arm64: dts: marvell: armada-37xx: declare USB2 UTMI PHYsMiquel Raynal
On Marvell Armada 3700 SoCs there are two USB2 UTMI PHYs. They are both very similar but only one has OTG/charging capabilities. Because there are USB host registers and PHY registers mixed in a single area, a system controller is also created and referenced from both the USB host node and the PHY node. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-02-06arm64: dts: marvell: armada-37xx: fix USB2 memory regionMiquel Raynal
The specification splits the USB2 memory region into three sections: 1/ 0xD005E000-0xD005EFFF: USB2 Host Controller Registers 2/ 0xD005F000-0xD005F7FF: USB2 UTMI PHY Registers 3/ 0xD005F800-0xD005FFFF: USB2 Host Miscellaneous Registers Section 1/ belongs to the USB2 node but section 2/ belongs to the UTMI PHY node. Section 3/ can be accessed by both the USB controller and the PHY because of the miscaellaneous nature of the registers inside so a specific node will be created to cover the area and a handle to it will be added in both the USB controller and the PHY node. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-02-06arm64: dts: marvell: armada-37xx: declare SATA clockMiquel Raynal
The SATA IP get its clock from the north-bridge. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-02-06arm64: dts: marvell: armada-37xx: fix SATA node scopeMiquel Raynal
Fix the SATA IP memory area which is only 0x178 bytes long (from Marvell A3700 specification). Actually, starting from the offset 0xe0178, there is an area dedicated to the COMPHY driver. Suggested-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-02-06arm64: dts: marvell: add interrupt support to cp110 thermal nodeMiquel Raynal
Add interrupt properties in the thermal node as well as a critical trip point in the thermal-zone. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Eduardo Valentin <edubezval@gmail.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-02-06arm64: dts: marvell: add interrupt support to ap806 thermal nodeMiquel Raynal
Add interrupt properties in the thermal node as well as a critical trip point in the thermal-zone. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Eduardo Valentin <edubezval@gmail.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-02-04arm64: dts: hikey: Revert "Enable HS200 mode on eMMC"Alistair Strachan
This reverts commit abd7d0972a192ee653efc7b151a6af69db58f2bb. This change was already partially reverted by John Stultz in commit 9c6d26df1fae ("arm64: dts: hikey: Fix eMMC corruption regression"). This change appears to cause controller resets and block read failures which prevents successful booting on some hikey boards. Cc: Ryan Grachek <ryan@edited.us> Cc: Wei Xu <xuwei5@hisilicon.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: stable <stable@vger.kernel.org> #4.17+ Signed-off-by: Alistair Strachan <astrachan@google.com> Signed-off-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2019-02-04arm64: dts: hikey: Give wifi some time after power-onJan Kiszka
Somewhere along recent changes to power control of the wl1835, power-on became very unreliable on the hikey, failing like this: wl1271_sdio: probe of mmc2:0001:1 failed with error -16 wl1271_sdio: probe of mmc2:0001:2 failed with error -16 After playing with some dt parameters and comparing to other users of this chip, it turned out we need some power-on delay to make things stable again. In contrast to those other users which define 200 ms, the hikey would already be happy with 1 ms. Still, we use the safer 10 ms, like on the Ultra96. Fixes: ea452678734e ("arm64: dts: hikey: Fix WiFi support") Cc: <stable@vger.kernel.org> #4.12+ Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2019-02-03ARM: dts: lpc32xx: ea3250: beautify gpio keys children nodesVladimir Zapolskiy
Regarding the 'gpio_keys' device node a dtc reports a couple of warnings: Warning (avoid_unnecessary_addr_size): /gpio_keys: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Warning (unit_address_vs_reg): /gpio_keys/button@21: node has a unit name, but no reg property The change fixes these issues and adds empty lines between adjacent children device nodes. The device node itself is renamed by substituting an underscore by hyphen to follow the standard naming convention of device tree nodes. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-02-03ARM: dts: lpc32xx: ea3250: add unit address to memory device nodeVladimir Zapolskiy
The change adds a unit address to memory device node, the issue was reported as a unit_address_vs_reg warning by dtc. Root device node properties #address-cells and #size-cells were removed as inherited from lpc32xx.dtsi. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-02-03ARM: dts: lpc32xx: phy3250: add unit address to memory device nodeVladimir Zapolskiy
The change adds a unit address to memory device node, the issue was reported as a unit_address_vs_reg warning by dtc. Root device node properties #address-cells and #size-cells were removed as inherited from lpc32xx.dtsi. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-02-03ARM: dts: lpc32xx: phy3250: setup LCD controller to panel interfaceVladimir Zapolskiy
The change adds description of Sharp LQ035Q7DB03 3.5" 320x240 TFT panel, which is connected to Phytec phyCORE-LPC3250 board, ARM PrimeCell PL111 LCD controller on NXP LPC3250 SoC gets its configuration appropriately to support graphics output to the panel. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-02-03ARM: dts: lpc32xx: phy3250: remove regulators umbrella device nodeVladimir Zapolskiy
The originally added 'regulators' device node has a number of flaws, to name a few its children has unit addresses but no reg properties, the regulators are not captured by a device driver due to a missing 'simple-bus' compatible, the regulator names are selected by killing either alphabetical order or device node grouping property. The change removes 'regulators' device node and renames the regulators and labels. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-02-03ARM: dts: lpc32xx: phy3250: fix SD card regulator voltageVladimir Zapolskiy
The fixed voltage regulator on Phytec phyCORE-LPC3250 board, which supplies SD/MMC card's power, has a constant output voltage level of either 3.15V or 3.3V, the actual value depends on JP4 position, the power rail is referenced as VCC_SDIO in the board hardware manual. Fixes: d06670e96267 ("arm: dts: phy3250: add SD fixed regulator") Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-02-03ARM: dts: lpc32xx: fix ARM PrimeCell LCD controller clocks propertyVladimir Zapolskiy
The originally added ARM PrimeCell PL111 clocks property misses the required "clcdclk" clock, which is the same as a clock to enable the LCD controller on NXP LPC3230 and NXP LPC3250 SoCs. Fixes: 93898eb775e5 ("arm: dts: lpc32xx: add clock properties to device nodes") Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-02-03ARM: dts: lpc32xx: fix ARM PrimeCell LCD controller variantVladimir Zapolskiy
ARM PrimeCell PL111 LCD controller is found on On NXP LPC3230 and LPC3250 SoCs variants, the original reference in compatible property to an older one ARM PrimeCell PL110 is invalid. Fixes: e04920d9efcb3 ("ARM: LPC32xx: DTS files for device tree conversion") Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-02-03ARM: dts: lpc32xx: reparent keypad controller to SIC1Vladimir Zapolskiy
After switching to a new interrupt controller scheme by separating SIC1 and SIC2 from MIC interrupt controller just one SoC keypad controller was not taken into account, fix it now: WARNING: CPU: 0 PID: 1 at kernel/irq/irqdomain.c:524 irq_domain_associate+0x50/0x1b0 error: hwirq 0x36 is too large for interrupt-controller@40008000 ... lpc32xx_keys 40050000.key: failed to get platform irq lpc32xx_keys: probe of 40050000.key failed with error -22 Fixes: 9b8ad3fb81ae ("ARM: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC") Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-02-03ARM: dts: lpc32xx: add required clocks property to keypad device nodeVladimir Zapolskiy
NXP LPC32xx keypad controller requires a clock property to be defined. The change fixes the driver initialization problem: lpc32xx_keys 40050000.key: failed to get clock lpc32xx_keys: probe of 40050000.key failed with error -2 Fixes: 93898eb775e5 ("arm: dts: lpc32xx: add clock properties to device nodes") Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-02-03ARM: dts: Add DT for MYIR Tech MYD-LPC4357 Development BoardVladimir Zapolskiy
Add support for MYIR Tech MYD-LPC4357 Development Board and MY-LCD70TP-C 7" TFT LCD module with Innolux AT070TN82 panel. The board contains quite rich periferals, the list features NXP LPC4357 SoC, 32 MB SDRAM, 4 MB SPI Flash, audio input/output interface, LCD panel, micro SD card slot, USB, USB OTG, Ethernet, 2 CAN ports, 4 UARTs, I2C and SPI interfaces routed to external interface. More information can be found on http://www.myirtech.com/list.asp?id=422 Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-02-03ARM: dts: lpc32xx: Remove leading 0x and 0s from bindings notationMathieu Malaterre
Improve the DTS files by removing all the leading "0x" and zeros to fix the following dtc warnings: Warning (unit_address_format): Node /XXX unit name should not have leading "0x" and Warning (unit_address_format): Node /XXX unit name should not have leading 0s Converted using the following command: find . -type f \( -iname *.dts -o -iname *.dtsi \) -exec sed -i -e "s/@\([0-9a-fA-FxX\.;:#]+\)\s*{/@\L\1 {/g" -e "s/@0x\(.*\) {/@\1 {/g" -e "s/@0+\(.*\) {/@\1 {/g" {} + For simplicity, two sed expressions were used to solve each warnings separately. To make the regex expression more robust a few other issues were resolved, namely setting unit-address to lower case, and adding a whitespace before the opening curly brace: https://elinux.org/Device_Tree_Linux#Linux_conventions This will solve as a side effect warning: Warning (simple_bus_reg): Node /XXX@<UPPER> simple-bus unit address format error, expected "<lower>" This is a follow up to commit 4c9847b7375a ("dt-bindings: Remove leading 0x from bindings notation") Reported-by: David Daney <ddaney@caviumnetworks.com> Suggested-by: Rob Herring <robh@kernel.org> Signed-off-by: Mathieu Malaterre <malat@debian.org> [vzapolskiy: fixed commit message to pass checkpatch.pl test] Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-02-03ARM: dts: rockchip: Use the correct regulator properties on rv1108-evbOtavio Salvador
The following properties: - regulator-state-enabled - regulator-state-disabled - regulator-state-uv are not valid ones as per Documentation/devicetree/bindings/regulator/regulator.txt Fix it by using the correct properties as per the dt bindings. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-02-03ARM: dts: rockchip: Use the correct regulator properties on rv1108-elginOtavio Salvador
The following properties: - regulator-state-enabled - regulator-state-disabled - regulator-state-uv are not valid ones as per Documentation/devicetree/bindings/regulator/regulator.txt Fix it by using the correct properties as per the dt bindings. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-02-03ARM: dts: rockchip: Fix vcc5/6-supply representation on rv1108-elginOtavio Salvador
On rv1108-elgin-r1 board the RK805 VCC5 and VCC6 supplies come from the BUCK2 regulator at 2.2V, so fix the representation in the device tree. While at it, rename it from vdd_cam to vdd_buck2, which is a better name for the regulator label. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-02-02Merge tag 'tags/bcm2835-dt-64-next-2019-02-01' into devicetree-arm64/nextFlorian Fainelli
This pull request brings in the arm64 reference for Raspberry Pi 3 A+. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2019-02-01arm64: dts: sdm845: Add interconnect provider DT nodesDavid Dai
Add RSC (Resource State Coordinator) provider dictating network-on-chip interconnect bus performance found on SDM845-based platforms. Signed-off-by: David Dai <daidavid1@codeaurora.org> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-02-01arm64: dts: qcom: msm8996: Disabled VFE SMMUBjorn Andersson
Initializing the SMMU trips a security violation, so disable the VFE SMMU for now. Fixes: f3442ab97257 ("arm64: dts: qcom: msm8996: Add VFE SMMU node") Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-02-01arm64: dts: qcom: qcs404: Add rpmcc nodeBjorn Andersson
Add the rpm clock controller node, to provide the low-noise baseband clock for the USB PHYs, among other things. Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-02-01arm64: dts: qcom: msm8998: Add rpmcc nodeMarc Gonzalez
Add MSM8998 Resource Power Manager Clock Controller DT node. Tested-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Reviewed-by: Jeffrey Hugo <jhugo@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-02-01arm64: dts: qcom: msm8998: Add USB-related nodesJeffrey Hugo
Add nodes for USB and related PHYs. Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-02-01arm64: dts: broadcom: Add reference to RPi 3 A+Stefan Wahren
This adds a reference to the dts of the Raspberry Pi 3 A+, so we don't need to maintain the content in arm64. Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2019-02-01ARM: dts: add Raspberry Pi 3 A+Stefan Wahren
The Raspberry Pi 3 A+ is similar to the Pi 3 B+ but has only 512 MB RAM, 1 USB 2.0 port and no Ethernet. Compared to the Raspberry Pi 3 B it isn't possible to control BT_ON and WL_ON separately. Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Acked-by: Eric Anholt <eric@anholt.net>
2019-02-01Merge tag 'tags/bcm2835-dt-next-2019-02-01' into devicetree/nextFlorian Fainelli
This pull request adds support for the new Raspberry Pi 3 A+ and the missing GPIO labels for RPi 2/3. Additionally it contains some minor DT fixes. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2019-02-01arm64: dts: allwinner: a64: teres-i: enable power suppliesHarald Geyer
TERES-I has ACIN connector and battery. Signed-off-by: Harald Geyer <harald@ccbib.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-02-01arm64: dts: imx8mq-evk: Add fsl,magic-packet propertyCarlo Caione
Add the fsl,magic-packet property in the fec node. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-02-01arm64: dts: imx8mq-evk: add missing MDIO / PHY nodesCarlo Caione
Populate the fec1 node with the missing MDIO and PHY entries. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-02-01arm64: dts: imx8mq-evk: enable USB nodes for USB3 hostLucas Stach
It enables USB3 host device support for imx8mq-evk board. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-02-01arm64: dts: imx8mq: add USB nodesLucas Stach
It adds USB device and phy nodes for imx8mq SoC. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-02-01ARM: dts: bcm2835-rpi-zero-w: Drop unnecessary pinctrlStefan Wahren
There is no need to specify a pinctrl for the reset GPIO. So we better remove this avoid a potential conflict between pinctrl and pwrseq after the pinmux driver has been changed to strict: pinctrl-bcm2835 20200000.gpio: pin gpio41 already requested by wifi-pwrseq; cannot claim for pinctrl-bcm2835:499 pinctrl-bcm2835 20200000.gpio: pin-41 (pinctrl-bcm2835:499) status -22 pwrseq_simple: probe of wifi-pwrseq failed with error -22 Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2019-02-01ARM: dts: bcm283x: Add missing GPIO line namesStefan Wahren
The GPIO sysfs is deprecated and disabled in the defconfig files. So in order to motivate the usage of the new GPIO character device API add the missing GPIO line names for Raspberry Pi 2 and 3. In the lack of full schematics i would leave all undocumented pins as unnamed. Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Tested-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net>
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