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2013-06-18ARM: dts: OMAP4/5: Use existing constants for IRQsFlorian Vaussard
Use the constants defined in include/dt-bindings/interrupt-controller/ to enhance readability. Signed-off-by: Florian Vaussard <florian.vaussard@epfl.ch> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
2013-06-18ARM: dts: OMAP2+: Use existing constants for GPIOsFlorian Vaussard
Use standard GPIO constants to enhance the readability of DT GPIOs. Signed-off-by: Florian Vaussard <florian.vaussard@epfl.ch> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
2013-06-18ARM: dts: OMAP2+: Use #include for all device treesFlorian Vaussard
Replace /include/ by #include for OMAP2+ DT, in order to use the C pre-processor, making use of #define features possible. Signed-off-by: Florian Vaussard <florian.vaussard@epfl.ch> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
2013-06-18ARM: dts: AM33XX: Add NAND flash device tree data to am335x-evmPhilip Avinash
GPMC controller on AM335x-EVM has a NAND flash connected to it. This patch updates following in am335x-evm.dts: - adds nandflash specific pin-mux configs - adds nand node as child of GPMC contoller, with information about NAND flash interface, NAND partition table, ECC scheme, elm handle id. - updates GPMC node for newer GPMC DT properties added in linux-3.10. Signed-off-by: Philip Avinash <avinashphilip@ti.com> Signed-off-by: Gupta, Pekon <pekon@ti.com> Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
2013-06-18ARM: dts: AM33XX: Add ELM nodePhilip, Avinash
ELM hardware engine is used for locating bit-flips in NAND data This patch is required for working of hardware based NAND ECC schemes with DT support. Signed-off-by: Philip Avinash <avinashphilip@ti.com> Acked-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
2013-06-18ARM: dts: omap3-igep0030: Add NAND flash supportJavier Martinez Canillas
The IGEP COM Module has an 512MB NAND flash memory. Add a device node for this NAND and its partition layout. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
2013-06-18ARM: dts: omap3-igep0020: Add NAND flash supportJavier Martinez Canillas
The IGEPv2 board has an 512MB NAND flash memory. Add a device node for this NAND and its partition layout. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
2013-06-18ARM: dts: omap3-igep0020: Add SMSC911x LAN chip supportJavier Martinez Canillas
The IGEPv2 board has an SMSC LAN9221i ethernet chip connected to the OMAP3 processor though the General-Purpose Memory Controller. This patch adds a device node for the ethernet chip as a GPMC child and all its dependencies (regulators, GPIO and pin muxs). Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
2013-06-18ARM: dts: AM33XX: Set pinmux for clkout2 pad used for clock outputVaibhav Hiremath
xdma_event_intr1.clkout2 pad can be used to source clock from either 32K OSC or any of the PLL (except MPU) outputs. On the existing AM335x based boards (EVM, EVM-SK and Bone), this pad is used to feed the clock to audio codes. So, this patch configures the pinmux to get clkout2 on the pad. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
2013-06-18ARM: dts: AM33XX: Add default pinctrl binding for UART0 deviceVaibhav Hiremath
Add pin control binding for UART0 device nodes in all board specific DT files. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Acked-by: Matt Porter <mporter@ti.com> Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
2013-06-18ARM: dts: AM33XX: Fix uart numbering to match hardware/TRMVaibhav Hiremath
With DT support, where naming convention is based on base-addr and not id, so we should follow TRM/Spec numbering label. This patch changes UART numbering as per TRM, as uart0-5. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Acked-by: Matt Porter <mporter@ti.com> Cc: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
2013-06-18ARM: dts: AM33XX: Add pinctrl binding to gpio-leds nodeVaibhav Hiremath
Now gpio-leds driver is using devm_pinctrl_get_select_default() api to set default pinmux configuration required for the functionality of the driver, so this patch moves respective pinctrl binding inside leds node. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
2013-06-18ARM: dts: AM33XX: Add default pinctrl binding for I2C deviceVaibhav Hiremath
Add pin control binding for I2C device nodes in all board specific DT files (as per current usage), EVM: Both i2c0 and i2c1 EVM-SK and Bone: Only i2c0 Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Acked-by: Matt Porter <mporter@ti.com> Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
2013-06-18ARM: dts: OMAP4+: Remove multimedia carveoutsSuman Anna
The carveouts that have been reserved for multimedia usecases are not being used currently by any driver and so have been cleaned up. Memory will be allocated runtime through CMA for enabling the multimedia usecases. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
2013-06-18UIO: fix uio_pdrv_genirq with device tree but no interruptPavel Machek
If device is initialized from device tree, but has no interrupt assigned, uio will still try to request and interrupt old way, fails, and fails registration. This is wrong; don't try initializing irq using platform data if device tree is available. Simplified code based on suggestion by Grant Likely. Fixed memory leak in "irq can not be registered" error path. Signed-off-by: Pavel Machek <pavel@denx.de> Reported-by: Detlev Zundel <dzu@denx.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-06-18UIO: allow binding uio_pdrv_genirq.c to devices using command line optionPavel Machek
This adds ability to bind uio driver to given open firmware device using command line option. Thus, userspace driver can be developed and used without modifying the kernel. Signed-off-by: Pavel Machek <pavel@denx.de> Tested-by: Detlev Zundel <dzu@denx.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-06-18FMC: add a char-device mezzanine driverAlessandro Rubini
This driver exports the memory area associated with the mezzanine card as a misc device, so users can access registers. Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Acked-by: Juan David Gonzalez Cobas <dcobas@cern.ch> Acked-by: Emilio G. Cota <cota@braap.org> Acked-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-06-18FMC: add a driver to write mezzanine EEPROMAlessandro Rubini
This driver allows to reprogram the EEPROM in a mezzanine, to store its own identifiers during manufacturing or to save other useful data. Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Acked-by: Juan David Gonzalez Cobas <dcobas@cern.ch> Acked-by: Emilio G. Cota <cota@braap.org> Acked-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-06-18FMC: add a software mezzanine driverAlessandro Rubini
This simple do-nothing mezzanine driver shows how to write a mezzanine driver, that can also handle interrupts reported by the carrier. Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Acked-by: Juan David Gonzalez Cobas <dcobas@cern.ch> Acked-by: Emilio G. Cota <cota@braap.org> Acked-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-06-18FMC: add a software carrier driverAlessandro Rubini
This fake carrier is designed to help FMC users understand how a carrier driver works, and to experiment the behaviour with EEPROM reprogramming (with a mezzanine driver commited later). This carrier can register up to 4 (fake) mezzanines. We have real carriers (both on PCI-E and VME), but they are bigger things and are not part of this submission. Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Acked-by: Juan David Gonzalez Cobas <dcobas@cern.ch> Acked-by: Emilio G. Cota <cota@braap.org> Acked-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-06-18FMC: add documentation for the coreAlessandro Rubini
This is selected sections of the current manual for fmc-bus, as developed outside of the kernel before submission. Like the other patches in this set, it corresponds to commit ab23167f of the repository at ohwr.org Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Acked-by: Juan David Gonzalez Cobas <dcobas@cern.ch> Acked-by: Emilio G. Cota <cota@braap.org> Acked-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com> Acked-by: Rob Landley <rob@landley.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-06-18FMC: add core bus driverAlessandro Rubini
This module offers registration services for both carriers (i.e. devices) and mezzanines (i.e. drivers). The matching for devices and drivers is performed according to the IPMI standard for FRU devices (Field Replaceable Units). The code includes support for parsing an SDB tree if present in the FPGA, and dumping it for diagnostics. SDB is not mandatory. Files in this commit correspond to commit ab23167f in the master branch of the project hosted on ohwr.org. Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Acked-by: Juan David Gonzalez Cobas <dcobas@cern.ch> Acked-by: Emilio G. Cota <cota@braap.org> Acked-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-06-18MAINTAINERS: add stable_kernel_rules.txt to stable maintainer informationGreg Kroah-Hartman
This hopefully will help point developers to the proper way that patches should be submitted for inclusion in the stable kernel releases. Reported-by: David Howells <dhowells@redhat.com> Acked-by: David Howells <dhowells@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-06-18x86: fix build error and kconfig for ia32_emulation and binfmtRandy Dunlap
Fix kconfig warning and build errors on x86_64 by selecting BINFMT_ELF when COMPAT_BINFMT_ELF is being selected. warning: (IA32_EMULATION) selects COMPAT_BINFMT_ELF which has unmet direct dependencies (COMPAT && BINFMT_ELF) fs/built-in.o: In function `elf_core_dump': compat_binfmt_elf.c:(.text+0x3e093): undefined reference to `elf_core_extra_phdrs' compat_binfmt_elf.c:(.text+0x3ebcd): undefined reference to `elf_core_extra_data_size' compat_binfmt_elf.c:(.text+0x3eddd): undefined reference to `elf_core_write_extra_phdrs' compat_binfmt_elf.c:(.text+0x3f004): undefined reference to `elf_core_write_extra_data' [ hpa: This was sent to me for -next but it is a low risk build fix ] Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Link: http://lkml.kernel.org/r/51C0B614.5000708@infradead.org Cc: <stable@vger.kernel.org> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2013-06-18Merge branch 'for-rmk/arch-timer-cleanups' of git://linux-arm.org/linux-mr ↵Russell King
into devel-stable Please pull these arch_timer cleanups I've been holding onto for a while. They're the same as my last posting [1], but have been rebased to v3.10-rc3. [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2013-May/170602.html -- Mark Rutland
2013-06-18Merge branch 'for-rmk/lpae' of ↵Russell King
git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into devel-stable Conflicts: arch/arm/kernel/smp.c Please pull these miscellaneous LPAE fixes I've been collecting for a while now for 3.11. They've been tested and reviewed by quite a few people, and most of the patches are pretty trivial. -- Will Deacon.
2013-06-19ARM: EXYNOS: extend soft-reset support for EXYNOS5420Chander Kashyap
Extend the soft reset support for EXYNOS5420 SoC. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-06-19ARM: EXYNOS: add secondary CPU boot base location for EXYNOS5420Chander Kashyap
The location at which the boot address is specified for secondary CPUs of EXYNOS5420 is SYSRAM base + 4. Update the cpu_boot_reg function accordingly. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-06-19clocksource: exynos_mct: use (request/free)_irq calls for local timer ↵Chander Kashyap
registration Replace the (setup/remove)_irq calls for local timer registration with (request/free)_irq calls. This generalizes the local timer registration API. Suggested by Mark Rutland. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-06-19ARM: dts: Add initial device tree support for EXYNOS5420Chander Kashyap
Add initial device tree nodes for EXYNOS5420 SoC and SMDK5420 board. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-06-19clk: exynos5420: register clocks using common clock frameworkChander Kashyap
The EXYNOS5420 clocks are statically listed and registered using the Samsung specific common clock helper functions. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-06-19ARM: EXYNOS: use four additional chipid bits to identify EXYNOS familyChander Kashyap
Use chipid[27:20] bits to identify the EXYNOS family while setting up the serial port during the uncompression setup. This uses four additional bits of chipid to identify the EXYNOS family since this is required for identifying EXYNOS5420 SoC. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-06-19serial: samsung: select EXYNOS specific driver data if ARCH_EXYNOS is definedChander Kashyap
All EXYNOS4/5 SoCs share a common driver data in the samsung serial driver. Hence, let the driver data inclusion be based on ARCH_EXYNOS instead of SOC specific definition. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Reviewed by: Girish K S <ks.giri@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-06-19ARM: EXYNOS: Add support for EXYNOS5420 SoCChander Kashyap
EXYNOS5420 is new SoC in Samsung's Exynos5 SoC series. Add initial support for this new SoC. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-06-19ARM: dts: list the CPU nodes for EXYNOS5250Chander Kashyap
Instead of having to specify the number for CPUs in EXYNOS5250 in platsmp.c file, let the number of CPUs be determined by having this information listed in EXYNOS5250 device tree file. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-06-19ARM: dts: fork out common EXYNOS5 nodesChander Kashyap
In preparation of adding support for EXYNOS5420, which has many peripherals similar to EXYNOS5250, a new common EXYNOS5 device tree source file is created out of the exising EXYNOS5250 device tree source file. Only the common nodes required for basic boot up on EXYNOS5420 based boards are moved into this new file and the rest of the common nodes would be moved subsequently. EXYNOS5440 SoC is quite different from EXYNOS5250 and EXYNOS5420. Hence it is not possible to reuse "exynos5.dtsi" for EXYNOS5440. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-06-18Merge branch 'for-rmk/hugepages' of ↵Russell King
git://git.linaro.org/people/stevecapper/linux into devel-stable These changes bring both HugeTLB support and Transparent HugePage (THP) support to ARM. Only long descriptors (LPAE) are supported in this series. The code has been tested on an Arndale board (Exynos 5250).
2013-06-18Staging: silicom: move more assignments out of if conditionsChad Williamson
Remove more assignments from if-statement conditions in bpctl_mod.c, resolving checkpatch.pl errors. Those that remain need more attention than I'm presently prepared to give them. Signed-off-by: Chad Williamson <chad@dahc.us> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-06-19ARM: EXYNOS: call scu_enable() only in case of cortex-A9 processorLeela Krishna Amudala
This patch reads the cpuid part number and if it matches with cortex-A9, calls scu_enable() Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-06-19ARM: EXYNOS: Select PINCTRL_EXYNOS for exynos4/5 at chip levelDoug Anderson
Previously if you had MACH_EXYNOS5_DT but not MACH_EXYNOS4_DT you'd be missing the pincontrol definitions. Move PINCTRL selects to the arch level since we should be enabling the code for all exynos variants. Update the PINCTRL descriptions to indicate that PINCTRL_EXYNOS is not for exynos5440. Also add basic dependencies for the PINCTRL_EXYNOS kernel config. Signed-off-by: Doug Anderson <dianders@chromium.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-06-19ARM: EXYNOS: Enable XHCI support on exynos5Vivek Gautam
This patch enables support for XHCI on exynos5 series of SOCs, to support host side USB 3.0 support. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-06-18Staging: silicom: move assignments out of if conditionsChad Williamson
Remove a bunch of assignments from if-statement conditions in bpctl_mod.c, resolving checkpatch.pl errors. (This isn't all of them, but the patch is getting rather long...) Signed-off-by: Chad Williamson <chad@dahc.us> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-06-18Staging: silicom: remove unnecessary braces in bpctl_mod.cChad Williamson
Remove unnecessary braces in bpctl_mod.c, resolving checkpatch.pl warnings. Signed-off-by: Chad Williamson <chad@dahc.us> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-06-18staging: rtl8192u: rename general variables in r819xU_phy.cXenia Ragiadakou
This patch renames the following variables: - dwRegAddr and RegAddr into reg_addr - dwData and Data into data - BitShift into bitshift - Offset into offset - NewOffset into new_offset - Bandwidth into bandwidth The renaming was done to remove camel case and unnecessary 'dw' prefix from the above variable names. Signed-off-by: Xenia Ragiadakou <burzalodowa@gmail.com> Reviewed-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-06-18staging: rtl8192u: rename *BitMask variables in r819xU_phy.cXenia Ragiadakou
This patch renames BitMask and dwBitMask variables into bitmask to remove camel case. dwBitMask in the given context can be renamed into simply bitmask since its number of bits (dw->32) can be deduced by its type which is u32. Signed-off-by: Xenia Ragiadakou <burzalodowa@gmail.com> Reviewed-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-06-18staging: rtl8192u: replace *Value variables in r819xU_phy.cXenia Ragiadakou
This patch renames the variables OriginalValue, NewValue, Original_Value, New_Value and retValue to reg, and the variables bRegValue and dwRegValue to reg_u8 and reg_u32, respectively. This is done primarily in order to reduce the variable name length and consequently line length. Also, it replaces the pair of Original and New variables with one variable. Signed-off-by: Xenia Ragiadakou <burzalodowa@gmail.com> Reviewed-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-06-18staging: rtl8192u: fix spaces around relational operators in r819xU_phy.cXenia Ragiadakou
This patch fixes the whitespace around relational operators to meet the linux kernel coding style. Signed-off-by: Xenia Ragiadakou <burzalodowa@gmail.com> Reviewed-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-06-18staging: rtl8192u: fix spaces around ';' in r819xU_phy.cXenia Ragiadakou
This patch fixes the whitespace around ';' to meet the linux kernel coding style. Signed-off-by: Xenia Ragiadakou <burzalodowa@gmail.com> Reviewed-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-06-18staging: rtl8192u: fix spaces around '=' in r819xU_phy.cXenia Ragiadakou
This patch fixes the whitespace around the assignment operator to meet linux kernel coding style. Signed-off-by: Xenia Ragiadakou <burzalodowa@gmail.com> Reviewed-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-06-18parisc: Use unshadowed index register for flush instructions in ↵John David Anglin
flush_dcache_page_asm and flush_icache_page_asm The comment at the start of pacache.S states that the base and index registers used for fdc,fic, and pdc instructions should not use shadowed registers. Although this is probably unnecessary for tmpalias flushes, there is also no reason not to comply. Signed-off-by: John David Anglin <dave.anglin@bell.net> Signed-off-by: Helge Deller <deller@gmx.de>
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