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2018-12-03drm/i915/icl: add pll mapping for DSIJani Nikula
Add encoder specific pll mapping for DSI. The differences with the DDI version are big enough to warrant a separate function. v2: add posting read (Madhav) Cc: Madhav Chauhan <madhav.chauhan@intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181203094326.28294-1-jani.nikula@intel.com
2018-12-03drm/i915/icl: Ungate DSI clocksMadhav Chauhan
Ungate the clocks on the selected port. Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/2a01b3158feda624f98581b780854fe3df8c328d.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Gate clocks for DSIMadhav Chauhan
As per BSPEC, depending on the DSI transcoder being used, DDI clock for the associated port should be gated. This patch does the same. Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/e032bc3d8fff91b8c2631c73121268214615a7e8.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: add dummy DSI GPIO element execution functionJani Nikula
Add dummy debug logging GPIO element execution function for ICL. Reviewed-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/f59009ea0a0ebc489a5ec66f387d9dcf7264141f.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Define display GPIO pins for DSIMadhav Chauhan
Display Pins are the only GPIOs that need to be used by driver for DSI panels. So driver should now have its own implementation to toggle these pins based on GPIO info received from VBT sequences. Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/e7e3bb05d4f48b1876169a69f495bcf6d511fda5.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Define Panel power ctrl registerMadhav Chauhan
There are two panel power sequencers. Each register has two addressable instances. This patch defines both the instances of Panel power control register Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/99bb687b17a9165527a6210a79271c8175c8a4e3.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Define missing bitfield for shortplug regMadhav Chauhan
This patch define missing bitfield for shortplug ctl ddi register which will be used for ICL DSI GPIO programming. Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/4b9feb75eb6c303556b91c8a23c505a4593a99a1.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Get pipe timings for DSIMadhav Chauhan
Transcoder timings for Gen11 DSI encoder is available at pipe level unlike in older platform where port specific registers need to be accessed. v2 by Jani: - get timings for (!dsi || icl) instead of (dsi && icl). Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/f60e0c1aee08248e758da3219d3239898b43ba41.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Consider DSI for getting transcoder stateMadhav Chauhan
For Gen11 DSI, we use similar registers like for eDP to find if DSI encoder is connected or not to a pipe. This patch refactors existing hsw_get_transcoder_state() to handle this. v2 by Jani: - Add WARN_ON(dsi && edp) (Ville) Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/2e10b977dfc7aa985a8559d6cd59ed0981848e95.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Configure DSI Dual link modeMadhav Chauhan
This patch configures DSI video mode dual link by programming DSS_CTL registers. v2: Use new bitfield definitions from Anusha's patch Correct register to be programmed and use max depth buffer value (James) v3 by Jani: - checkpatch fixes Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/d8962f4e1beffc2099b8bef8cb5a5191aa1d9efd.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Add DSI encoder compute config hookMadhav Chauhan
This patch implements compute config for Gen11 DSI encoder which is required at the time of modeset. For DSI 8X clock is AFE clock which is 5 times port clock. v2 by Jani: - drop the enable nop hook - fixed_mode is always true - HAS_GMCH_DISPLAY() is always false v3 by Jani: - set encoder->compute_config dropped during rebase v4 by Jani: - squash Vandita's port clock patch - remove todo comment Co-developed-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/a21574173caa5e2932d9e3c537b0931097ab5ac2.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Get HW state for DSI encoderMadhav Chauhan
This patch read out the current hw state for DSI and return true if encoder is active. v2 by Jani: - Squash connector get hw state hook here - Squash encode get hw state fix here v3 by Jani: - Add encoder->get_power_domains() (Imre) v4 by Jani: - Make encoder->get_power_domains() sensible... (Imre) v5 by Jani: - Power domains are bit positions, not bits (Stan, Imre) Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ec6da32a55b9fb045527f14e41ed3dce86d46a97.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Add get config functionality for DSIVandita Kulkarni
This patch implements the functionality for getting PIPE configuration to which DSI encoder is connected. Use the same method to get port clock like other DDI encoders. Used during the atomic modeset. v2 by Jani: - Squash Madhav's and Vandita's get config bits together - Move cnl_calc_wrpll_link() to intel_drv.h - Drop extra temp variables - Use enc_to_intel_dsi() instead of open coding Co-developed-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/f21fa4258068d04582f2bf30735e5536a8043bdf.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Allocate DSI hosts and imlement host transferMadhav Chauhan
Allocate DSI host structure for each DSI port available on gen11 and register them with DSI fwk of DRM. Some of the DSI host operations are also registered as part of this. Retrieves DSI pkt (from DSI msg) to be sent over DSI link using DRM DSI exported functions. A wrapper function is also added as "DSI host transfer" for sending DSI data/cmd. Add DSI packet payload to command payload queue using credit based mechanism for *long* packets. v2 by Jani: - indentation - Use the new credit available helper - Use int for free_credits - Add intel_dsi local variable for better code flow - Use the new credit available helper - Use int for free_credits, i, and j v3 by Jani: - Squash DSI host allocation and transfer patches together Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/af4f168ed8737d44687d8b6f21ecaa7e805eb695.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Fill DSI ports infoMadhav Chauhan
This patch fills backlight, CABC and general port info for Gen11 DSI. Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/48c9f867d61a60dc7c2ce744ac2325655652c55f.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Use the same pll functions for dsiVandita Kulkarni
The same pll manager functions can be used to enable dpll for mipi. Hence enabling the IO power and esc clock as part of pre pll enable call. v2 by Jani: - fix function parameter indent (Madhav) Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/07db5b1ce59c00295fad8a8e81908d59d8d76915.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Allocate DSI encoder/connectorMadhav Chauhan
This patch allocates memory for DSI encoder and connector which will be used for various DSI encoder/connector operations and attaching the same to DRM subsystem. This patch also extracts DSI modes info from VBT and save the desired mode info to connector. v2 by Jani: - Drop GEN11 prefix from encoder name - Drop extra parenthesis - Drop extra local variable - Squash encoder power domain here v3 by Jani: - Squash connector and connector helper functions here - Move intel_dsi_vbt_init call here Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/0197023b92ffa2d59064e30fd4ca22b6a4cff16c.1543500286.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Calculate DPLL params for DSIMadhav Chauhan
This patch calculates various DPLL dividers and parameters for DSI encoder and adjust AFE clock for DSI. For DSI, 8x clock is AFE clock. v2: Extend haswell_crtc_compute_clock() for Gen11 DSI v3: Rebase v4: use port clock instead of bitrate. v5: Reabse and remove divide by 5 v6 by Jani: - Fix indent (Madhav) - Fix dpll state calc for EDP and DP MST Co-developed-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/525d41d0d893dcdc8874d2ce70afa226227ea3f4.1543500285.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: Sanitize DDI port clock gating for DSI portsImre Deak
The requirement for the DDI port clock gating for a port in DSI mode is the opposite wrt. the case when the port is in DDI mode: the clock should be gated when the port is active and ungated when the port is inactive. Note that we cannot simply keep the DDI clock gated when the port will be only used in DSI mode: it must be gated/ungated at a specific spot in the DSI enable/disable sequence. Ensure the above for all ports of a DSI encoder, also adding a sanity check that we haven't registered another encoder using the same port (VBT should never allow this to happen). Cc: Madhav Chauhan <madhav.chauhan@intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Clint Taylor <clinton.a.taylor@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ceb14d5a68e8e23988d923d4290a4f981789e616.1543500285.git.jani.nikula@intel.com
2018-12-03drm/i915/icl: push pll to port mapping/unmapping to ddi encoder hooksJani Nikula
Unclutter the haswell_crtc_enable() and haswell_crtc_disable() functions a bit by moving the pll to port mapping and unmapping functions to the ddi encoder hooks. This allows removal of a bunch of boilerplate code from the functions. Additionally, the ICL DSI encoder needs to do the clock gating and ungating slightly differently, and this allows its own handling in a clean fashion. Cc: Madhav Chauhan <madhav.chauhan@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Madhav Chauhan <madhav.chauhan@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/f8e2982ceea4c05dc254a0c15e2b3be1d5f271d3.1543500285.git.jani.nikula@intel.com
2018-12-03drm/i915/selftests: Terminate hangcheck sanitycheck forciblyChris Wilson
If all else fails and we are stuck eternally waiting for the undying request, abandon all hope. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181203113701.12106-6-chris@chris-wilson.co.uk
2018-12-03drm/i915/ringbuffer: Clear semaphore sync registers on ring initChris Wilson
Ensure that the sync registers are cleared every time we restart the ring to avoid stale values from creeping in from random neutrinos. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108888 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181203113701.12106-3-chris@chris-wilson.co.uk
2018-12-03drm/meson: Fix an Alpha Primary Plane bug on Meson GXL/GXM SoCsNeil Armstrong
On the Amlogic GXL & GXM SoCs, a bug occurs on the primary plane when alpha is used where the alpha is not aligned with the pixel content. The workaround Amlogic implemented is to reset the OSD1 plane hardware block each time the plane is (re)enabled, solving the issue. In the reset, we still need to save the content of 2 registers which depends on the status of the plane, in addition to reload the scaler conversion matrix at the same time. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Maxime Jourdan <mjourdan@baylibre.com> Reviewed-by: Maxime Jourdan <mjourdan@baylibre.com> [narmstrong: fixed typo in commit log] Link: https://patchwork.freedesktop.org/patch/msgid/20181128100734.6536-1-narmstrong@baylibre.com
2018-11-30drm/v3d: Fix prime imports of buffers from other drivers.Eric Anholt
v3d_bo_get_pages() checks this to decide to map the imported buffer instead of the backing shmem file. The caller was about to set this value anyway, and there's no error path in between. Ideally we wouldn't even allocate the shmem file for our imports, but that's a more invasive fix. Signed-off-by: Eric Anholt <eric@anholt.net> Fixes: 57692c94dcbe ("drm/v3d: Introduce a new DRM driver for Broadcom V3D V3.x+") Link: https://patchwork.freedesktop.org/patch/msgid/20181128230927.10951-3-eric@anholt.net Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Dave Emett <david.emett@broadcom.com>
2018-11-30drm/v3d: Drop the "dev" argument to lock/unlock of BO reservations.Eric Anholt
They were unused, as Dave Emett noticed in TFU review. Signed-off-by: Eric Anholt <eric@anholt.net> Cc: Dave Emett <david.emett@broadcom.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181128230927.10951-2-eric@anholt.net Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2018-11-30drm/v3d: Add support for submitting jobs to the TFU.Eric Anholt
The TFU can copy from raster, UIF, and SAND input images to UIF output images, with optional mipmap generation. This will certainly be useful for media EGL image input, but is also useful immediately for mipmap generation without bogging the V3D core down. For now we only run the queue 1 job deep, and don't have any hang recovery (though I don't think we should need it, with TFU). Queuing multiple jobs in the HW will require synchronizing the YUV coefficient regs updates since they don't get FIFOed with the job. v2: Change the ioctl to IOW instead of IOWR, always set COEF0, explain why TFU is AUTH, clarify the syncing docs, drop the unused TFU interrupt regs (you're expected to use the hub's), don't take &bo->base for NULL bos. v3: Fix a little whitespace alignment (noticed by checkpatch), rebase on drm_sched_job_cleanup() changes. Signed-off-by: Eric Anholt <eric@anholt.net> Reviewed-by: Dave Emett <david.emett@broadcom.com> (v2) Link: https://patchwork.freedesktop.org/patch/264607/
2018-11-30drm/i915/psr: Get pipe id following atomic guidelinesJosé Roberto de Souza
As stated in struct drm_encoder, crtc field should only be used by non-atomic drivers. So here caching the pipe id in intel_psr_enable() what is way more simple and efficient than at every call to intel_psr_flush()/invalidate() get the drm.mode_config.connection_mutex lock to safely be able to get the pipe id by reading drm_connector_state.crtc. This should fix the null pointer dereference crash below as the previous way to get the pipe id was prone to race conditions. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105959 Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181128072838.22773-1-jose.souza@intel.com
2018-11-30drm/amd/display: Clean up for DCN1 clock debug loggingFatemeh Darbehani
[Why] To prepare for clock debug logging. With the exception of removing max_supported_dppclk_khz from logs, there are no functional changes. [How] Add clk_bypass struct and clean up buffer logic Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Su Chung <Su.Chung@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amd/display: 3.2.08Steven Chiu
Signed-off-by: Steven Chiu <steven.chiu@amd.com> Reviewed-by: Fatemeh Darbehani <Fatemeh.Darbehani@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amd/display: Allow clock lower on dce100David Francis
dce100 was set to always pass safe_to_lower = false to the clock manager Thus, on suspend the clocks were not being set to 0 which is incorrect behaviour This was causing s3 resume to blackscreen on intel CPUs with dce100 GPUs attached (Note that the hash in this Fixes: tag is the hash on Alex's tree) Fixes: ae7d8aeb38d7 ("drm/amd/display: remove safe_to_lower flag from dc, use 2 functions instead") Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amd/display: Program dithering if requestedSivapiriyanKumarasamy
Dithering needs to be enabled or disabled as requested. If dc_stream_update->dither_option is non-null, program the FMT blocks. Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amd/display: Copy crc_enabled when duplicating dm_crtc_stateNicholas Kazlauskas
[Why] When running igt@kms_plane@pixel-format-pipe-* tests the CRC read will time out and the test will fail. This is because the CRTC is duplicated but the crc_enabled parameter isn't copied over to the new dm_crtc_state. CRC reads will time out because amdgpu_dm_crtc_handle_crc_irq will no longer call drm_crtc_add_crc_entry. [How] Copy crc_enabled when duplicating the state. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amd/display: Add customizable tracing eventChiawen Huang
[why] add customizable log with a message input, which is for adding test log in debugging as printf function in ETW. [Usage] EVENT_LOG_CUST_MSG1("TestLog","Hello World %d=0x%x", 123, pDC); Signed-off-by: Chiawen Huang <chiawen.huang@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amd/display: Re-arrange GFX9 fieldsNevenko Stupar
For more clear usage in future Signed-off-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amd/display: fbc state could not reach while enable fbchersen wu
[WHY] fbc is within the data path from memory to dce. while re-configure mc dmif, fbc should be enabled. otherwise, fbc may not be enabled properly. [HOW] before re-configure mc dmif, disable fbc, only after dmif re-configuration fully done, enable fbc again. Signed-off-by: hersen wu <hersenxs.wu@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amd/display: Info frame cleanupHarmanprit Tatla
* Use provided infopacket in stream (if valid) instead of reconstructing in set_vendor_info_packet() * Use proper format for enums * Use dc info packet struct instead Signed-off-by: Harmanprit Tatla <Harmanprit.Tatla@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amd/display: CTS 4.2.2.7abdoulaye berthe
[Why] Failure to read Detailed Capabilities Info. [How] Read Detailed Capbilities Info 80h-08Fh. Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amd/display: Fix spelling of axis in modules/color/color_gamma.cKrunoslav Kovac
Use axis instead of axix Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amd/display: Remove unused panel patch "disconnect_delay"Joshua Aberback
[Why] This patch is for use by dm, no need for it in dc. Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amd/display: Start documentation of DCDavid Francis
[Why] There are a lot of unintuitive parts of the dm-dc interface. It would help us if these were documented to provide a common understanding of what they are supposed to do [How] Most of this documentation is stubs, to be filled out more thoroughly by the experts Not every dm-accessible function and struct is mentioned. Simple functions like getters, setters, retain, release, create, destroy can be left unadorned. Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amd/display: 3.2.07Steven Chiu
Signed-off-by: Steven Chiu <steven.chiu@amd.com> Reviewed-by: Shahin Khayyer <Shahin.Khayyer@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amd/display: fix sporadic multiple aux transaction failureYogesh Mohan Marimuthu
[why] When there are multiple aux transaction in parallel, it is sometime sporadically the aux transaction starts to continuously fail. The aux transaction was failing because the busy bit for the given gpio pin was always set. The busy bit was alway set because the programming sequence to read, modify and write busy bit was not atomic. Due to which when multiple threads are trying to modify the busy bits for their gpio pins in the same integer variable sometimes the busy bits integer variable is written with old data causing failure. [how] Instead of using individual bits to track gpio pins and grouping them to integers, one byte will be allcoated for each gpio pin. Now whenever a gpio pin needs to be set to mark being used, only writing a value of one to that byte is sufficient, other bytes are not impacted. Also no need to have atomicity with bytes unlike with bits. Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amdgpu: wait for IB test on first device openChristian König
Instead of delaying that to the first query. Otherwise we could try to use the SDMA for VM updates before the IB tests are done. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amdgpu: add VCN JPEG support amdgpu_ctx_num_entitiesAlex Deucher
Looks like it was missed when setting support was added. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amdgpu: don't expose fan attributes on APUsAlex Deucher
They don't have a fan controller. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amdgpu: Fix num_doorbell calculation issueOak Zeng
When paging queue is enabled, it use the second page of doorbell. The AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the kernel doorbells are in the first page. So with paging queue enabled, the total kernel doorbell range should be original num_doorbell plus one page (0x400 in dword), not *2. Signed-off-by: Oak Zeng <ozeng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/ttm: fix LRU handling in ttm_buffer_object_transferChristian König
We need to set the NO_EVICT flag on the ghost object or otherwise we are adding it to the LRU. When it is added to the LRU we can run into a race between destroying and evicting it again. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm/amd/display: Fix NULL ptr deref for commit_planes_to_streamNicholas Kazlauskas
[Why] With scaling, underscan and abm changes we can end up calling commit_planes_to_stream in commit_tail. This call uses dm_state->context which can be NULL if the commit was a fast update. [How] Use dc_state instead since that can't be NULL unless the system ran out of memory. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108912 Fixes: e64abff2f133 ("drm/amd/display: Use private obj helpers for dm_atomic_state") Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-30drm: Fix up drm_atomic_state_helper.[hc] extractionDaniel Vetter
I've misplaced two functions by accident: - drm_atomic_helper_duplicate_state is really part of the resume/suspend/shutdown device-wide helpers. - drm_atomic_helper_legacy_gamma_set is part of the legacy ioctl compat helpers. Move them both back. Fixes: 9ef8a9dc4b21 ("drm: Extract drm_atomic_state_helper.[hc]") Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Sean Paul <sean@poorly.run> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181128100728.4674-1-daniel.vetter@ffwll.ch
2018-11-30drm/i915/selftests: Fix live_workarounds to actually do resetsTvrtko Ursulin
The test was missing some magic ingredients to actually trigger the resets. In case of the full reset we need the I915_RESET_HANDOFF flag set, and in case of engine reset we need a busy request. Thanks to Chris for helping with reset magic. v2: * Grab RPM ref over reset. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20181130095211.23849-1-tvrtko.ursulin@linux.intel.com
generated by cgit (git 2.34.1) at 2025-09-11 17:53:48 +0000