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2019-09-11Merge branch 'devlink-unknown'David S. Miller
Simon Horman says: ==================== devlink: add unknown 'fw_load_policy' value Dirk says: Recently we added an unknown value for the 'reset_dev_on_drv_probe' devlink parameter. Extend the 'fw_load_policy' parameter in the same way. The only driver that uses this right now is the nfp driver. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2019-09-11nfp: devlink: set unknown fw_load_policyDirk van der Merwe
If the 'app_fw_from_flash' HWinfo key is invalid, set the 'fw_load_policy' devlink parameter value to unknown. Suggested-by: Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by: Dirk van der Merwe <dirk.vandermerwe@netronome.com> Signed-off-by: Simon Horman <simon.horman@netronome.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-09-11devlink: add unknown 'fw_load_policy' valueDirk van der Merwe
Similar to the 'reset_dev_on_drv_probe' devlink parameter, it is useful to have an unknown value which can be used by drivers to report that the hardware value isn't recognized or is otherwise invalid instead of failing the operation. This is especially useful for u8/enum parameters. Suggested-by: Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by: Dirk van der Merwe <dirk.vandermerwe@netronome.com> Signed-off-by: Simon Horman <simon.horman@netronome.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-09-11NFC: st95hf: fix spelling mistake "receieve" -> "receive"Colin Ian King
There is a spelling mistake in a dev_err message. Fix it. Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-09-11net/rds: An rds_sock is added too early to the hash tableKa-Cheong Poon
In rds_bind(), an rds_sock is added to the RDS bind hash table before rs_transport is set. This means that the socket can be found by the receive code path when rs_transport is NULL. And the receive code path de-references rs_transport for congestion update check. This can cause a panic. An rds_sock should not be added to the bind hash table before all the needed fields are set. Reported-by: syzbot+4b4f8163c2e246df3c4c@syzkaller.appspotmail.com Signed-off-by: Ka-Cheong Poon <ka-cheong.poon@oracle.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-09-11mac80211: Do not send Layer 2 Update frame before authorizationJouni Malinen
The Layer 2 Update frame is used to update bridges when a station roams to another AP even if that STA does not transmit any frames after the reassociation. This behavior was described in IEEE Std 802.11F-2003 as something that would happen based on MLME-ASSOCIATE.indication, i.e., before completing 4-way handshake. However, this IEEE trial-use recommended practice document was published before RSN (IEEE Std 802.11i-2004) and as such, did not consider RSN use cases. Furthermore, IEEE Std 802.11F-2003 was withdrawn in 2006 and as such, has not been maintained amd should not be used anymore. Sending out the Layer 2 Update frame immediately after association is fine for open networks (and also when using SAE, FT protocol, or FILS authentication when the station is actually authenticated by the time association completes). However, it is not appropriate for cases where RSN is used with PSK or EAP authentication since the station is actually fully authenticated only once the 4-way handshake completes after authentication and attackers might be able to use the unauthenticated triggering of Layer 2 Update frame transmission to disrupt bridge behavior. Fix this by postponing transmission of the Layer 2 Update frame from station entry addition to the point when the station entry is marked authorized. Similarly, send out the VLAN binding update only if the STA entry has already been authorized. Signed-off-by: Jouni Malinen <jouni@codeaurora.org> Reviewed-by: Johannes Berg <johannes@sipsolutions.net> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-09-11Merge branch 'fixes' into nextUlf Hansson
2019-09-11mmc: sdhci-pci-o2micro: Fix O2 Host data read/write DLL Lock phase shift issueShirley Her (SC)
Fix data read/write error in HS200 mode due to chip DLL lock phase shift Signed-off-by: Shirley Her <shirley.her@bayhubtech.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci-pci-o2micro: Move functions in preparation to fix DLL lock phase ↵Shirley Her (SC)
shift issue Move functions in preparation to fix DLL lock phase shift issue Signed-off-by: Shirley Her <shirley.her@bayhubtech.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci-pci-o2micro: Change O2 Host PLL and DLL register nameShirley Her (SC)
Change O2 Host PLL and DLL register name Signed-off-by: Shirley Her <shirley.her@bayhubtech.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci: Fix incorrect switch to HS modeAl Cooper
When switching from any MMC speed mode that requires 1.8v (HS200, HS400 and HS400ES) to High Speed (HS) mode, the system ends up configured for SDR12 with a 50MHz clock which is an illegal mode. This happens because the SDHCI_CTRL_VDD_180 bit in the SDHCI_HOST_CONTROL2 register is left set and when this bit is set, the speed mode is controlled by the SDHCI_CTRL_UHS field in the SDHCI_HOST_CONTROL2 register. The SDHCI_CTRL_UHS field will end up being set to 0 (SDR12) by sdhci_set_uhs_signaling() because there is no UHS mode being set. The fix is to change sdhci_set_uhs_signaling() to set the SDHCI_CTRL_UHS field to SDR25 (which is the same as HS) for any switch to HS mode. This was found on a new eMMC controller that does strict checking of the speed mode and the corresponding clock rate. It caused the switch to HS400 mode to fail because part of the sequence to switch to HS400 requires a switch from HS200 to HS before going to HS400. Suggested-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Al Cooper <alcooperx@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci-of-aspeed: Depend on CONFIG_OF_ADDRESSAndrew Jeffery
Resolves the following build error reported by the 0-day bot: ERROR: "of_platform_device_create" [drivers/mmc/host/sdhci-of-aspeed.ko] undefined! SPARC does not set CONFIG_OF_ADDRESS so the symbol is missing. Depend on CONFIG_OF_ADDRESS to ensure the driver is only built for supported configurations. Fixes: 2d28dbe042f4 ("mmc: sdhci-of-aspeed: Add support for the ASPEED SD controller") Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci-of-aspeed: Allow max-frequency limitation of SDCLKAndrew Jeffery
Add a get_max_clock() handler to sdhci-of-aspeed to report f_max as the maximum clock rate if it is set. This enables artificial limitation of the bus speed via max-frequency in the devicetree for e.g. the AST2600 evaluation board where I was seeing errors at 200MHz. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci-of-aspeed: Uphold clocks-on post-condition of set_clock()Andrew Jeffery
The early-exit didn't seem to matter on the AST2500, but on the AST2600 the SD clock genuinely may not be running on entry to aspeed_sdhci_set_clock(). Remove the early exit to ensure we always run sdhci_enable_clk(). Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci-of-aspeed: Drop redundant assignment to host->clockAndrew Jeffery
host->clock is already managed by sdhci_set_ios(). Suggested-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: mmc_spi: Convert to use for_each_sg()Andy Shevchenko
Use for_each_sg() macro instead of open coded variant. No functional change intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhi: fill in actual_clockTamás Szűcs
Save set clock in mmc_host actual_clock enabling exporting it via debugfs. This will indicate the precise SD clock in I/O settings rather than only the sometimes misleading requested clock. Signed-off-by: Tamás Szűcs <tszucs@protonmail.ch> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci: use lower/upper_32_bits() macros for DMA addressesMasahiro Yamada
Currently, the DMA addresses are casted to (u64) for the upper 32bits to avoid "right shift count >= width of type" warning. <linux/kernel.h> provides macros to address this, and I like the macro names are self-documenting. I introduced a new helper, sdhci_set_adma_addr() to avoid the code duplication. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci-cadence: override spec versionMasahiro Yamada
The datasheet of the IP (sd4hc) says it is compiatible with SDHCI v4, but the spec version field in the version register is read as 2 (i.e. SDHCI_SPEC_300) based on the RTL provided by Cadence. Socionext did not fix it up when it integrated the IP into the SoCs. So, it is working as SDHCI v3. It is not a real problem because there is no difference in the program flow in sdhci.c between SDHCI_SPEC_300/400, but set the real version just in case. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci: constify references of parameters to __sdhci_read_caps()Masahiro Yamada
__sdhci_read_caps() does not modify *ver, *caps, or *caps1. Probably, the caller of this function will want to constifythe parameters passed in. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: mediatek: enable SDIO IRQ low level trigger functionyong mao
SDIO IRQ is not defaultly triggered by low level, but by falling edge. It needs to set related register to enable SDIO IRQ low level trigger function. Otherwise the SDIO IRQ may be lost in some specail condition. Signed-off-by: Yong Mao <yong.mao@mediatek.com> Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci: Export sdhci_abort_tuning function symbolBen Chuang
Export sdhci_abort_tuning() function symbols which are used by other SD Host controller driver modules. Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> Co-developed-by: Michael K Johnson <johnsonm@danlj.org> Signed-off-by: Michael K Johnson <johnsonm@danlj.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11PCI: Add Genesys Logic, Inc. Vendor IDBen Chuang
Add the Genesys Logic, Inc. vendor ID to pci_ids.h. Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> Co-developed-by: Michael K Johnson <johnsonm@danlj.org> Signed-off-by: Michael K Johnson <johnsonm@danlj.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci: Add PLL Enable support to internal clock setupBen Chuang
The GL9750 and GL9755 chipsets, and possibly others, require PLL Enable setup as part of the internal clock setup as described in 3.2.1 Internal Clock Setup Sequence of SD Host Controller Simplified Specification Version 4.20. Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> Co-developed-by: Michael K Johnson <johnsonm@danlj.org> Signed-off-by: Michael K Johnson <johnsonm@danlj.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci: Change timeout of loop for checking internal clock stableBen Chuang
According to section 3.2.1 internal clock setup in SD Host Controller Simplified Specifications 4.20, the timeout of loop for checking internal clock stable is defined as 150ms. Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> Co-developed-by: Michael K Johnson <johnsonm@danlj.org> Signed-off-by: Michael K Johnson <johnsonm@danlj.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci-of-arasan: Add Support for Intel LGM eMMCRamuthevar Vadivel Muruganx
The current arasan sdhci PHY configuration isn't compatible with the PHY on Intel's LGM(Lightning Mountain) SoC devices. Therefore, add a new compatible, to adapt the Intel's LGM eMMC PHY with arasan-sdhc controller to configure the PHY. Signed-off-by: Ramuthevar Vadivel Muruganx <vadivel.muruganx.ramuthevar@linux.intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11dt-bindings: mmc: sdhci-of-arasan: Add new compatible for Intel LGM eMMCRamuthevar Vadivel Murugan
Add a new compatible to use the sdhc-arasan host controller driver with the eMMC PHY on Intel's Lightning Mountain SoC. Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci-of-aspeed: Fix return value check in aspeed_sdc_probe()Wei Yongjun
In case of error, the function of_platform_device_create() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11dt-bindings: mmc: sdhci-of-aspeed: Update example ranges propertyAndrew Jeffery
The example node in the binding uses the AST2500 compatible string for the SD controller with a 64kiB ranges property, but the SD controller is allocated 128kiB of MMIO space according to the AST2500 datasheet. Fix the example to correctly reflect the hardware in the AST2500, however it should be noted that the MMIO region is reduced to 64kiB in the AST2600 where a second SD controller block has been introduced into the address space. Also add the IBM copyright header that I left out of the initial patch. Suggested-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: bcm2835: Take SWIOTLB memory size limitation into accountStefan Wahren
Make sure the sdhost driver doesn't use requests bigger than SWIOTLB can handle. Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci-of-aspeed: Add support for the ASPEED SD controllerAndrew Jeffery
Add a minimal driver for ASPEED's SD controller, which exposes two SDHCIs. The ASPEED design implements a common register set for the SDHCIs, and moves some of the standard configuration elements out to this common area (e.g. 8-bit mode, and card detect configuration which is not currently supported). The SD controller has a dedicated hardware interrupt that is shared between the slots. The common register set exposes information on which slot triggered the interrupt; early revisions of the patch introduced an irqchip for the register, but reality is it doesn't behave as an irqchip, and the result fits awkwardly into the irqchip APIs. Instead I've taken the simple approach of using the IRQ as a shared IRQ with some minor performance impact for the second slot. Ryan was the original author of the patch - I've taken his work and massaged it to drop the irqchip support and rework the devicetree integration. The driver has been smoke tested under qemu against a minimal SD controller model and lightly tested on an ast2500-evb. Signed-off-by: Ryan Chen <ryanchen.aspeed@gmail.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11dt-bindings: mmc: sdhci-of-aspeed: Document Aspeed SD controllerAndrew Jeffery
The ASPEED SD/SDIO/MMC controller exposes two slots implementing the SDIO Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit data bus if only a single slot is enabled. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: mediatek: support 24bits segment sizeChaotian Jing
MSDC IP which support 64G DRAM will support 24bits BDMA buffer length, so add support it. Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: mediatek: fix controller busy when plug out SDChaotian Jing
when plug out SD card, may get data CRC error, the MMC core will issue CMD13 to get card status, then CMD13 timeout(due to card plug out) will trigger CMD19 tuning, first CMD19 timeout has not call msdc_reset_hw() and cause the next CMD19 gets controller busy. Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: renesas_sdhi_sys_dmac: Remove all R-Car Gen3 SoCsYoshihiro Shimoda
All R-Car Gen3 SoCs with any ES version cannot use this DMAC actually. So, this patch removes the compatibles of R-Car Gen3 SoCs from renesas_sdhi_sys_dmac_of_match. Since the previous code has an empty whitelist to prevent probing of R-Car Gen3 SoCs, no behavior changes. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: jz4740: Drop dependency on arch headerPaul Cercueil
We don't need to set the 'slave_id' anymore - that field is never read by the DMA driver. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: jz4740: Code cleanupPaul Cercueil
Fix wrong code indentation which made the code hard to read, and fix return with value in void function. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci-cadence: use struct_size() helperGustavo A. R. Silva
One of the more common cases of allocation size calculations is finding the size of a structure that has a zero-sized array at the end, along with memory for some number of elements for that array. For example: struct sdhci_cdns_priv { ... struct sdhci_cdns_phy_param phy_params[0]; }; Make use of the struct_size() helper instead of an open-coded version in order to avoid any potential type mistakes. So, replace the following form: sizeof(*priv) + sizeof(priv->phy_params[0]) * nr_phy_params with: struct_size(priv, phy_params, nr_phy_params) Also, notice that, in this case, variable priv_size is not necessary, hence it is removed. This code was detected with the help of Coccinelle. Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci-of-esdhc: add erratum A011334 support in ls1028a 1.0 SoCYinbo Zhu
This patch is to add erratum A011334 support in ls1028a 1.0 SoC Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: Remove dev_err() usage after platform_get_irq()Stephen Boyd
We don't need dev_err() messages when platform_get_irq() fails now that platform_get_irq() prints an error message itself when something goes wrong. Let's remove these prints with a simple semantic patch. // <smpl> @@ expression ret; struct platform_device *E; @@ ret = ( platform_get_irq(E, ...) | platform_get_irq_byname(E, ...) ); if ( \( ret < 0 \| ret <= 0 \) ) { ( -if (ret != -EPROBE_DEFER) -{ ... -dev_err(...); -... } | ... -dev_err(...); ) ... } // </smpl> While we're here, remove braces on if statements that only have one statement (manually). Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: linux-mmc@vger.kernel.org Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci-pci: Add another Id for Intel CMLAdrian Hunter
Add another PCI Id for Intel CML. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci-s3c: Mark expected switch fall-throughGustavo A. R. Silva
Mark switch cases where we are expecting to fall through. This patch fixes the following warnings: drivers/mmc/host/sdhci-s3c.c: In function 'sdhci_s3c_probe': drivers/mmc/host/sdhci-s3c.c:613:19: warning: this statement may fall through [-Wimplicit-fallthrough=] host->mmc->caps |= MMC_CAP_8_BIT_DATA; drivers/mmc/host/sdhci-s3c.c:614:2: note: here case 4: ^~~~ Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: atmel-mci: Mark expected switch fall-throughsGustavo A. R. Silva
Mark switch cases where we are expecting to fall through. This patch fixes the following warnings: drivers/mmc/host/atmel-mci.c: In function 'atmci_get_cap': drivers/mmc/host/atmel-mci.c:2415:30: warning: this statement may fall through [-Wimplicit-fallthrough=] host->caps.has_odd_clk_div = 1; ~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~ drivers/mmc/host/atmel-mci.c:2416:2: note: here case 0x400: ^~~~ drivers/mmc/host/atmel-mci.c:2422:28: warning: this statement may fall through [-Wimplicit-fallthrough=] host->caps.has_highspeed = 1; ~~~~~~~~~~~~~~~~~~~~~~~~~^~~ drivers/mmc/host/atmel-mci.c:2423:2: note: here case 0x200: ^~~~ drivers/mmc/host/atmel-mci.c:2426:40: warning: this statement may fall through [-Wimplicit-fallthrough=] host->caps.need_notbusy_for_read_ops = 1; ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~ drivers/mmc/host/atmel-mci.c:2427:2: note: here case 0x100: ^~~~ Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Reviewed-by: Kees Cook <keescook@chromium.org> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci-pltfm: Use devm_platform_ioremap_resource() to simplify codeJisheng Zhang
devm_platform_ioremap_resource() wraps platform_get_resource() and devm_ioremap_resource() in a single helper, let's use that helper to simplify the code. Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: mmci: Clarify comments and some code for busy detectionUlf Hansson
The code dealing with busy detection is somewhat complicated. In a way to make it a bit clearer, let's try to clarify the comments in the code about it. Additionally, move the part for clearing the so called busy start IRQ, to the place where the IRQ is actually delivered. Ideally, this should make the code a bit more robust. Finally, to improve understanding of the code and the sequence of the busy detection, move the corresponding code around a bit in mmci_cmd_irq(). Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Jean Nicolas GRAUX <jean-nicolas.graux@st.com> Reviewed-by: Jean Nicolas GRAUX <jean-nicolas.graux@st.com>
2019-09-11memstick: r592: Use dev_get_drvdataChuhong Yuan
Instead of using to_pci_dev + pci_get_drvdata, use dev_get_drvdata to make code simpler. Signed-off-by: Chuhong Yuan <hslester96@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci-pci: Use dev_get_drvdataChuhong Yuan
Instead of using to_pci_dev + pci_get_drvdata, use dev_get_drvdata to make code simpler. Signed-off-by: Chuhong Yuan <hslester96@gmail.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11mmc: sdhci-iproc: Add support for emmc2 of the BCM2711Stefan Wahren
The additional emmc2 interface of the BCM2711 is an improved version of the old emmc controller, which is able to provide DDR50 mode on the Raspberry Pi 4. Except 32 bit only register access no other quirks are known yet. Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Reviewed-by: Matthias Brugger <mbrugger@suse.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11dt-bindings: mmc: sdhci-iproc: Add brcm,bcm2711-emmc2Stefan Wahren
Add a new compatible for the additional emmc2 controller on BCM2711 and clearify usage. Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Reviewed-by: Matthias Brugger <mbrugger@suse.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-11dt-bindings: mmc: sunxi: Add H5 compatiblesMaxime Ripard
The conversion to the YAML binding left out two compatibles. Add them. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
generated by cgit (git 2.34.1) at 2025-09-18 07:03:17 +0000