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2020-07-01drm/amd/display: Passing initial SDP deadline to dmubpo-tchen
[Why] The SDP deadline indicate the vertical time to send CRC infopacket in PSR. Signed-off-by: po-tchen <po-ting.chen@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Force delay after DP receive power upMartin Tsai
[Why] Some sprcified monitor scalar cannot recognize timing change on demand. Once the link phy disable and enable during a short period then the Sink protection mechanism could keep the screen in blank and cannot be recoverred. [How] To add 100ms delay between enable link phy and link training. Signed-off-by: Martin Tsai <martin.tsai@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: 3.2.88Aric Cyr
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: [FW Promotion] Release 1.0.14Anthony Koo
[Header Changes] - Add SDP transmission deadline for PSR config cmd Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: update audio wall clock programmingCharlene Liu
[why] for audio on real TV issue. [how] -add wall clock programming for DPREF based when Pixel clock is done by DP DTO. Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Fix VBA chroma calculation for pipe splittingNicholas Kazlauskas
[Why] DML failures occur for 420 modes with dynamic pipe splitting enabled because the ChromaViewport exceeds the ChromaSurfaceWidth. This is caused by adding the viewport_width instead of the viewport_width_c. This similarly occurs for rotated modes due to the use of viewport_height instead of viewport_height_c. [How] Correct the calculations. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Revert "enable plane if plane_status changed"Hugo Hu
This reverts commmit fd0293dd5b68a67a8731d54a6b334945e4e95757. Signed-off-by: Hugo Hu <hugo.hu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Remove unused macro from dcn21Roman Li
[Why] SOC_BOUNDING_BOX_VALID is unused and not required for dcn21. [How] Remove it. Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Use u16 for drm_bpp in DSC calculationsNicholas Kazlauskas
[Why] DSC calculations fail because the u16 bits_per_pixel from the DRM struct is being casted to the u8 drm_bpp parameters and locals. Integer wraparound is happening because this value is greater than 255. [How] Use u16 to match what's in the structure instead of u8. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Move call to disable DPGWesley Chalmers
[WHY] Disabling DPG should happen after setting watermarks and clocks Signed-off-by: Wesley Chalmers <wchalmer@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: [FW Promotion] Release 1.0.13Anthony Koo
[Header Changes] - Version bump to 1.0.13 Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Fix incorrect dcn1 bandwidth calculationsMichael Strauss
[WHY] Typos cause bandwidth calculation errors, one of which can cause infinite loop on dcn1 with eDP Signed-off-by: Michael Strauss <michael.strauss@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Rework dsc to isolate FPU operationsRodrigo Siqueira
When we want to use float point operation on Linux we need to use within special kernel protection (`kernel_fpu_{begin,end}()`.), otherwise the kernel can clobber userspace FPU register state. For detecting these issues we use a tool named objtool (with -Ffa flags) to highlight the FPU problems, all warnings can be summed up as follows: ./tools/objtool/objtool check -Ffa drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.o [..] dc/dsc/rc_calc.o: warning: objtool: get_qp_set()+0x2f8: FPU instruction outside of kernel_fpu_{begin,end}() [..] dc/dsc/rc_calc.o: warning: objtool: dsc_roundf()+0x5: FPU instruction outside of kernel_fpu_{begin,end}() [..] dc/dsc/rc_calc.o: warning: objtool: dsc_ceil()+0x5: FPU instruction outside of kernel_fpu_{begin,end}() [..] dc/dsc/rc_calc.o: warning: objtool: get_ofs_set()+0x3eb: FPU instruction outside of kernel_fpu_{begin,end}() [..] dc/dsc/rc_calc.o: warning: objtool: calc_rc_params()+0x3c: FPU instruction outside of kernel_fpu_{begin,end}() [..] dc/dsc/dc_dsc.o: warning: objtool: get_dsc_bandwidth_range.isra.0()+0x8d: FPU instruction outside of kernel_fpu_{begin,end}() [..] dc/dsc/dc_dsc.o: warning: objtool: setup_dsc_config()+0x2ef: FPU instruction outside of kernel_fpu_{begin,end}() [..] dc/dsc/rc_calc_dpi.o: warning: objtool:copy_pps_fields()+0xbb: FPU instruction outside of kernel_fpu_{begin,end}() [..] dc/dsc/rc_calc_dpi.o: warning: objtool: dscc_compute_dsc_parameters()+0x7b: FPU instruction outside of kernel_fpu_{begin,end}() This commit fixes the above issues by rework DSC as described: 1. Isolate all FPU operations in a single file; 2. Use FPU flags only in the file that handles FPU operations; 3. Isolate all functions that require float point operation in static functions; 4. Add a mid-layer function that does not use any float point operation, and that could be safely invoked in other parts of the code. 5. Keep float point operation under DC_FP_{START/END} macro. CC: Christian König <christian.koenig@amd.com> CC: Alexander Deucher <Alexander.Deucher@amd.com> CC: Peter Zijlstra <peterz@infradead.org> CC: Tony Cheng <tony.cheng@amd.com> CC: Harry Wentland <hwentlan@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by: Mikita Lipski <Mikita.Lipski@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: correct alpha_en programming for new pixel formatCharlene Liu
[why] for following new format, no alpha SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT/_FIX: SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT/_FIX same as case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/amdgpu: Add SQ_DEBUG_STS_GLOBAL* registers/bitsTom St Denis
Even though they are technically MMIO registers I put the bits with the sqind block for organizational purposes. Requested for UMR debugging. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu/jpeg: fix race condition issue for jpeg startJames Zhu
Fix race condition issue when multiple jpeg starts are called. Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu/sriov: Need to clear kiq positionEmily Deng
As will clear vf fw during unload driver, to avoid idle fail. Need to clear KIQ portion also. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Ack-by: Monk.liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu/sriov: Disable pm for multiple vf sriovEmily Deng
Signed-off-by: Emily Deng <Emily.Deng@amd.com> Ack-by: Monk.liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu/sriov: Add clear vf fw supportEmily Deng
Guest VM issue the PSP clear_vf_fw command at 2 points: 1.On VF driver loading, after VF message PSP to setup rings, the next command is “clear_vf_fw” 2.On VF driver unload before VF message to destroy rings Signed-off-by: Emily Deng <Emily.Deng@amd.com> Ack-by: Monk.liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: fix the nullptr issue as for PWR IP not existing in discovery tablePrike.Liang
Fixes: c1cf79ca5ced46 ("drm/amdgpu: use IP discovery table for renoir") This nullptr issue should be specific on the Renoir series during try access the PWR_MISC_CNTL_STATUS when PWR IP not been detected by discovery table. Moreover the PWR IP not existing in Renoir series is expected therefore just avoid access PWR register in Renoir series. Signed-off-by: Prike.Liang <Prike.Liang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: Replace invalid device ID with a valid device IDSandeep Raghuraman
Initializes Powertune data for a specific Hawaii card by fixing what looks like a typo in the code. The device ID 66B1 is not a supported device ID for this driver, and is not mentioned elsewhere. 67B1 is a valid device ID, and is a Hawaii Pro GPU. I have tested on my R9 390 which has device ID 67B1, and it works fine without problems. Signed-off-by: Sandeep Raghuraman <sandy.8925@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: Fix a buffer overflow handling the serial numberDan Carpenter
The comments say that the serial number is a 16-digit HEX string so the buffer needs to be at least 17 characters to hold the NUL terminator. The other issue is that "size" returned from sprintf() is the number of characters before the NUL terminator so the memcpy() wasn't copying the terminator. The serial number needs to be NUL terminated so that it doesn't lead to a read overflow in amdgpu_device_get_serial_number(). Also it's just cleaner and faster to sprintf() directly to adev->serial[] instead of using a temporary buffer. Fixes: 81a16241114b ("drm/amdgpu: Add unique_id and serial_number for Arcturus v3") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com>
2020-07-01drm/amd/powerplay: maximum code sharing on sensor readingEvan Quan
Move the common code to amdgpu_smu.c instead of having one copy in both smu_v11_0.c and smu_v12_0.c. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: revise the calling chain on sensor readingEvan Quan
Update the calling chain from "amdgpu_smu.c -> ${asic}_ppt.c -> smu_v11/12_0.c -> amdgpu_smu.c (smu_common_read_sensor())" to " "amdgpu_smu.c -> ${asic}_ppt.c -> smu_v11/12_0.c". This can help to maintain clear code layers. More similar changes will be coming. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: drop unnecessary SMU_MSG_GetDpmClockFreq checkEvan Quan
Since SMU_MSG_GetDpmClockFreq is known to be supported for Vega20 and before ASICs only. For those ASICs supporting swSMU, it is not supported. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: drop unnecessary wrapper .populate_smc_tablesEvan Quan
Since .populate_smc_tables is just a wrapper of .set_default_dpm_table. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: drop redundant .set_min_dcefclk_deep_sleep API (v2)Evan Quan
It has exactly the same functionality as .set_deep_sleep_dcefclk. V2: correct the macro name for better trace Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd: correct trivial kernel-doc inconsistenciesColton Lewis
Silence documentation warnings by correcting kernel-doc comments. ./drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:3388: warning: Excess function parameter 'suspend' description in 'amdgpu_device_suspend' ./drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:3485: warning: Excess function parameter 'resume' description in 'amdgpu_device_resume' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:418: warning: Excess function parameter 'tbo' description in 'amdgpu_vram_mgr_del' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:418: warning: Excess function parameter 'place' description in 'amdgpu_vram_mgr_del' ./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:279: warning: Excess function parameter 'tbo' description in 'amdgpu_gtt_mgr_del' ./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:279: warning: Excess function parameter 'place' description in 'amdgpu_gtt_mgr_del' ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:332: warning: Function parameter or member 'hdcp_workqueue' not described in 'amdgpu_display_manager' ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:332: warning: Function parameter or member 'cached_dc_state' not described in 'amdgpu_display_manager' Signed-off-by: Colton Lewis <colton.w.lewis@protonmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/amdgpu: Add SQ debug registers to GFX9/GFX10 headers (v2)Tom St Denis
Requested for UMR support. (v2): Also add reg/bits for gfx9 headers Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/amdgpu: handle return value of amdgpu_driver_load_kmsLiu ChengZhe
if guest driver failed to enter full GPU access, amdgpu_driver_load_kms will unload kms and free dev->dev_private, drm_dev_register would access null pointer. Driver will enter an error state and can't be unloaded. Signed-off-by: Liu ChengZhe <ChengZhe.Liu@amd.com> Reviewed-by: Madhav Chauhan <madhav.chauhan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: move maximum sustainable clock retrieving to .hw_initEvan Quan
Since DAL settings come between .hw_init and .late_init of SMU. And DAL needs to know the maximum sustainable clocks. Signed-off-by: Evan Quan <evan.quan@amd.com> Reported-and-Tested-by: Flora Cui <flora.cui@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: add check for power limit OD supportEvan Quan
Before counting the OD percent into max power limit margin. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: correct power limit retrieving based on current power sourceEvan Quan
Instead of hard coding it as SMU_POWER_SOURCE_AC. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: drop unused code around power limitEvan Quan
Drop unused APIs, variables and argument. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: simplify the code around setting power limitEvan Quan
Use the cached max/current power limit and move the input check to the top layer. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: simplify the code around retrieving power limitEvan Quan
Use the cached max/current power limit for other cases except .late_init. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: maximize code sharing around power limitEvan Quan
Also cache the current and max power limits. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: drop unnecessary get_pptable_power_limit wrappersEvan Quan
Minor code cleanup. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: correct the APIs' namingEvan Quan
'UVD' is a HW engine name for Vega20 and before ASICs. For newer ASICs, the similar engine is named as 'VCN'. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: drop unnecessary wrappersEvan Quan
These APIs are used in amdgpu_smu.c only. Thus these wrappers are unnecessary. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: drop dead vce powergate codeEvan Quan
This was for Vega20. However Vega20 support is already dropped from current swSMU. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: add error messages on some critical pathsEvan Quan
Helpful for error diagnostic. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: forbid to use pr_err/warn/info/debugEvan Quan
Use dev_err/warn/info/dbg instead. They are more MGPU friendly. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: use MGPU friendly err/warn/info/dbg messagesEvan Quan
Use dev_err/warn/info/dbg instead of pr_err/warn/info/debug. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu/soc15: fix nullptr issue in soc15_read_register() for reg base ↵Prike.Liang
accessing The failed case is no SDMA1 IP for Renoir discovery table while in accessing SDMA1 reg base, thus need have nullptr test for soc15_read_register invoked in MMR addres space inquire opt. Signed-off-by: Prike.Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Fix indenting in dcn30_set_output_transfer_func()Dan Carpenter
These lines are a part of the if statement and they are supposed to be indented one more tab. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Use kfree() to free rgb_user in calculate_user_regamma_ramp()Denis Efremov
Use kfree() instead of kvfree() to free rgb_user in calculate_user_regamma_ramp() because the memory is allocated with kcalloc(). Signed-off-by: Denis Efremov <efremov@linux.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Use kvfree() to free coeff in build_regamma()Denis Efremov
Use kvfree() instead of kfree() to free coeff in build_regamma() because the memory is allocated with kvzalloc(). Fixes: e752058b8671 ("drm/amd/display: Optimize gamma calculations") Cc: stable@vger.kernel.org Signed-off-by: Denis Efremov <efremov@linux.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: skip BAR resizing if the bios already did itAlex Deucher
No need to do it again. Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: use the same interval as PMFW on retrieving metrics tableEvan Quan
Current 100ms interval makes no sense. User gets outdated data due to this. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit (git 2.34.1) at 2025-09-13 07:21:00 +0000