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2023-06-15arm64: dts: ti: k3: j721s2/j784s4: Switch to https linksNishanth Menon
Looks like a couple of http:// links crept in. Use https instead. While at it, drop unicode encoded character. Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230417225450.1182047-1-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: j721s2: Add VTM nodeKeerthy
VTM stands for Voltage Thermal Management. Add the thermal zones. Six sensors mapping to six thermal zones. Main0, Main1, Main2, Main3, WKUP1 & WKUP2 domains respectively. Signed-off-by: Keerthy <j-keerthy@ti.com> [bb@ti.com: rebased on v6.3-rc1] Signed-off-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20230405215328.3755561-8-bb@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: j7200: Add VTM nodeKeerthy
VTM stands for Voltage Thermal Management. Add the thermal zones. Three sensors mapping to 3 thermal zones. MCU, MPU & Main domains respectively. Signed-off-by: Keerthy <j-keerthy@ti.com> [bb@ti.com: rebased on v6.3-rc1] Signed-off-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20230405215328.3755561-7-bb@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: j721e: Add VTM nodeKeerthy
VTM stands for Voltage Thermal Management. Add the thermal zones. Five sensors mapping ton 5 thermal zones. WKUP, MPU, C7x, GPU & R5F respectively. Signed-off-by: Keerthy <j-keerthy@ti.com> [bb@ti.com: rebased on v6.3-rc1] Signed-off-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20230405215328.3755561-6-bb@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-15arm64: dts: ti: j784s4: Add VTM nodeKeerthy
VTM stands for Voltage Thermal Management. Add the thermal zones. Seven sensors mapping to seven thermal zones. Main0, Main1, Main2, Main3, Main4, WKUP1 & WKUP2 domains respectively. Signed-off-by: Keerthy <j-keerthy@ti.com> [bb@ti.com: rebased on v6.3-rc1] Signed-off-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20230405215328.3755561-5-bb@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-14arm64: dts: ti: k3-am62a-wakeup: add VTM nodeBryan Brattlof
The am62ax supports a single Voltage and Thermal Management (VTM) device located in the wakeup domain with three associated temperature monitors located in various hot spots of the die. Signed-off-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20230405215328.3755561-4-bb@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-14arm64: dts: ti: k3-am62-wakeup: add VTM nodeBryan Brattlof
The am62x supports a single Voltage and Thermal Management (VTM) module located in the wakeup domain with two associated temperature monitors located in hot spots of the die. Signed-off-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20230405215328.3755561-3-bb@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-14arm64: dts: ti: k3-am64-main: add VTM nodeBryan Brattlof
The am64x supports a single VTM module which is located in the main domain with two associated temperature monitors located at different hot spots on the die. Tested-by: Christian Gmeiner <christian.gmeiner@gmail.com> Signed-off-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20230405215328.3755561-2-bb@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-14arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIeAswath Govindraju
x1 lane PCIe slot in the common processor board is enabled and connected to J721S2 SOM. Add PCIe DT node in common processor board to reflect the same. Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Matt Ranostay <mranostay@ti.com> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230331090028.8373-9-r-gunasekaran@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-14arm64: dts: ti: k3-j721s2-main: Add PCIe device tree nodeAswath Govindraju
Add PCIe1 RC device tree node for the single PCIe instance present on the J721S2. Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Matt Ranostay <mranostay@ti.com> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230331090028.8373-8-r-gunasekaran@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-14arm64: dts: ti: k3-j721s2: Add support for OSPI FlashesAswath Govindraju
J721S2 has an OSPI NOR flash on its SOM connected the OSPI0 instance and a QSPI NOR flash on the common processor board connected to the OSPI1 instance. Add support for the same Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Matt Ranostay <mranostay@ti.com> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230331090028.8373-7-r-gunasekaran@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-14arm64: dts: ti: k3-j721s2-common-proc-board: Add USB supportAswath Govindraju
The board uses lane 1 of SERDES for USB. Set the mux accordingly. The USB controller and EVM supports super-speed for USB0 on the Type-C port. However, the SERDES has a limitation that up to 2 protocols can be used at a time. The SERDES is wired for PCIe, eDP and USB super-speed. It has been chosen to use PCIe and eDP as default. So restrict USB0 to high-speed mode. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Matt Ranostay <mranostay@ti.com> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230331090028.8373-6-r-gunasekaran@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-14arm64: dts: ti: k3-j721s2-common-proc-board: Enable SERDES0Aswath Govindraju
Configure first lane to PCIe, the second lane to USB and the last two lanes to eDP. Also, add sub-nodes to SERDES0 DT node to represent SERDES0 is connected to PCIe. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Matt Ranostay <mranostay@ti.com> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230331090028.8373-5-r-gunasekaran@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-14arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPIAswath Govindraju
Add support for two instance of OSPI in J721S2 SoC. Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Matt Ranostay <mranostay@ti.com> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230331090028.8373-4-r-gunasekaran@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-14arm64: dts: ti: k3-j721s2-main: Add SERDES and WIZ device tree nodeMatt Ranostay
Add dt node for the single instance of WIZ (SERDES wrapper) and SERDES module shared by PCIe, eDP and USB. Signed-off-by: Matt Ranostay <mranostay@ti.com> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230331090028.8373-3-r-gunasekaran@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-14arm64: dts: ti: k3-j721s2-main: Add support for USBAswath Govindraju
Add support for single instance of USB 3.0 controller in J721S2 SoC. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Matt Ranostay <mranostay@ti.com> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230331090028.8373-2-r-gunasekaran@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-14arm64: dts: ti: k3-am625: Enable Type-C port for USB0Roger Quadros
USB0 is a Type-C port with dual data role and power sink. Signed-off-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230330084954.49763-3-rogerq@kernel.org Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-14arm64: dts: ti: k3-j784s4-evm: Reserve memory for remote proc IPCHari Nagalla
Reserve memory for remote processors. Two memory regions are reserved for each remote processor. The first 1Mb region is used for virtio Vring buffers for IPC and the second region is used for holding resource table, trace buffer and as external memory to the remote processor. The mailboxes are also assigned for each remote processor. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Link: https://lore.kernel.org/r/20230502231527.25879-4-hnagalla@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-14arm64: dts: ti: k3-j784s4-main: Add C71x DSP nodesHari Nagalla
The J784S4 SoCs have four TMS320C71x DSP subsystems in the MAIN voltage domain. The functionality of these DSP subsystems is similar to the C71x DSP subsystems on earlier k3 device J721S2. Each subsystem has a 48 KB of L1D configurable SRAM/Cache and 512 KB of L2 SRAM/Cache. This subsystem has a CMMU but is not currently used. The inter-processor communication between the main A72 cores and the C71x DSPs is achieved through shared memory and mailboxes. Add the DT nodes for these DSP processor sub-systems. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Link: https://lore.kernel.org/r/20230502231527.25879-3-hnagalla@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-14arm64: dts: ti: k3-j784s4-main: Add R5F cluster nodesHari Nagalla
The J784S4 SoCs have 4 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within the MCU domain, and the remaining three clusters are present in the MAIN domain (MAIN_R5FSS0, MAIN_R5FSS1 & MAIN_R5FSS2). The functionality of the R5FSS is same as the R5FSS functionality on earlier K3 platform device J721S2. Each of the R5FSS can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). There are some IP integration differences from standard Arm R5 clusters such as the absence of an ACP port, presence of an additional TI-specific Region Address Translater (RAT) module for translating 32-bit CPU addresses into larger system bus addresses etc. Add the DT nodes for the R5F cluster/subsystems, the two R5F cores are each added as child nodes to the corresponding cluster node. The clusters are configured to run in LockStep mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. The following firmware names are used by default for these cores, and can be overridden in a board dts file if needed: MAIN R5FSS0 Core0: j784s4-main-r5f0_0-fw (both in LockStep and Split modes) MAIN R5FSS0 Core1: j784s4-main-r5f0_1-fw (needed only in Split mode) MAIN R5FSS1 Core0: j784s4-main-r5f1_0-fw (both in LockStep and Split modes) MAIN R5FSS1 Core1: j784s4-main-r5f1_1-fw (needed only in Split mode) MAIN R5FSS2 Core0: j784s4-main-r5f2_0-fw (both in LockStep and Split modes) MAIN R5FSS2 Core1: j784s4-main-r5f2_1-fw (needed only in Split mode) MCU R5FSS0 Core0: j784s4-mcu-r5f0_0-fw (needed only in Split mode) MCU R5FSS0 Core1: j784s4-mcu-r5f0_1-fw (needed only in Split mode) Signed-off-by: Hari Nagalla <hnagalla@ti.com> Link: https://lore.kernel.org/r/20230502231527.25879-2-hnagalla@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-06arm64: dts: ti: k3-j7200-som: Enable I2CUdit Kumar
This patch enables wkup_i2c0 node in board dts file along with pin mux and speed. Also enables underneath eeprom CAV24C256WE. J7200 Datasheet (Table 6-106, Section 6.4 Pin Multiplexing) : https://www.ti.com/lit/ds/symlink/dra821u.pdf J7200 User Guide (Section 4.3, Table 4-2) : https://www.ti.com/lit/ug/spruiw7a/spruiw7a.pdf Signed-off-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20230419040007.3022780-3-u-kumar1@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-06arm64: dts: ti: k3-j7200: Fix physical address of pinKeerthy
wkup_pmx splits into multiple regions. Like wkup_pmx0 -> 13 pins (WKUP_PADCONFIG 0 - 12) wkup_pmx1 -> 2 pins (WKUP_PADCONFIG 14 - 15) wkup_pmx2 -> 59 pins (WKUP_PADCONFIG 26 - 84) wkup_pmx3 -> 8 pins (WKUP_PADCONFIG 93 - 100) With this split, pin offset needs to be adjusted to match with new pmx for all pins above wkup_pmx0. Example a pin under wkup_pmx1 should start from 0 instead of old offset(0x38 WKUP_PADCONFIG 14 offset) J7200 Datasheet (Table 6-106, Section 6.4 Pin Multiplexing) : https://www.ti.com/lit/ds/symlink/dra821u.pdf Fixes: 9ae21ac445e9 ("arm64: dts: ti: k3-j7200: Fix wakeup pinmux range") Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20230419040007.3022780-2-u-kumar1@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-06-06arm64: dts: ti: k3-am62a7-sk: Describe main_uart1 and wkup_uartNishanth Menon
wkup_uart and main_uart1 on this platform is used by tifs and DM firmwares. Describe them for completeness including the pinmux. Signed-off-by: Nishanth Menon <nm@ti.com> [bb@ti.com: updated pinmux and commit subject] Signed-off-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20230425221708.549675-1-bb@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am65-main: Remove "syscon" nodes added for pcieX_ctrlNishanth Menon
Remove "syscon" nodes added for pcieX_ctrl and have the PCIe node point to the parent with an offset argument. This change is as discussed in [1]. [1] http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230424144949.244135-2-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: add missing cache propertiesKrzysztof Kozlowski
As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: k3-am6528-iot2050-basic-pg2.dtb: l3-cache0: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230421223143.115099-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am65: Drop aliasesNishanth Menon
iot boards have always defined their own aliases and with the base-board defining it's own aliases, there are no pending boards depending on common aliases defined in SoC level. aliases are meant to be defined appropriately based on the exposed interfaces at a board level, drop the aliases defined at SoC level. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com> Link: https://lore.kernel.org/r/20230419225913.663448-8-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am654-base-board: Add aliasesNishanth Menon
Introduce aliases compatible with the base definition, but focussed on the interfaces that have been exposed on the platform. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com> Link: https://lore.kernel.org/r/20230419225913.663448-7-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am654-base-board: Add board detect eepromNishanth Menon
Enable AT24CM01 on the base board using the corresponding compatible. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com> Link: https://lore.kernel.org/r/20230419225913.663448-6-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am654-base-board: Add missing PMICNishanth Menon
Add the missing vdd_mpu PMIC. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com> Link: https://lore.kernel.org/r/20230419225913.663448-5-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am654-base-board: Add VTT GPIO regulator for DDRNishanth Menon
Hold the DDR vtt regulator active for functionality. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com> Link: https://lore.kernel.org/r/20230419225913.663448-4-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am654-base-board: Rename regulator node nameNishanth Menon
Rename the regulator node names to the standard regulator-0.. numbers. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com> Link: https://lore.kernel.org/r/20230419225913.663448-3-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am654-base-board: Add missing pinmux wkup_uart, mcu_uart ↵Nishanth Menon
and mcu_i2c Many of the definitions depend on pinmux done by the bootloader. Be explicit about the pinmux for functionality and completeness. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com> Link: https://lore.kernel.org/r/20230419225913.663448-2-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am62a: Add watchdog nodesNishanth Menon
Add nodes for watchdogs: - 5 in main domain - 1 in MCU domain - 1 in wakeup domain Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230418012717.1230882-3-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am62a: Add general purpose timersNishanth Menon
Similar to commit 3308a31c507c ("arm64: dts: ti: k3-am62: Add general purpose timers for am62"), there are 12 general purpose timers on am62a7 split between 8 in main and 4 in mcu domains. The 4 in mcu domain do not have interrupts that are routable to a53. We configure the timers with the 25 MHz input clock by default as the 32.768 kHz clock may not be wired on the device. We leave the MCU domain timers clock mux unconfigured, and mark the MCU domain timers reserved. The MCU domain timers are likely reserved by the software for the ESM module. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230418012717.1230882-2-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-j721s2-common-proc-board: Drop bootargsNishanth Menon
Drop bootargs from the dts. The console arguments are already covered in stdout-path property and earlycon is a debug property that should be enabled only when debug is desired and not as default. Link: https://lore.kernel.org/linux-arm-kernel/81134eb9-2b7d-05bc-3035-a47f020861a8@linaro.org/ Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230419141222.383567-6-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-j7200-common-proc-board: Drop bootargsNishanth Menon
Drop bootargs from the dts. The console arguments are already covered in stdout-path property and earlycon is a debug property that should be enabled only when debug is desired and not as default. Link: https://lore.kernel.org/linux-arm-kernel/81134eb9-2b7d-05bc-3035-a47f020861a8@linaro.org/ Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230419141222.383567-5-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-j721e-*: Drop bootargsNishanth Menon
Drop bootargs from the dts. The console arguments are already covered in stdout-path property and earlycon is a debug property that should be enabled only when debug is desired and not as default. Link: https://lore.kernel.org/linux-arm-kernel/81134eb9-2b7d-05bc-3035-a47f020861a8@linaro.org/ Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230419141222.383567-4-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am65*: Drop bootargsNishanth Menon
Drop bootargs from the dts. earlycon is a debug property that should be enabled only when debug is desired and not as default - see referenced link on discussion on this topic. Cc: Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/linux-arm-kernel/81134eb9-2b7d-05bc-3035-a47f020861a8@linaro.org/ Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/r/20230419141222.383567-3-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am62x-sk-common: Drop bootargsNishanth Menon
Drop bootargs from the dts. The console arguments are already covered in stdout-path property and earlycon is a debug property that should be enabled only when debug is desired and not as default. Link: https://lore.kernel.org/linux-arm-kernel/81134eb9-2b7d-05bc-3035-a47f020861a8@linaro.org/ Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230419141222.383567-2-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am642-sk|evm: Drop bootargs, add aliasesNishanth Menon
Drop bootargs and add aliases based on base pinout of SK as per [1] and evm per [2]. Indices chosen attempt to maintain some level of consistency with existing aliases. While at this, drop a extra EoL. While this patch could be split, it seems trivial to add additional cleanup steps. [1] https://www.ti.com/lit/df/sprr432/sprr432.pdf [2] https://www.ti.com/lit/zip/swrr171 Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230414073328.381336-11-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am642-evm: Add VTT GPIO regulator for DDRNishanth Menon
Hold the DDR vtt regulator active for functionality. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230414073328.381336-10-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am642-evm: Rename regulator node nameNishanth Menon
Rename the regulator node names to the standard regulator-0.. numbers. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230414073328.381336-9-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am642-evm: Describe main_uart1 pinsNishanth Menon
Describe the main_uart1 pins even though it is a reserved node for hardware complete description. This is used by other users of device tree to help configure the SoC per board requirements. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230414073328.381336-8-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am642-evm: Enable main_i2c0 and eepromNishanth Menon
Enable AT24CM01 on the base board using the corresponding compatible. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230414073328.381336-7-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am642-sk: Rename regulator node nameNishanth Menon
Rename the regulator node names to the standard regulator-0.. numbers. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230414073328.381336-6-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am642-sk: Describe main_uart1 pinsNishanth Menon
Describe the main_uart1 pins even though it is a reserved node for hardware complete description. This is used by other users of device tree to help configure the SoC per board requirements. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230414073328.381336-5-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am642-sk: Enable main_i2c0 and eepromNishanth Menon
Enable AT24C512C on the base board. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230414073328.381336-4-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am642-sk: Fix mmc1 pinmuxNishanth Menon
Fix the pinmux for pulldirection to get stable sdcard behavior. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230414073328.381336-3-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-08arm64: dts: ti: k3-am64: Add general purpose timersNishanth Menon
There are 11 general purpose timers on am64 that can be used for things like PWM using pwm-omap-dmtimer driver. There are also additional four timers in the MCU domain that do not have interrupts routable for Linux. We configure the timers with the 25 MHz input clock by default as the 32.768 kHz clock may not be wired on the device. We leave the MCU domain timers clock mux unconfigured, and mark the MCU domain timers reserved. The MCU domain timers are likely reserved by the software for the ESM module. Compared to am65, the timers on am64 do not have a dedicated IO mux for the timers. On am62, the timers have different interrupts, clocks and power domains compared to am65, and the MCU timers are at a different IO address. Compared to AM62, the AM64 times have different clocks and count in main domain are different as well. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230414073328.381336-2-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-05-07Linux 6.4-rc1v6.4-rc1Linus Torvalds
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