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2025-03-06arm64: dts: airoha: en7581: Add more nodes to EN7581 SoC evaluation boardLorenzo Bianconi
Introduce the following nodes to EN7581 SoC and EN7581 evaluation board: - rng controller - pinctrl - i2c controllers Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20250221-en7581-dts-spi-pinctrl-v3-1-4719e2d01555@kernel.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-03-06arm64: dts: mediatek: mt8390-genio-common: Configure touch vreg pinsAngeloGioacchino Del Regno
Add a pinctrl configuration for the Touchscreen IC's power line to make sure that the pin is configured as GPIO and to stop relying on correct pin configuration from bootloader. Link: https://lore.kernel.org/r/20250220110948.45596-5-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-03-06arm64: dts: mediatek: mt8188-geralt: Add graph for DSI and DP displaysAngeloGioacchino Del Regno
The base SoC devicetree now defines a display controller graph: connect the board specific outputs (eDP internal display, DP external display) to fully migrate Cherry and make it finally possible to make Chromebooks and other board types to coexist without per-board driver modifications. Tested-by: Chen-Yu Tsai <wenst@chromium.org> # On MT8188 Ciri (int. and ext.) Link: https://lore.kernel.org/r/20250220110948.45596-4-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-03-06arm64: dts: rockchip: Enable hdmi out display for rk3576-evb-v10Andy Yan
Enable vop and hdmi on rk3576 evb1, so we can get a display output on this board now. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Link: https://lore.kernel.org/r/20250305025128.479245-1-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-03-04arm64: dts: rockchip: Enable hdmi display on sige5Andy Yan
Enable hdmi display on sige5 board. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Link: https://lore.kernel.org/r/20241231095728.253943-4-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-03-04arm64: dts: rockchip: Add hdmi for rk3576Andy Yan
Add hdmi and it's phy dt node for rk3576. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Link: https://lore.kernel.org/r/20241231095728.253943-3-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-03-04arm64: dts: rockchip: Add vop for rk3576Andy Yan
Add VOP and VOP_MMU found on rk3576. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Link: https://lore.kernel.org/r/20241231095728.253943-2-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-03-04arm64: dts: rockchip: Add ES8388 audio codec fallback on RK3588 boardsKrzysztof Kozlowski
Devicetree bindings for ES8388 audio codec expect the device to be marked as compatible with ES8328. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250304104200.76178-2-krzysztof.kozlowski@linaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-03-04arm64: dts: rockchip: Add ES8388 audio codec fallback on RK3399 ROC PC PLUSKrzysztof Kozlowski
Devicetree bindings for ES8388 audio codec expect the device to be marked as compatible with ES8328. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250304104200.76178-1-krzysztof.kozlowski@linaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-03-04arm64: dts: rockchip: Add uart0 pinctrl to Radxa E20CJonas Karlman
Radxa E20C route UART0 M0 pins (GPIO4_C7 and GPIO4_D0) to the onboard CH340B for debug console use. Add pinctrl for UART0 M0 pins used for serial console. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250228064024.3200000-6-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-03-04arm64: dts: rockchip: Add pinctrl and gpio nodes for RK3528Jonas Karlman
Add pinctrl and gpio nodes for RK3528 and import rk3528-pinctrl.dtsi from vendor linux-6.1-stan-rkr5 kernel with the hdmi-pins-idle node removed due to missing label reference to pcfg_output_low_pull_down. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250228064024.3200000-5-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-03-04dt-bindings: soc: rockchip: Add RK3528 ioc grf sysconJonas Karlman
The GPIO is accessible via ioc grf syscon registers on RK3528. Add compatible string for RK3528 ioc grf syscon. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250228064024.3200000-2-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-03-03arm64: dts: corstone1000: Add definitions for secondary CPU coresHugues KAMBA MPIANA
Add cpu{1-3} device nodes to the corstone1000 device tree to enable the support for secondary CPU cores. This update facilitates symmetric multiprocessing (SMP) support on the corstone1000 Fixed Virtual Platform (FVP), allowing the secondary cores to be properly initialised and utilised. Only FVP platform will have SMP support and hence the secondary cpu definitions are not added to corstone1000.dtsi. Signed-off-by: Hugues KAMBA MPIANA <hugues.kambampiana@arm.com> Message-Id: <20250303170012.469576-1-hugues.kambampiana@arm.com> (sudeep.holla: Added psci enable-method for cpu0) Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2025-02-28arm64: dts: rockchip: add usb typec host support to rk3588-jaguarHeiko Stuebner
Jaguar has two type-c ports connected to fusb302 controllers that can work both in host and device mode and can also run in display-port altmode. While these ports can work in dual-role data mode, they do not support powering the device itself as power-sink. This causes issues because the current infrastructure does not cope well with dual-role data without dual-role power. So add the necessary nodes for the type-c controllers as well as enable the relevant core usb nodes. So far host modes works reliably, but device-mode does not. So devicemode needs more investigation. Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> Tested-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250228150853.329175-1-heiko@sntech.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-28arm64: dts: rockchip: Add GPU power domain regulator dependency for RK3588Sebastian Reichel
Enabling the GPU power domain requires that the GPU regulator is enabled. The regulator is enabled at boot time, but gets disabled automatically when there are no users. This means the system might run into a failure state hanging the whole system for the following use cases: * if the GPU driver is being probed late (e.g. build as a module and firmware is not in initramfs), the regulator might already have been disabled. In that case the power domain is enabled before the regulator. * unbinding the GPU driver will disable the PM domain and the regulator. When the driver is bound again, the PM domain will be enabled before the regulator and error appears. Avoid this by adding an explicit regulator dependency to the power domain. Tested-by: Heiko Stuebner <heiko@sntech.de> Reported-by: Adrián Martínez Larumbe <adrian.larumbe@collabora.com> Tested-by: Adrian Larumbe <adrian.larumbe@collabora.com> # On Rock 5B Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20250220-rk3588-gpu-pwr-domain-regulator-v6-8-a4f9c24e5b81@kernel.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27arm64: dts: rockchip: Enable HDMI1 audio output for Orange Pi 5 UltraJimmy Hon
HDMI audio is available on the Orange Pi 5 Ultra HDMI1 TX port. Signed-off-by: Jimmy Hon <honyuenkwun@gmail.com> Link: https://lore.kernel.org/r/20250222193332.1761-6-honyuenkwun@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27arm64: dts: rockchip: Enable HDMI1 on Orange Pi 5 UltraJimmy Hon
Enable the only HDMI output port on the Orange Pi 5 Ultra Signed-off-by: Jimmy Hon <honyuenkwun@gmail.com> Tested-By: Johannes Erdfelt <johannes@erdfelt.com> Link: https://lore.kernel.org/r/20250222193332.1761-5-honyuenkwun@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27arm64: dts: rockchip: Add Orange Pi 5 Ultra boardJimmy Hon
The RK3588 Single Board Computer includes - eMMC - microSD - UART - 2 PWM LEDs - RTC - RTL8125 network controller on PCIe 2.0x1. - M.2 M-key connector routed to PCIe 3.0x4 - PWM controlled heat sink fan. - 2 USB2 ports - lower USB3 port - upper USB3 port with OTG capability - Mali GPU - SPI NOR flash - Mask Rom button - Analog audio using es8388 codec via the headset jack and onboard mic - HDMI1 - HDMI IN the vcc5v0_usb30 regulator shares the same enable gpio pin as the vcc5v0_usb20 regulator. The Orange Pi 5 Ultra is a single board computer powered by the Rockchip RK3588 with similar board layout as the 5 Max but with the HDMI0 swapped for HDMI IN. Signed-off-by: Jimmy Hon <honyuenkwun@gmail.com> Tested-By: Johannes Erdfelt <johannes@erdfelt.com> Link: https://lore.kernel.org/r/20250222193332.1761-4-honyuenkwun@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27dt-bindings: arm: rockchip: Add Xunlong Orange Pi 5 UltraJimmy Hon
Add devicetree binding for the Xunlong Orange Pi 5 Ultra board. The Orange Pi 5 Ultra is a single board computer powered by the Rockchip RK3588 with similar board layout as the 5 Max but with the HDMI0 swapped for HDMI IN. Signed-off-by: Jimmy Hon <honyuenkwun@gmail.com> Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org> Link: https://lore.kernel.org/r/20250222193332.1761-3-honyuenkwun@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27arm64: dts: rockchip: Adapt to differences between Orange Pi 5 Max and UltraJimmy Hon
The Orange Pi 5 Plus and Orange Pi 5 Max have 2SK3018s attached to the PWM LEDs. The Orange Pi 5 Ultra does not, and thus needs the PWM polarity inverted. Also remove the model/compatible from the dtsi. It should be at the board level only. Fixes: c600d252dc52 ("arm64: dts: rockchip: Add Orange Pi 5 Max board") Signed-off-by: Jimmy Hon <honyuenkwun@gmail.com> Link: https://lore.kernel.org/r/20250222193332.1761-2-honyuenkwun@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27arm64: dts: rockchip: add hdmi1 support to ROCK 5 ITXJianfeng Liu
Enable the HDMI port next to ethernet port. Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com> Link: https://lore.kernel.org/r/20250225030904.2813023-1-liujianfeng1994@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27arm64: dts: rockchip: Enable HDMI audio outputs for Rock 5BDetlev Casanova
HDMI audio is available on the Rock 5B HDMI TX ports. Enable it for both ports. Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de> Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> Fixes: 419d1918105e ("ASoC: simple-card-utils: use __free(device_node) for device node") Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/20250217215641.372723-4-detlev.casanova@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27arm64: dts: rockchip: Add HDMI audio outputs for rk3588Detlev Casanova
For hdmi0_sound, use the simple-audio-card driver with the hdmi0 QP node as CODEC and the i2s5 device as CPU. Similarly for hdmi1_sound, the CODEC is the hdmi1 node and the CPU is i2s6, but only added in the rk3588-extra.dtsi device tree as the second TX HDMI port is not available on base versions of the SoC. The simple-audio-card,mclk-fs value is set to 128 as it is done in the downstream driver. The #sound-dai-cells value is set to 0 in the hdmi0 and hdmi1 nodes so that they can be used as audio codec nodes. Tested-by: Quentin Schulz <quentin.schulz@cherry.de> # RK3588 Tiger Haikou Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> Fixes: 419d1918105e ("ASoC: simple-card-utils: use __free(device_node) for device node") Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/20250217215641.372723-3-detlev.casanova@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27arm64: dts: rockchip: Enable HDMI1 on rk3588-evb1Cristian Ciocaltea
Add the necessary DT changes to enable the second HDMI output port on Rockchip RK3588 EVB1. While at it, switch the position of &vop_mmu and @vop to maintain the alphabetical order. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20250223-vop2-hdmi1-disp-modes-v2-5-f4cec5e06fbe@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27arm64: dts: rockchip: Add HDMI1 PHY PLL clock source to VOP2 on RK3588Cristian Ciocaltea
VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and more accurate pixel clock source to improve handling of display modes up to 4K@60Hz on video ports 0, 1 and 2. The HDMI1 PHY PLL clock source cannot be added directly to vop node in rk3588-base.dtsi, along with the HDMI0 related one, because HDMI1 is an optional feature and its PHY node belongs to a separate (extra) DT file. Therefore, add the HDMI1 PHY PLL clock source to VOP2 by overwriting its clocks & clock-names properties in the extra DT file. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20250223-vop2-hdmi1-disp-modes-v2-4-f4cec5e06fbe@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27arm64: dts: rockchip: Enable HDMI1 PHY clk provider on RK3588Cristian Ciocaltea
Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock provider support"), the HDMI PHY PLL can be used as an alternative and more accurate pixel clock source for VOP2 to improve display modes handling on RK3588 SoC. Add the missing #clock-cells property to allow using the clock provider functionality of HDMI1 PHY. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20250223-vop2-hdmi1-disp-modes-v2-3-f4cec5e06fbe@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27MAINTAINERS: Add Vincenzo Frascino as Arm Morello MaintainerVincenzo Frascino
Add Vincenzo Frascino <vincenzo.frascino@arm.com> as Arm Morello Software Development Platform Maintainer. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Message-Id: <20250221180349.1413089-11-vincenzo.frascino@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2025-02-27arm64: dts: morello: Add support for fvp dtsVincenzo Frascino
The Morello architecture is an experimental extension to Armv8.2-A, which extends the AArch64 state with the principles proposed in version 7 of the Capability Hardware Enhanced RISC Instructions (CHERI) ISA. Introduce Morello fvp dts. Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Message-Id: <20250221180349.1413089-10-vincenzo.frascino@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2025-02-27arm64: dts: morello: Add support for soc dtsVincenzo Frascino
The Morello architecture is an experimental extension to Armv8.2-A, which extends the AArch64 state with the principles proposed in version 7 of the Capability Hardware Enhanced RISC Instructions (CHERI) ISA. Introduce Morello SoC dts. Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Message-Id: <20250221180349.1413089-9-vincenzo.frascino@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2025-02-27arm64: dts: morello: Add support for common functionalitiesVincenzo Frascino
The Morello architecture is an experimental extension to Armv8.2-A, which extends the AArch64 state with the principles proposed in version 7 of the Capability Hardware Enhanced RISC Instructions (CHERI) ISA. The Morello Platform (soc) and the Fixed Virtual Platfom (fvp) share some functionalities that have conveniently been included in morello.dtsi to avoid duplication. Introduce morello.dtsi. Note: Morello fvp will be introduced with a future patch series. Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Message-Id: <20250221180349.1413089-8-vincenzo.frascino@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2025-02-27dt-bindings: arm-pmu: Add support for ARM Rainier PMUVincenzo Frascino
Add support for the ARM Rainier CPU core PMU. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Message-Id: <20250221180349.1413089-6-vincenzo.frascino@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2025-02-27dt-bindings: arm: Add Rainier compatibilityVincenzo Frascino
The Arm Morello System Development Platform uses Rainier CPUs. Add compatibility to Rainier. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Message-Id: <20250221180349.1413089-5-vincenzo.frascino@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2025-02-27dt-bindings: arm: Add Morello fvp compatibilityVincenzo Frascino
Add compatibility to Arm Morello Fixed Virtual Platform. Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Message-Id: <20250221180349.1413089-4-vincenzo.frascino@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2025-02-27dt-bindings: arm: Add Morello compatibilityVincenzo Frascino
Add compatibility to Arm Morello System Development Platform. Note: Morello is at the same time the name of an Architecture [1], an SoC [2] and a Board [2]. To distinguish in between Architecture/SoC and Board we refer to the first as arm,morello and to the second as arm,morello-sdp. [1] https://developer.arm.com/Architectures/Morello [2] https://www.morello-project.org/ Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Message-Id: <20250221180349.1413089-3-vincenzo.frascino@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2025-02-27arm64: Kconfig: Update description for CONFIG_ARCH_VEXPRESSVincenzo Frascino
Update the description and contextually the help text of CONFIG_ARCH_VEXPRESS to reflect the inclusion of all ARM Ltd Platforms. Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Message-Id: <20250221180349.1413089-2-vincenzo.frascino@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2025-02-26arm64: dts: rockchip: Enable USB3 OTG on rk3588s Cool Pi 4BAndy Yan
Enable USB3 OTG and it's related PHY node. And the PHY will also be shared with the upcoming DisplayPort controller. Signed-off-by: Andy Yan <andyshrk@163.com> Link: https://lore.kernel.org/r/20250223100757.73531-1-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-26arm64: dts: rockchip: Add UART clocks for RK3528 SoCYao Zi
Add missing clocks in UART nodes for RK3528 SoC. Signed-off-by: Yao Zi <ziyao@disroot.org> Link: https://lore.kernel.org/r/20250217061142.38480-10-ziyao@disroot.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-26arm64: dts: rockchip: Add clock generators for RK3528 SoCYao Zi
Add dt node for RK3528 clock and reset unit. Clock "gmac0_clk" is generated by internal Ethernet phy, a fixed clock node is added as a placeholder to avoid orphans. Signed-off-by: Yao Zi <ziyao@disroot.org> Link: https://lore.kernel.org/r/20250217061142.38480-9-ziyao@disroot.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-26Merge branch 'v6.15-shared/clkids' into v6.15-armsoc/dts64Heiko Stuebner
2025-02-26dt-bindings: clock: Document clock and reset unit of RK3528Yao Zi
There are two types of clocks in RK3528 SoC, CRU-managed and SCMI-managed. Independent IDs are assigned to them. For the reset part, differing from previous Rockchip SoCs and downstream bindings which embeds register offsets into the IDs, gapless numbers starting from zero are used. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250217061142.38480-6-ziyao@disroot.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-26arm64: dts: apple: Add touchbar digitizer nodesSasha Finkelstein
Adds device tree entries for the touchbar digitizer Co-developed-by: Janne Grunau <j@jannau.net> Signed-off-by: Janne Grunau <j@jannau.net> Reviewed-by: Neal Gompa <neal@gompa.dev> Acked-by: Sven Peter <sven@svenpeter.dev> Signed-off-by: Sasha Finkelstein <fnkl.kernel@gmail.com> Link: https://lore.kernel.org/r/20250225-z2-dts-v1-1-df101a7c17c8@gmail.com Signed-off-by: Sven Peter <sven@svenpeter.dev>
2025-02-25arm64: dts: mediatek: mt8188: Add base display controller graphAngeloGioacchino Del Regno
The display related IPs in MT8188 are flexible and support being interconnected with different instances of DDP IPs and/or with different DDP IPs, forming a full Display Data Path that ends with an actual display output, which is board specific. Add a common graph in the main mt8188.dtsi devicetree, which is shared between all of the currently supported boards. All boards featuring any display functionality will extend this common graph to hook the display controller of the SoC to their specific output port(s). Tested-by: Chen-Yu Tsai <wenst@chromium.org> # On MT8188 Ciri (int. and ext.) Link: https://lore.kernel.org/r/20250220110948.45596-2-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-02-25arm64: dts: mediatek: mt8390-genio-700: Add USB, TypeC Controller, MUXAngeloGioacchino Del Regno
This board features multiple USB connectors: * One Type-C connector with Power Delivery and Alt. Modes; * One MicroUSB connector, also used for bootloader SW download; * One USB through the RaspberryPi-compatible pins header. Add configuration for the MTU3 controllers providing OTG support with role switching both on the MicroUSB port, RPi pins header, and the Type-C port found on this board. Moreover, add the Richtek RT1715 Type-C Power Delivery Controller which manages current source/sink, linked to the iTE IT5205 Type-C Alternate Mode Passive Mux, handling both mode switching between USB (up to 3.1 Gen2 10Gbps) and DisplayPort (four lanes, DP1.4, op to 8.1Gbps) and plug orientation switching. All USB ports reside on different controller instances, and all of them support host or gadget and can be configured as desired at runtime. Link: https://lore.kernel.org/r/20250220105514.43107-4-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-02-25arm64: dts: mediatek: mt8188: Add MTU3 nodes and correctly describe USBAngeloGioacchino Del Regno
The MT8188 SoC has three USB controllers, and all of them are behind the MTU3 DRD controller. Add the missing MTU3 nodes, default disabled, for all USB controllers and move the related XHCI nodes to be children of their MTU3 DRD to correctly describe the SoC. In order to retain USB functionality on all of the MT8188 and MT8390 boards, also move the vusb33 supply and enable the relevant MTU3 nodes with special attention to the MT8188 Geralt Chromebooks, where it was necessary to set the dr_mode of all MTU3 controllers to host to avoid interfering with the EC performing DRD on its own. Tested-by: Chen-Yu Tsai <wenst@chromium.org> # on MT8188 Ciri Link: https://lore.kernel.org/r/20250220105514.43107-3-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-02-25dt-bindings: usb: mediatek,mtk-xhci: Add port for SuperSpeed EPAngeloGioacchino Del Regno
Add a port used to connect the SuperSpeed output endpoint to a Type-C connector. Note that the MediaTek XHCI controllers are always in front of a different controller handling the USB HS (usually, MTU3), so the only port that this controller provides is SuperSpeed, while the HighSpeed one comes from elsewhere. Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250220105514.43107-2-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-02-25arm64: dts: mediatek: mt8395-genio-1200-evk: add support for TCPC portFabien Parent
Enable USB Type-C support on MediaTek MT8395 Genio 1200 EVK by adding configuration for TCPC Port, USB-C connector, MUX IT5205 and related settings. Configure dual role switch capability, set up PD (Power Delivery) profiles, and establish endpoints for SS (SuperSpeed) and HS (HighSpeed) USB. Update pinctrl configurations for U3 P0 VBus default pins and set dr_mode to "otg" for OTG (On-The-Go) mode operation. Add ITE IT5205 (TYPEC MUX) under I2C2 bus and configure its properties; also add references and configurations to 'typec-mux' node. Signed-off-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Yow-Shin Liou <yow-shin.liou@mediatek.com> Signed-off-by: Simon Sun <simon.sun@yunjingtech.com> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20250224114934.3583191-1-macpaul.lin@mediatek.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-02-25dt-bindings: usb: mtu3: Add ports propertyMacpaul Lin
Define the ports property in the mediatek,mtu3 device tree binding schema. Include definitions for port@0 and port@1, specifying their roles as High Speed (HS) and Super Speed (SS) data buses, respectively. Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20250220142230.2530583-1-macpaul.lin@mediatek.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-02-25arm64: dts: mediatek: mt8390-genio-common: Fix duplicated regulator nameLouis-Alexis Eyraud
usb_p2_vbus regulator has the same regulator-name property value as sdio_fixed_3v3, so change it to avoid this. Fixes: a4fd1943bf9b ("arm64: dts: mediatek: mt8390-genio-700-evk: update regulator names") Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20250221-fix-mtk8390-genio-common-dup-regulator-name-v1-1-92f7b9f7a414@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-02-25arm64: dts: mediatek: mt8183: Switch to Elan touchscreen driverHsin-Te Yuan
After commit 2be404486c05 ("HID: i2c-hid-of: Add reset GPIO support to i2c-hid-of"), the i2c-hid-of driver used by some mt8183 devices resets the touchscreen without having enough post-reset delay. This makes those touchscreen fail to get probed. Switch to Elan touchscreen driver, which has enough post-reset delay. Fixes: 2be404486c05 ("HID: i2c-hid-of: Add reset GPIO support to i2c-hid-of") Signed-off-by: Hsin-Te Yuan <yuanhsinte@chromium.org> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-02-23arm64: dts: rockchip: disable I2C2 bus by default on RK3588 TigerQuentin Schulz
RK3588 Tiger routes I2C2 signals to the Q7 Camera FFC connector (P2) but nothing on the SoM itself is on that bus, therefore it'll be up to the adapter connected to the Q7 Camera FFC connector (P2) to enable the I2C2 controller, if need be. Thus, disable it by default. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250218-tsd-align-haikou-v1-9-5c44d1dd8658@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
generated by cgit (git 2.34.1) at 2025-10-01 01:32:26 +0000