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2020-05-14arm64: dts: qcom: c630: Add WiFi nodeBjorn Andersson
Specify regulators and enable the &wifi node. The firmware uses the 8 bit version of the host capability message, so specify this quirk. Reviewed-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20191018055841.3729591-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-05-14arm64: dts: qcom: msm8916-samsung-a3u: add nodes for display panelMichael Srba
This patch wires up display support on Samsung Galaxy A3 2015. Signed-off-by: Michael Srba <michael.srba@seznam.cz> Link: https://lore.kernel.org/r/20200514170129.10902-1-michael.srba@seznam.cz Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-05-14ARM: dts: stm32: Split Avenger96 into DHCOR SoM and Avenger96 boardMarek Vasut
The Avenger96 is in fact an assembly of DH Electronics DHCOR SoM on top of an Avenger96 reference board. The DHCOR SoM can be populated with any STM32MP15xx. Split the DTs to reflect this such that the common SoM and Avenger96 parts are now in stm32mp15xx-dhcor-*dtsi and a specific example implementation of STM32MP157A SoM and Avenger96 board is separated into stm32mp157a-dhcor-*dts* . The stm32mp157a-avenger96.dts is retained for the sake of backward naming compatibility. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-05-14ARM: dts: stm32: Split SoC-independent parts of DHCOM SOM and PDK2Marek Vasut
The DH Electronics PDK2 can be populated with SoM with any STM32MP15xx variant. Split the SoC-independent parts of the SoM and PDK2 into the stm32mp15xx-dhcom-*.dtsi and reduce stm32mp157c-dhcom-*dts* to example of adding STM32MP157C variant of the SoM into a PDK2 carrier board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-05-14ARM: dts: stm32: Add GPIO LEDs for STM32MP1 DHCOM PDK2Marek Vasut
Add bindings for the four GPIO LEDs on DH PDK2 board. Note that LED5 GPIO-E may conflict with touchscreen interrupt, hence LED5 must be disabled when using the DH 560-200 display unit with touchscreen. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-05-14ARM: dts: stm32: Add GPIO keys for STM32MP1 DHCOM PDK2Marek Vasut
Add bindings for the four GPIO keys on DH PDK2 board. Note that TA1 key is polled because it's IRQ line conflicts with ethernet IRQ, the rest of the GPIO keys, TA2, TA3, TA4, are interrupt-driven and wake up sources. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-05-14arm64: dts: qcom: db820c: Fix invalid pm8994 suppliesBjorn Andersson
It's uncertain where the "vreg_s8a_l3a_input" comes from, but the supply for VDD_L3_L11 on PM8994 should be VREG_S3A_1P3, so correct this - and drop the vreg_s8a_l3a_input. Reviewed-by: Vinod Koul <vkoul@kernel.org> Fixes: 83d9ed4342a3 ("arm64: dts: qcom: db820c: Use regulator names from schematics") Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20200417070712.1376355-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-05-14arm64: dts: qcom: db820c: Add pmi8994 RPM regulatorsBjorn Andersson
The PMI8994 provides 3 SPMS regulators and one boost/bypass regulator. Define s1 and the boot/bypass and update pm8994 to appropriately describe the supply from PMI8994. Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20200417070303.1376290-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-05-14ARM: dts: stm32: Add IoT Box board supportManivannan Sadhasivam
IoT Box is an IoT gateway device based on Stinger96 board powered by STM32MP1 SoC, designed and manufactured by Shiratech Solutions. This device makes use of Stinger96 board by having it as a base board with one additional mezzanine on top. Following are the features exposed by this device in addition to the Stinger96 board: * WiFi/BT * CCS811 VOC sensor * 2x Digital microphones IM69D130 * 12x WS2812B LEDs Following peripherals are tested and known to work: * WiFi/BT * CCS811 More information about this device can be found in Shiratech website: https://www.shiratech-solutions.com/products/iot-box/ Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-05-14dt-bindings: arm: stm32: Document IoT Box compatibleManivannan Sadhasivam
Document devicetree compatible of Shiratech IoT Box. Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-05-14ARM: dts: stm32: Add Stinger96 board supportManivannan Sadhasivam
Stinger96 is a 96Boards IoT Extended edition board designed and manufactured by Shiratech solutions based on STM32MP1 SoC. Following are the features of this board: * 256MB DDR * 125MB NAND Flash * Onboard BG96 modem * 1x uSD * 2x USB (1 available as external connector and another connected to BG96) * 1x SPI * 1x PCM * 2x UART (apart from serial console) * 2x I2C (apart from one connected to PMIC) Following peripherals are tested and known to work: * BG96 modem * 1x I2C (LS-I2C0) * 1x SPI * 1x UART (LS-UART0) * USB (Only Gadget mode) * uSD More information about this board can be found in Shiratech website: https://www.shiratech-solutions.com/products/stinger96/ Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-05-14dt-bindings: arm: stm32: Document Stinger96 compatibleManivannan Sadhasivam
Document devicetree compatible of Shiratech Stinger96 board. Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-05-14ARM: dts: stm32: Add missing pinctrl entries for STM32MP15Manivannan Sadhasivam
These pinctrl definitions will be used by Stinger96/IoTBox boards from Shiratech. Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-05-14dt-bindings: Add vendor prefix for Shiratech SolutionsManivannan Sadhasivam
This commit adds devicetree vendor prefix for Shiratech solutions, a SOM/embedded board manufacturing company. https://www.shiratech-solutions.com/ Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-05-13arm64: dts: qcom: msm8916: Disable coresight by defaultMichael Srba
On some msm8916 devices, attempts at initializing coresight cause the boot to fail. This was fixed by disabling the coresight-related nodes in the board dts files. However, a cleaner approach was chosen for fixing the same issue on msm8998: disabling coresight by default, and enabling it in board dts files where desired. This patch implements the same solution for msm8916, removes now redundant overwrites in board specific dts files and and enables coresight in db410c's board dts in order to keep the current behavior. Fixes: b1fcc5702a41 ("arm64: dts: qcom: msm8916: Add CTI options") Signed-off-by: Michael Srba <michael.srba@seznam.cz> Reviewed-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lore.kernel.org/r/20200513184735.30104-1-michael.srba@seznam.cz Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-05-13arm64: dts: allwinner: h6: Enable CPU opp tables for Tanix TX6Clément Péron
Enable CPU opp tables for Tanix TX6. Also add the fixed regulator that provided vdd-cpu-gpu required for CPU opp tables. This voltage has been found using a voltmeter and could be wrong. Tested-by: Jernej Škrabec <jernej.skrabec@gmail.com> Signed-off-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-05-13arm64: dts: allwinner: h6: add voltage range to OPP tableClément Péron
Some boards have a fixed regulator and can't reach the voltage set by the OPP table. Add a range where the minimal voltage is the target and the maximal voltage is 1.2V. Suggested-by: Ondřej Jirman <megous@megous.com> Signed-off-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-05-13arm64: tegra: Add XUDC node on Tegra194Nagarjuna Kristam
Tegra194 has one XUSB device mode controller which can be operated in HS and SS modes. Add a DT node for this XUSB device mode controller. Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-13arm64: tegra: Kill off "simple-panel" compatiblesRob Herring
"simple-panel" is a Linux driver and has never been an accepted upstream compatible string, so remove it. Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: linux-tegra@vger.kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-13Merge branch 'for-5.8/dt-bindings' into for-5.8/arm64/dtThierry Reding
2020-05-13ARM: dts: imx6qdl-gw552x: add USB OTG supportTim Harvey
The GW552x-B board revision adds USB OTG support. Enable the device-tree node and configure the OTG_ID pin. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-05-12dt-bindings: i2c: tegra: Document Tegra210 VI I2CThierry Reding
The Tegra210 features an instance of the Tegra I2C controller that is part of the host1x domain and typically used for camera use-cases. It uses pretty much the same programming model but the registers are laid out differently. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-12dt-bindings: tegra: Add VI and CSI bindingsSowjanya Komatineni
Tegra contains VI controller which can support up to 6 MIPI CSI camera sensors. Each Tegra CSI port from CSI unit can be one-to-one mapper to VI channel and can capture from an external camera sensor or from built-in test pattern generator. This patch adds dt-bindings for Tegra VI and CSI. Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-12dt-bindings: clock: tegra: Add clock ID for CSI TPG clockSowjanya Komatineni
Tegra210 uses PLLD out internally for CSI TPG. This patch adds a clock ID for this CSI TPG clock from PLLD. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-12dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30Dmitry Osipenko
Add device-tree binding that describes CPU frequency-scaling hardware found on NVIDIA Tegra20/30 SoCs. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-12dt-bindings: memory: tegra: Add external memory controller binding for Tegra210Joseph Lo
Add the binding document for the external memory controller (EMC) which communicates with external LPDDR4 devices. It includes the bindings of the EMC node and a sub-node of EMC table which under the reserved memory node. The EMC table contains the data of the rates that EMC supported. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-12dt-bindings: clock: tegra: Remove PMC clock IDsSowjanya Komatineni
clk_out_1, clk_out_2, clk_out_3, blink are part of Tegra PMC block so these clocks should be provided by the Tegra PMC. IDs for these clocks have been defined in dt-bindings/soc/tegra-pmc.h. This patch removes the IDs for these clocks from the Tegra clock device tree bindings. Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-12arm64: dts: qcom: sc7180: Add "no-map" to cmd_db reserved areaDouglas Anderson
The example in the bindings and all the current users (except sc7180) have "no-map". I'm pretty sure we need it on sc7180 too. Add it. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Fixes: e0abc5eb526e ("arm64: dts: qcom: sc7180: Add cmd_db reserved area") Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20200424085121.1.I9d1e84d30f488cdb5a957f582abaecd2c0b24d70@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-05-12arm64: dts: qcom: msm8916-samsung-a5u: Add touchscreenStephan Gerhold
A5U uses a Melfas MMS345L touchscreen that is connected to blsp_i2c5. Add it to the device tree. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20200426140642.204395-5-stephan@gerhold.net Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-05-12arm64: dts: qcom: msm8916-samsung-a2015: Add touchscreen regulatorStephan Gerhold
A3U and A5U both use an extra touchscreen LDO regulator that provides 3.3V for the touch screen controller. Add it as fixed regulator to the common include. Cc: Michael Srba <Michael.Srba@seznam.cz> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20200426140642.204395-4-stephan@gerhold.net Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-05-12arm64: dts: qcom: msm8916: Add blsp_i2c5Stephan Gerhold
MSM8916 has another I2C QUP controller that can be enabled on GPIO 18 and 19. Add blsp_i2c5 to msm8916.dtsi and disable it by default. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20200426140642.204395-3-stephan@gerhold.net Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-05-12arm64: dts: qcom: msm8916: Add blsp_i2c1Stephan Gerhold
MSM8916 has another I2C QUP controller that can be enabled on GPIO 2 and 3. Add blsp_i2c1 to msm8916.dtsi and disable it by default. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20200426140642.204395-2-stephan@gerhold.net Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-05-12arm64: dts: qcom: sc7180: Support ETMv4 power managementSai Prakash Ranjan
Now that deep idle states are properly supported on SC7180, we need to add "coresight-loses-context-with-cpu" property to avoid failure of trace session because of losing context on entering deep idle states. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Link: https://lore.kernel.org/r/20200424111644.27970-1-saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-05-12arm64: dts: renesas: r8a774c0-cat874: Add support for AISTARVISION MIPI ↵Lad Prabhakar
Adapter V2.1 This patch adds support for AISTARVISION MIPI Adapter V2.1 board connected to G2E board. Common file aistarvision-mipi-adapter-2.1.dtsi is created which have the camera endpoint nodes for imx219 and ov5645 so that this can be re-used with other G2x platforms. r8a774c0-ek874-mipi-2.1.dts file enables the required VIN/CSI nodes and by default ties ov5645 camera endpoint to CSI2. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/1587397794-11237-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-05-11arm64: dts: sdm845: Add "no-hpd" to sn65dsi86 on chezaDouglas Anderson
We don't have the HPD line hooked up to the bridge chip. Add it as suggested in the patch ("dt-bindings: drm/bridge: ti-sn65dsi86: Document no-hpd"). NOTE: this patch isn't expected to have any effect but just keeps us cleaner for the future. Currently the driver in Linux just assumes that nobody has HPD hooked up. This change allows us to later implement HPD support in the driver without messing up sdm845-cheza. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20200507143354.v5.6.I89df9b6094549b8149aa8b8347f7401c678055b0@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-05-11arch: arm64: dts: msm8996: Add CCI nodeLoic Poulain
Add CCI controller node, which can be used to communicate with camera sensors (I2C subset). MSM8996 CCI offers two masters, i2c-bus@0 and i2c-bus@1. Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Link: https://lore.kernel.org/r/1587470425-13726-2-git-send-email-loic.poulain@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-05-11arm64: dts: msm8996: Fix CSI IRQ typesLoic Poulain
Each IRQ_TYPE_NONE interrupt causes a warning at boot. Fix that by defining an appropriate type. Fixes: e0531312e78f ("arm64: dts: qcom: msm8996: Add CAMSS support") Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Link: https://lore.kernel.org/r/1587470425-13726-1-git-send-email-loic.poulain@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-05-11arm64: dts: qcom: sc7180: Update Q6V5 MSS nodeSibi Sankar
Add TCSR node and update MSS node to support MSA based Modem boot on SC7180 SoCs. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20200421143228.8981-8-sibis@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-05-11arm64: dts: qcom: sc7180: Add Q6V5 MSS nodeSibi Sankar
This patch adds Q6V5 MSS PAS remoteproc node for SC7180 SoCs. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20200421143228.8981-7-sibis@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-05-11arm64: dts: qcom: sc7180: Update reserved memory mapSibi Sankar
Add missing regions and remove unused regions from the reserved memory map, as described in version 5. Tested-by: Evan Green <evgreen@chromium.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20200421143228.8981-6-sibis@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-05-11ARM: dts: r8a7742: Add GPIO nodesLad Prabhakar
Describe GPIO blocks in the R8A7742 device tree. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1588794695-27852-10-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-05-11ARM: dts: r8a7742: Add [H]SCIF{A|B} supportLad Prabhakar
Describe [H]SCIF{A|B} ports in the R8A7742 device tree. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1588794695-27852-8-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-05-11ARM: dts: r8a7742: Add IRQC supportLad Prabhakar
Describe the IRQC interrupt controller in the r8a7742 device tree. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/1588794695-27852-4-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-05-07ARM: dts: stm32: Add bindings for SPI2 on AV96Marek Vasut
Add SPI2 bindings to AV96 DT, the SPI2 IOs are present on low-speed expansion connector X6. This is disabled by default and can be enabled if something is connected there. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-05-07ARM: dts: stm32: Add alternate pinmux for SPI2 pinsMarek Vasut
Add another mux option for SPI2 pins, this is used on AV96 board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-05-07ARM: dts: stm32: Add bindings for ADC on AV96Marek Vasut
Add ADC bindings to AV96 DT, the ADC inputs are present on low-speed expansion connector X6. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-05-07ARM: dts: stm32: Add alternate pinmux for ADC pinsMarek Vasut
Add another mux option for ADC pins, this is used on AV96 board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-05-07ARM: dts: stm32: Add bindings for FDCAN2 on AV96Marek Vasut
Add FDCAN2 bindings to AV96 DT, the FDCAN2 is present on low-speed expansion connector X6. This is disabled by default to match the 96boards specification though. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-05-07ARM: dts: stm32: Add alternate pinmux for FDCAN2 pinsMarek Vasut
Add another mux option for FDCAN2 pins, this is used on AV96 board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-05-07ARM: dts: stm32: Add bindings for FDCAN1 on AV96Marek Vasut
Add FDCAN1 bindings to AV96 DT, the FDCAN1 is present on low-speed expansion connector X6. This is disabled by default to match the 96boards specification though. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
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