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2014-03-31MIPS: Loongson: Add Loongson-3 Kconfig optionsHuacai Chen
Added Kconfig options include: Loongson-3 CPU and machine definition, CPU cache features, UEFI-like firmware interface (LEFI), HT-linked PCI, and swiotlb support. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Hongliang Tao <taohl@lemote.com> Signed-off-by: Hua Yan <yanh@lemote.com> Tested-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Alex Smith <alex.smith@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6637 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31MIPS: Loongson: Add swiotlb to support All-Memory DMAHuacai Chen
Loongson doesn't support DMA address above 4GB traditionally. If memory is more than 4GB, CONFIG_SWIOTLB and ZONE_DMA32 should be selected. In this way, DMA pages are allocated below 4GB preferably. However, if low memory is not enough, high pages are allocated and swiotlb is used for bouncing. Moreover, we provide a platform-specific dma_map_ops::set_dma_mask() to set a device's dma_mask and coherent_dma_mask. We use these masks to distinguishes an allocated page can be used for DMA directly, or need swiotlb to bounce. Recently, we found that 32-bit DMA isn't a hardware bug, but a hardware configuration issue. So, latest firmware has enable the DMA support as high as 40-bit. To support all-memory DMA for all devices (besides the Loongson platform limit, there are still some devices have their own DMA32 limit), and also to be compatible with old firmware, we keep use swiotlb. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Hongliang Tao <taohl@lemote.com> Signed-off-by: Hua Yan <yanh@lemote.com> Tested-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Alex Smith <alex.smith@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6636 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31MIPS: Loongson 3: Add serial port supportHuacai Chen
Loongson family machines has three types of serial port: PCI UART, LPC UART and CPU internal UART. Loongson-2E and parts of Loongson-2F based machines use PCI UART; most Loongson-2F based machines use LPC UART; Loongson-2G/3A has both LPC and CPU UART but usually use CPU UART. Port address of UARTs: CPU UART: REG_BASE + OFFSET; LPC UART: LIO1_BASE + OFFSET; PCI UART: PCIIO_BASE + OFFSET. Since LPC UART are linked in "Local Bus", both CPU UART and LPC UART are called "CPU provided serial port". Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Hongliang Tao <taohl@lemote.com> Signed-off-by: Hua Yan <yanh@lemote.com> Tested-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Alex Smith <alex.smith@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6635 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31MIPS: Loongson 3: Add IRQ init and dispatch supportHuacai Chen
IRQ routing path of Loongson-3: Devices(most) --> I8259 --> HT Controller --> IRQ Routing Table --> CPU ^ | Device(legacy devices such as UART) --> Bonito ---| IRQ Routing Table route 32 INTs to CPU's INT0~INT3(IP2~IP5 of CP0), 32 INTs include 16 HT INTs(mostly), 4 PCI INTs, 1 LPC INT, etc. IP6 is used for IPI and IP7 is used for internal MIPS timer. LOONGSON_INT_ROUTER_* are IRQ Routing Table registers. I8259 IRQs are 1:1 mapped to HT1 INTs. LOONGSON_HT1_* are configuration registers of HT1 controller. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Hongliang Tao <taohl@lemote.com> Signed-off-by: Hua Yan <yanh@lemote.com> Tested-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Alex Smith <alex.smith@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6634 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31MIPS: Loongson 3: Add HT-linked PCI supportHuacai Chen
Loongson family machines use Hyper-Transport bus for inter-core connection and device connection. The PCI bus is a subordinate linked at HT1. With LEFI firmware interface, We don't need fixup for PCI irq routing (except providing a VBIOS of the integrated GPU). Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Hongliang Tao <taohl@lemote.com> Signed-off-by: Hua Yan <yanh@lemote.com> Tested-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Alex Smith <alex.smith@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6633 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31MIPS: Loongson: Add UEFI-like firmware interface (LEFI) supportHuacai Chen
The new UEFI-like firmware interface (LEFI, i.e. Loongson Unified Firmware Interface) has 3 advantages: 1, Firmware export a physical memory map which is similar to X86's E820 map, so prom_init_memory() will be more elegant that #ifdef clauses can be removed. 2, Firmware export a pci irq routing table, we no longer need pci irq routing fixup in kernel's code. 3, Firmware has a built-in vga bios, and its address is exported, the linux kernel no longer need an embedded blob. With the LEFI interface, Loongson-3A/2G and all their successors can use a unified kernel. All Loongson-based machines support this new interface except 2E/2F series. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Hongliang Tao <taohl@lemote.com> Signed-off-by: Hua Yan <yanh@lemote.com> Tested-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Alex Smith <alex.smith@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6632 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31MIPS: Loongson 3: Add Lemote-3A machtypes definitionHuacai Chen
Add four Loongson-3 based machine types: MACH_LEMOTE_A1004/MACH_LEMOTE_A1201 are laptops; MACH_LEMOTE_A1101 is mini-itx; MACH_LEMOTE_A1205 is all-in-one machine. The most significant differrent between A1004/A1201 and A1101/A1205 is the laptops have EC but others don't. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Hongliang Tao <taohl@lemote.com> Signed-off-by: Hua Yan <yanh@lemote.com> Tested-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Alex Smith <alex.smith@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6631 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31MIPS: Loongson: Add basic Loongson-3 CPU supportHuacai Chen
Basic Loongson-3 CPU support include CPU probing and TLB/cache initializing. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Hongliang Tao <taohl@lemote.com> Signed-off-by: Hua Yan <yanh@lemote.com> Tested-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Alex Smith <alex.smith@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6630 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31MIPS: Loongson: Add basic Loongson-3 definitionHuacai Chen
Loongson-3 is a multi-core MIPS family CPU, it support MIPS64R2 fully. Loongson-3 has the same IMP field (0x6300) as Loongson-2. Loongson-3 has a hardware-maintained cache, system software doesn't need to maintain coherency. Loongson-3A is the first revision of Loongson-3, and it is the quad- core version of Loongson-2G. Loongson-3A has a simplified version named Loongson-2Gq, the main difference between Loongson-3A/2Gq is 3A has two HyperTransport controller but 2Gq has only one. HT0 is used for cross- chip interconnection and HT1 is used to link PCI bus. Therefore, 2Gq cannot support NUMA but 3A can. For software, Loongson-2Gq is simply identified as Loongson-3A. Exsisting Loongson family CPUs: Loongson-1: Loongson-1A, Loongson-1B, they are 32-bit MIPS CPUs. Loongson-2: Loongson-2E, Loongson-2F, Loongson-2G, they are 64-bit single-core MIPS CPUs. Loongson-3: Loongson-3A(including so-called Loongson-2Gq), they are 64-bit multi-core MIPS CPUs. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Hongliang Tao <taohl@lemote.com> Signed-off-by: Hua Yan <yanh@lemote.com> Tested-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Alex Smith <alex.smith@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6629/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31MIPS: MT: proc: Add support for printing VPE and TC idsRalf Baechle
And there are more CPUs or configurations that want to provide special per-CPU information in /proc/cpuinfo. So I think there needs to be a hook mechanism, such as a notifier. This is a first cut only; I need to think about what sort of looking the notifier needs to have. But I'd appreciate testing on MT hardware! Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6066/
2014-03-31MIPS: BCM47XX: Add new file for device specific workaroundsRafał Miłecki
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: https://patchwork.linux-mips.org/patch/6627/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31MIPS: VR41xx: Mark GPIO lines used for IRQLinus Walleij
When an IRQ is started on a GPIO line, mark this GPIO as IRQ in the gpiolib so we can keep track of the usage centrally. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: linux-gpio@vger.kernel.org Cc: Alexandre Courbot <acourbot@nvidia.com> Patchwork: https://patchwork.linux-mips.org/patch/6417/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31MIPS: Simplify ptrace_getfpregs FPU IR retrievalPaul Burton
All architecturally defined bits in the FPU implementation register are read only & unchanging. It contains some implementation-defined bits but the architecture manual states "This bits are explicitly not intended to be used for mode control functions" which seems to provide justification for viewing the register as a whole as unchanging. This being the case we can simply re-use the value we read at boot rather than having to re-read it later, and avoid the complexity which that read entails. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6147/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31MIPS: Simplify PTRACE_PEEKUSR for FPC_EIRPaul Burton
All architecturally defined bits in the FPU implementation register are read only & unchanging. It contains some implementation-defined bits but the architecture manual states "This bits are explicitly not intended to be used for mode control functions" which seems to provide justification for viewing the register as a whole as unchanging. This being the case we can simply re-use the value we read at boot rather than having to re-read it later, and avoid the complexity which that read entails. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6144/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31MIPS: Use current_cpu_type() instead of c->cputypeWu Zhangjin
If current_cpu_type() is pre-defined in cpu-feature-overrides.h, This may save about 10k for the compressed kernel image(vmlinuz). Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1901/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31EDAC: Octeon: Add error injection supportDaniel Walker
This adds an ad-hoc error injection method. Octeon II doesn't have hardware support for injection, so this simulates it. Signed-off-by: Daniel Walker <dwalker@fifo99.com> Cc: David Daney <david.daney@cavium.com> Cc: Doug Thompson <dougthompson@xmission.com> Cc: linux-edac@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5873/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31EDAC: Octeon: Fix lack of opstate_initDaniel Walker
If the opstate_init() isn't called the driver won't start properly. I just added it in what appears to be an appropriate place. Signed-off-by: Daniel Walker <dwalker@fifo99.com> Cc: David Daney <david.daney@cavium.com> Cc: Doug Thompson <dougthompson@xmission.com> Cc: linux-edac@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5872/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31MIPS: Octeon: Remove SYS_HAS_DMA_OPSRichard Weinberger
The symbol is an orphan, get rid of it. Signed-off-by: Richard Weinberger <richard@nod.at> Cc: linux-mips@linux-mips.org (open list:MIPS) Cc: linux-kernel@vger.kernel.org (open list) Patchwork: https://patchwork.linux-mips.org/patch/6523/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31MIPS: SEAD3: Don't use module_init in non-modular sead3-mtd.c codePaul Gortmaker
The sead3-mtd.o is built for obj-y -- and hence this code is always present. It will never be modular, so using module_init as an alias for __initcall can be somewhat misleading. Fix this up now, so that we can relocate module_init from init.h into module.h in the future. If we don't do this, we'd have to add module.h to obviously non-modular code, and that would be a worse thing. Note that direct use of __initcall is discouraged, vs. one of the priority categorized subgroups. As __initcall gets mapped onto device_initcall, our use of device_initcall directly in this change means that the runtime impact is zero -- it will remain at level 6 in initcall ordering. We also fix a missing semicolon, which this change uncovers. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Reported-by: kbuild test robot <fengguang.wu@intel.com> Cc: linux-mips@linux-mips.org Cc: fengguang.wu@intel.com Patchwork: https://patchwork.linux-mips.org/patch/6412/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31MIPS: Malta: Fix CONFIG_BLK_DEV_IDE vestiges.Ralf Baechle
Don't depend on CONFIG_IDE to make this more robust. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31MIPS: Loongson: Rename PRID_IMP_LOONGSON1 and PRID_IMP_LOONGSON2Huacai Chen
Loongson-1 is a 32-bit MIPS CPU and Loongson-2/3 are 64-bit MIPS CPUs, and both Loongson-2/3 has the same PRID IMP filed (0x6300). As a result, renaming PRID_IMP_LOONGSON1 and PRID_IMP_LOONGSON2 to PRID_IMP_LOONGSON_32 and PRID_IMP_LOONGSON_64 will make more sense. Signed-off-by: Huacai Chen <chenhc@lemote.com> Tested-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Alex Smith <alex.smith@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6552/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31MIPS: No need to select ARCH_SUPPORTS_MSIPaul Bolle
Commit c24a8a7a9988 ("MIPS: Netlogic: Add MSI support for XLP") added "select ARCH_SUPPORTS_MSI". But the Kconfig symbol ARCH_SUPPORTS_MSI was already removed in v3.12, so that select is a nop. Drop it. Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Cc: Jayachandran C <jchandra@broadcom.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/6521/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31MIPS: perf: Add interAptiv supportDeng-Cheng Zhu
Choose event/cache maps and handle raw event mapping for interAptiv. Update code comments. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Reviewed-by: Markos Chandras <Markos.Chandras@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Steven.Hill@imgtec.com Patchwork: https://patchwork.linux-mips.org/patch/6528/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31MIPS: perf: Add proAptiv supportDeng-Cheng Zhu
Choose event/cache maps and handle raw event mapping for proAptiv. Update code comments. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Reviewed-by: Markos Chandras <Markos.Chandras@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Steven.Hill@imgtec.com Patchwork: https://patchwork.linux-mips.org/patch/6527/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31MIPS: perf: Rename 74K event/cache maps in preparation for Aptiv supportDeng-Cheng Zhu
74K/proAptiv share the same event/cache maps. So it's better to change the names of the existing mipsxx74Kcore_[event|cache]_map. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Reviewed-by: Markos Chandras <Markos.Chandras@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Steven.Hill@imgtec.com Patchwork: https://patchwork.linux-mips.org/patch/6526/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-31GFS2: Fix uninitialized VFS inode in gfs2_create_inodeAbhi Das
When gfs2_create_inode() fails due to quota violation, the VFS inode is not completely uninitialized. This can cause a list corruption error. This patch correctly uninitializes the VFS inode when a quota violation occurs in the gfs2_create_inode codepath. Resolves: rhbz#1059808 Signed-off-by: Abhi Das <adas@redhat.com> Signed-off-by: Steven Whitehouse <swhiteho@redhat.com>
2014-03-31drm/omap: Don't dereference list head when the connectors list is emptyLaurent Pinchart
The connectors list iterator returns the list head when the list is empty. Fix it by returning NULL in that case. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-03-31drm/msm/mdp: add timeout for irq waitRob Clark
Make things recover a bit more gracefully if we get stuck with no vblank irq ever coming. Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-03-31drm/msm: validate flags, etcRob Clark
After reading a nice article on LWN[1], I went back and double checked my handling of invalid-input checking. Turns out there were a couple places I had missed. Since the driver is fairly young, and the devices it supports are really only just barely usable for basic stuff (serial console) with an upstream kernel, I think we should fix this now and revert specific parts of this patch later in the unlikely event that a regression is reported. [1] https://lwn.net/Articles/588444/ Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-03-31drm/msm: use componentised device supportRob Clark
Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-03-31drm/msm: add chip-id paramRob Clark
Some of the w/a or different behavior of userspace blob driver seem to be keyed to gpu patch revision, rather than gpu-id. So expose the full chip-id to userspace so it can DTRT. Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-03-31drm/msm: crank down gpu when inactiveRob Clark
Shut down the clks when the gpu has nothing to do. A short inactivity timer is used to provide a low pass filter for power transitions. Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-03-31drm/msm: spin helperRob Clark
Helper macro to simplify places where we need to poll with timeout waiting for gpu. Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-03-31drm/msm: add hang_debug module paramRob Clark
msm.hang_debug=y will dump out current register values if the gpu locks up, for easier debugging. Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-03-31drm/msm: hdmi audio supportRob Clark
Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-03-31dm thin: simplify pool_is_congestedMike Snitzer
The pool is congested if the pool is in PM_OUT_OF_DATA_SPACE mode. This is more explicit/clear/efficient than inferring whether or not the pool is congested by checking if retry_on_resume_list is empty. Signed-off-by: Mike Snitzer <snitzer@redhat.com> Acked-by: Joe Thornber <ejt@redhat.com>
2014-03-31ARC: Remove unused DT template fileVineet Gupta
Commit abe11ddea1d759f9 "Enabling DeviceTree for Angel4 board" made angel4.dts as default leaving the orphan skeleton file behind. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-03-31drm/i915: prefer struct drm_i915_private to drm_i915_private_tJani Nikula
Remove the rest of the references to drm_i915_private_t. No functional changes. Signed-off-by: Jani Nikula <jani.nikula@intel.com> [danvet: Drop hunk in i915_cmd_parser.c] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-03-31drm/i915/overlay: prefer struct drm_i915_private to drm_i915_private_tJani Nikula
No functional changes. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-03-31drm/i915/ringbuffer: prefer struct drm_i915_private to drm_i915_private_tJani Nikula
No functional changes. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-03-31drm/i915/display: prefer struct drm_i915_private to drm_i915_private_tJani Nikula
No functional changes. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-03-31drm/i915/irq: prefer struct drm_i915_private to drm_i915_private_tJani Nikula
Also drop any unnecessary casts. No functional changes. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-03-31drm/i915/gem: prefer struct drm_i915_private to drm_i915_private_tJani Nikula
No functional changes. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-03-31drm/i915/dma: prefer struct drm_i915_private to drm_i915_private_tJani Nikula
Also drop any unnecessary casts. No functional changes. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-03-31drm/i915/debugfs: prefer struct drm_i915_private to drm_i915_private_tJani Nikula
No functional changes. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-03-31m68k: Update defconfigs for v3.14-rc1Geert Uytterhoeven
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2014-03-31mfd: wm5110: Correct default for HEADPHONE_DETECT_1Charles Keepax
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2014-03-31mfd: arizona: Correct small errors in the DT binding documentationCharles Keepax
This patch does not alter the binding at all it only brings the documentation up to date with the existing binding. Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2014-03-31mfd: arizona: Mark DSP clocking register as volatileCharles Keepax
The DSPs will often control there own clock speeds whilst running as such we should mark the registers controlling this as volatile. Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2014-03-31mfd: devicetree: bindings: Add pm8xxx RTC descriptionJosh Cartwright
The PM8xxx family of PMICs contain an RTC. This RTC is described as a subnode of the PM8xxx. Document these bindings, and replace the pwrkey node in the example with the RTC, which is now described in this document. While we're here, add a short description to the device tree bindings describing what the the PM8xxx devices are and how they are expected to be used. Signed-off-by: Josh Cartwright <joshc@codeaurora.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
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