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2022-05-10clk: samsung: exynosautov9: add cmu_fsys2 clock supportChanho Park
CMU_FSYS2 is responsible to control clocks of BLK_FSYS2 which includes ufs and ethernet IPs. This patch adds some essential clocks to be controlled by ethernet/ufs drivers instead of listing full clocks. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20220504075154.58819-8-chanho61.park@samsung.com
2022-05-10clk: samsung: exynosautov9: add cmu_busmc clock supportChanho Park
CMU_BUSMC is responsible to control clocks of BLK_BUSMC which represents Data/Peri buses. Most clocks except PDMA/SPDMA are not necessary to be controlled by HLOS. So, this adds PDMA/SPDMA gate clocks. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20220504075154.58819-7-chanho61.park@samsung.com
2022-05-10clk: samsung: exynosautov9: add cmu_peris clock supportChanho Park
CMU_PERIS is responsible to control clocks of BLK_PERIS which has OPT/MCT/WDT and TMU. This patch only supports WDT gate clocks and all other clocks except WDT will be supported later. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20220504075154.58819-6-chanho61.park@samsung.com
2022-05-10clk: samsung: exynosautov9: add cmu_core clock supportChanho Park
Add CMU_CORE clock which represents Core BUS clocks. The source clocks of this CMU block are oscclk or dout_clkcmu_core_bus. Thus, two source clocks should be provided via device tree. All the gate clocks are defined as CLK_IS_CRITICAL because they control(gate/ungate) core bus clocks but not been assigned to any drivers. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20220504075154.58819-5-chanho61.park@samsung.com
2022-05-10clk: samsung: add top clock support for Exynos Auto v9 SoCChanho Park
This adds support for CMU_TOP which generates clocks for all the function blocks such as CORE, FSYS0/1/2, PERIC0/1 and so on. For CMU_TOP, PLL_SHARED0,1,2,3 and 4 will be the sources of this block and they will generate bus clocks. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20220504075154.58819-4-chanho61.park@samsung.com
2022-05-06clk: sunxi-ng: h616: Add PLL derived 32KHz clockAndre Przywara
The RTC section of the H616 manual mentions in a half-sentence the existence of a clock "32K divided by PLL_PERI(2X)". This is used as one of the possible inputs for the mux that selects the clock for the 32 KHz fanout pad. On the H616 this is routed to pin PG10, and some boards use that clock output to compensate for a missing 32KHz crystal. On the OrangePi Zero2 this is for instance connected to the LPO pin of the WiFi/BT chip. The new RTC clock binding requires this clock to be named as one input clock, so we need to expose this to the DT. In contrast to the D1 SoC there does not seem to be a gate for this clock, so just use a fixed divider clock, using a newly assigned clock number. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220428230933.15262-3-andre.przywara@arm.com
2022-05-06clk: sunxi-ng: h6-r: Add RTC gate clockAndre Przywara
The H6 and H616 feature an (undocumented) bus clock gate for accessing the RTC registers. This seems to be enabled at reset (or by the BootROM), so we got away without it so far, but exists regardless. Since the new RTC clock binding for the H616 requires this "bus" clock to be specified in the DT, add this to R_CCU clock driver and expose it on the DT side with a new number. We do this for both the H6 and H616, but mark it as IGNORE_UNUSED, as we cannot reference it in any H6 DTs. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220428230933.15262-2-andre.przywara@arm.com
2022-05-06clk: tegra: Update kerneldoc to match prototypesThierry Reding
For some DFLL functions, the kerneldoc comments don't match the function prototype. Fix them up to avoid some warnings at build time. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-05-06clk: renesas: r9a09g011: Add eth clock and reset entriesPhil Edworthy
Add ethernet clock/reset entries to CPG driver. Note that the AXI and CHI clocks are both enabled and disabled using the same register bit. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220504145454.71287-2-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06clk: renesas: Add RZ/V2M support using the rzg2l driverPhil Edworthy
The Renesas RZ/V2M SoC is very similar to RZ/G2L, though it doesn't have any CLK_MON registers. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220503115557.53370-11-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05clk: renesas: rzg2l: Add support for RZ/V2M reset monitor regPhil Edworthy
The RZ/V2M doesn't have a matching set of reset monitor regs for each reset reg like the RZ/G2L. Instead, it has a single CPG_RST_MON reg which has a single bit per module. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220503115557.53370-10-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05clk: renesas: rzg2l: Make use of CLK_MON registers optionalPhil Edworthy
The RZ/V2M SoC doesn't use CLK_MON registers, so make them optional. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220503115557.53370-9-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05clk: renesas: rzg2l: Set HIWORD mask for all mux and dividersPhil Edworthy
All of the muxes and dividers that can be modified require the HIWORD flags, so make the macros set them. It won't affect read only muxes and dividers. This will make the clock tables a little easier to read, particularly for new SoCs coming. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220503115557.53370-8-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05clk: renesas: rzg2l: Add read only versions of the clk macrosPhil Edworthy
This just makes the clk tables easier to read. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Link: https://lore.kernel.org/r/20220503115557.53370-7-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macroPhil Edworthy
We only ever use ARRAY_SIZE() to populate the number of parents, so move this into the macro to always detect it automatically. This also makes the tables of clocks a little simpler. Similarly for the DEF_SD_MUX macro. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Link: https://lore.kernel.org/r/20220503115557.53370-6-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05dt-bindings: clock: renesas,rzg2l: Document RZ/V2M SoCPhil Edworthy
Document the device tree binding for the Renesas RZ/V2M (r9a09g011) SoC. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20220503115557.53370-4-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05Merge tag 'renesas-r9a09g011-dt-binding-defs-tag' into renesas-clk-for-v5.19Geert Uytterhoeven
Renesas RZ/V2M DT Binding Definitions Clock definitions for the Renesas RZ/V2M (R9A09G011) SoC, shared by driver and DT source files.
2022-05-05clk: renesas: r9a07g044: Fix OSTM1 module clock nameGeert Uytterhoeven
Fix a typo in the name of the "ostm1_pclk" clock. This change has no run-time impact. Fixes: 161450134ae9bab3 ("clk: renesas: r9a07g044: Add OSTM clock and reset entries") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/e0eff1f57378ec29d0d3f1a7bdd7e380583f736b.1651494871.git.geert+renesas@glider.be
2022-05-05clk: renesas: r9a07g043: Add clock and reset entries for ADCBiju Das
Add clock and reset entries for ADC block in CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220501083450.26541-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05clk: renesas: r9a07g043: Add TSU clock and reset entryBiju Das
Add TSU clock and reset entry to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220501083450.26541-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05clk: renesas: r9a07g043: Add RSPI clock and reset entriesBiju Das
Add RSPI{0,1,2} clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220501083450.26541-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05clk: renesas: r9a07g043: Add clock and reset entries for SPI Multi I/O Bus ↵Biju Das
Controller Add clock and reset entries for SPI Multi I/O Bus Controller. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220501083450.26541-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05clk: renesas: r9a07g044: Add DSI clock and reset entriesBiju Das
Add DSI clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220430114156.6260-10-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05clk: renesas: r9a07g044: Add LCDC clock and reset entriesBiju Das
Add LCDC clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220430114156.6260-9-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05clk: renesas: r9a07g044: Add M4 Clock supportBiju Das
Add support for M4 clock which is sourced from pll2_533_div2. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220430114156.6260-8-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05clk: renesas: r9a07g044: Add M3 Clock supportBiju Das
Add support for M3 clock which is sourced from DSI divider connected to PLL5_4 mux. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220430114156.6260-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks supportBiju Das
Add support for {M2, M2_DIV2} clocks which is sourced from pll3_533. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220430114156.6260-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05clk: renesas: r9a07g044: Add M1 clock supportBiju Das
Add support for M1 clock which is sourced from FOUTPOSTDIV. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220430114156.6260-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05clk: renesas: rzg2l: Add DSI divider clk supportBiju Das
M3 clock is sourced from DSI Divider (DSIDIVA * DSIDIVB) This patch add support for DSI divider clk by combining DSIDIVA and DSIDIVB. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220430114156.6260-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05clk: renesas: rzg2l: Add PLL5_4 clk mux supportBiju Das
Add PLL5_4 clk mux support to select clock from clock sources FOUTPOSTDIV and FOUT1PH0. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220430114156.6260-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05clk: renesas: rzg2l: Add FOUTPOSTDIV clk supportBiju Das
PLL5 generates FOUTPOSTDIV clk and is sourced by LCDC/DSI modules. The FOUTPOSTDIV is connected to PLL5_4 MUX. Video clock is sourced from DSI divider which is connected to PLL5_4 MUX. This patch adds support for generating FOUTPOSTDIV clk. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220430114156.6260-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05dt-bindings: clock: Add r9a09g011 CPG Clock DefinitionsPhil Edworthy
Define RZ/V2M (R9A09G011) Clock Pulse Generator module clock outputs (CPG_CLK_ON* registers), and reset definitions (CPG_RST_* registers) in Section 48.5 ("Register Description") of the RZ/V2M Hardware User's Manual (Rev. 1.10, Sep. 2021). Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220503115557.53370-3-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05dt-bindings: clock: add Exynos Auto v9 SoC CMU bindingsChanho Park
Add dt-schema for Exynos Auto v9 SoC clock controller. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220504075154.58819-3-chanho61.park@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-05-05dt-bindings: clock: add clock binding definitions for Exynos Auto v9Chanho Park
Add device tree clock binding definitions for below CMU blocks. - CMU_TOP - CMU_BUSMC - CMU_CORE - CMU_FYS2 - CMU_PERIC0 / C1 - CMU_PERIS Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Chanho Park <chanho61.park@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20220504075154.58819-2-chanho61.park@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-05-04clk: tegra: Replace .round_rate() with .determine_rate()Rajkumar Kasirajan
Replace the .round_rate() callback with .determine_rate() which can consider max_rate imposed by clk_set_max_rate() while rounding the clock rate. Note that if the .determine_rate() callback is defined it will be called instead of the .round_rate() callback when calling clk_round_rate(). By using .determine_rate(), the maximum rate returned when calling clk_round_rate() is now limited by the current max_rate. Signed-off-by: Rajkumar Kasirajan <rkasirajan@nvidia.com> [jonathanh@nvidia.com: checkpatch fixes and commit message update] Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-05-04clk: tegra: Register clocks from root to leafTimo Alho
Current clock initialization causes intermediate registering of orphan clocks (i.e. a clock without a parent registered). CCF keeps track of orphan clocks and any time a new clock is registered, it will loop through the list of orphan and queries if the parent is now available. This operation triggers one or more clock operations, which are IPCs with BPMP-FW. Hence, due to the order in which the clocks appear currently, this causes > 5000 IPC messages to be sent to BPMP-FW during clock initialization. Optimize the clock probing by registering clocks hierarchically from root clock towards leafs. Signed-off-by: Timo Alho <talho@nvidia.com> [jonathanh@nvidia.com: checkpatch fixes] Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-05-04clk: tegra: Add missing reset deassertionDiogo Ivo
Commit 4782c0a5dd88 ("clk: tegra: Don't deassert reset on enabling clocks") removed deassertion of reset lines when enabling peripheral clocks. This breaks the initialization of the DFLL driver which relied on this behaviour. Fix this problem by adding explicit deassert/assert requests to the driver. Tested on Google Pixel C. Cc: stable@vger.kernel.org Fixes: 4782c0a5dd88 ("clk: tegra: Don't deassert reset on enabling clocks") Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-05-03clk: rockchip: Mark hclk_vo as critical on rk3568Sascha Hauer
Whenever pclk_vo is enabled hclk_vo must be enabled as well. This is described in the Reference Manual as: | 2.8.6 NIU Clock gating reliance | | A part of niu clocks have a dependence on another niu clock in order to | sharing the internal bus. When these clocks are in use, another niu | clock must be opened, and cannot be gated. These clocks and the special | clock on which they are relied are as following: | | Clocks which have dependency The clock which can not be gated | ----------------------------------------------------------------- | ... | pclk_vo_niu, hclk_vo_s_niu hclk_vo_niu | ... The clock framework doesn't offer a way to enable clock B whenever clock A is enabled, at least not when B is not an ancestor of A. Workaround this by marking hclk_vo as critical so it is never disabled. This is suboptimal in terms of power consumption, but a stop gap solution until the clock framework has a way to deal with this. We have this clock tree: | aclk_vo 2 2 0 300000000 0 0 50000 Y | aclk_hdcp 0 0 0 300000000 0 0 50000 N | pclk_vo 2 3 0 75000000 0 0 50000 Y | pclk_edp_ctrl 0 0 0 75000000 0 0 50000 N | pclk_dsitx_1 0 0 0 75000000 0 0 50000 N | pclk_dsitx_0 1 2 0 75000000 0 0 50000 Y | pclk_hdmi_host 1 2 0 75000000 0 0 50000 Y | pclk_hdcp 0 0 0 75000000 0 0 50000 N | hclk_vo 2 5 0 150000000 0 0 50000 Y | hclk_hdcp 0 0 0 150000000 0 0 50000 N | hclk_vop 0 2 0 150000000 0 0 50000 N Without this patch the edp, dsitx, hdmi and hdcp driver would enable their clocks which then enables pclk_vo, but hclk_vo stays disabled and register accesses just hang. hclk_vo is enabled by the VOP2 driver, so reproducibility of this issue depends on the probe order. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Reviewed-by: Robin Murphy <robin.murphy@arm.com> Tested-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20220422072841.2206452-2-s.hauer@pengutronix.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-05-02clk: imx8mp: add clkout1/2 supportLucas Stach
clkout1 and clkout2 allow to supply clocks from the SoC to the board, which is used by some board designs to provide reference clocks. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220427162131.3127303-1-l.stach@pengutronix.de Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-05-02clk: imx: scu: Use pm_runtime_resume_and_get to fix pm_runtime_get_sync() usageMiaoqian Lin
If the device is already in a runtime PM enabled state pm_runtime_get_sync() will return 1. Also, we need to call pm_runtime_put_noidle() when pm_runtime_get_sync() fails, so use pm_runtime_resume_and_get() instead. this function will handle this. Fixes: 78edeb080330 ("clk: imx: scu: add runtime pm support") Signed-off-by: Miaoqian Lin <linmq006@gmail.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220425011117.25093-1-linmq006@gmail.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-04-29clk: renesas: cpg-mssr: Add support for R-Car V4HYoshihiro Shimoda
Initial CPG support for R-Car V4H (r8a779g0). Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20220428135058.597586-2-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-29Merge tag 'renesas-r8a779g0-dt-binding-defs-tag' into renesas-clk-for-v5.19Geert Uytterhoeven
Renesas R-Car V4H DT Binding Definitions Clock and Power Domain definitions for the Renesas R-Car V4H (R8A779G0) SoC, shared by driver and DT source files.
2022-04-29clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4Yoshihiro Shimoda
R-Car V4H (r8a779g0) has PLL4 so that add CLK_TYPE_GEN4_PLL4. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20220425064201.459633-5-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28clk: renesas: r9a07g043: Add WDT clock and reset entriesBiju Das
Add WDT{0,2} clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220425095244.156720-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28clk: renesas: r9a07g043: Add OSTM clock and reset entriesBiju Das
Add OSTM{0,1,2} clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220425095244.156720-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28clk: renesas: r9a07g043: Add clock and reset entries for CANFDBiju Das
Add clock and reset entries for CANFD in CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220425095244.156720-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28clk: renesas: r9a07g043: Add USB clocks/resetsBiju Das
Add clock/reset entries for USB PHY control, USB2.0 host and device. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220425095244.156720-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28clk: renesas: r9a07g043: Add SSIF-2 clock and reset entriesBiju Das
Add SSIF-2{0,1,2,3} clock and reset entries in CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220425095244.156720-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28clk: renesas: r9a07g043: Add I2C clocks/resetsBiju Das
Add I2C{0,1,2,3} clock and reset entries. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220425095244.156720-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28clk: renesas: r9a06g032: Fix the RTC hclock descriptionMiquel Raynal
It needs to be un-gated, but also a reset must be released and an idle flag should also be disabled. The driver already supports all these operations, so update the description of the RTC hclock to fit these requirements. Fixes: 4c3d88526eba2143 ("clk: renesas: Renesas R9A06G032 clock driver") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20220421090016.79517-3-miquel.raynal@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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