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2016-11-24KVM: PPC: Book3S HV: Adjust host/guest context switch for POWER9Paul Mackerras
Some special-purpose registers that were present and accessible by guests on POWER8 no longer exist on POWER9, so this adds feature sections to ensure that we don't try to context-switch them when going into or out of a guest on POWER9. These are all relatively obscure, rarely-used registers, but we had to context-switch them on POWER8 to avoid creating a covert channel. They are: SPMC1, SPMC2, MMCRS, CSIGR, TACR, TCSCR, and ACOP. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2016-11-24KVM: PPC: Book3S HV: Set partition table rather than SDR1 on POWER9Paul Mackerras
On POWER9, the SDR1 register (hashed page table base address) is no longer used, and instead the hardware reads the HPT base address and size from the partition table. The partition table entry also contains the bits that specify the page size for the VRMA mapping, which were previously in the LPCR. The VPM0 bit of the LPCR is now reserved; the processor now always uses the VRMA (virtual real-mode area) mechanism for guest real-mode accesses in HPT mode, and the RMO (real-mode offset) mechanism has been dropped. When entering or exiting the guest, we now only have to set the LPIDR (logical partition ID register), not the SDR1 register. There is also no requirement now to transition via a reserved LPID value. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2016-11-24KVM: PPC: Book3S HV: Adapt to new HPTE format on POWER9Paul Mackerras
This adapts the KVM-HV hashed page table (HPT) code to read and write HPT entries in the new format defined in Power ISA v3.00 on POWER9 machines. The new format moves the B (segment size) field from the first doubleword to the second, and trims some bits from the AVA (abbreviated virtual address) and ARPN (abbreviated real page number) fields. As far as possible, the conversion is done when reading or writing the HPT entries, and the rest of the code continues to use the old format. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2016-11-23PCI: Set Read Completion Boundary to 128 iff Root Port supports it (_HPX)Johannes Thumshirn
Per PCIe spec r3.0, sec 2.3.1.1, the Read Completion Boundary (RCB) determines the naturally aligned address boundaries on which a Read Request may be serviced with multiple Completions: - For a Root Complex, RCB is 64 bytes or 128 bytes This value is reported in the Link Control Register Note: Bridges and Endpoints may implement a corresponding command bit which may be set by system software to indicate the RCB value for the Root Complex, allowing the Bridge/Endpoint to optimize its behavior when the Root Complex’s RCB is 128 bytes. - For all other system elements, RCB is 128 bytes Per sec 7.8.7, if a Root Port only supports a 64-byte RCB, the RCB of all downstream devices must be clear, indicating an RCB of 64 bytes. If the Root Port supports a 128-byte RCB, we may optionally set the RCB of downstream devices so they know they can generate larger Completions. Some BIOSes supply an _HPX that tells us to set RCB, even though the Root Port doesn't have RCB set, which may lead to Malformed TLP errors if the Endpoint generates completions larger than the Root Port can handle. The IBM x3850 X6 with BIOS version -[A8E120CUS-1.30]- 08/22/2016 supplies such an _HPX and a Mellanox MT27500 ConnectX-3 device fails to initialize: mlx4_core 0000:41:00.0: command 0xfff timed out (go bit not cleared) mlx4_core 0000:41:00.0: device is going to be reset mlx4_core 0000:41:00.0: Failed to obtain HW semaphore, aborting mlx4_core 0000:41:00.0: Fail to reset HCA ------------[ cut here ]------------ kernel BUG at drivers/net/ethernet/mellanox/mlx4/catas.c:193! After 6cd33649fa83 ("PCI: Add pci_configure_device() during enumeration") and 7a1562d4f2d0 ("PCI: Apply _HPX Link Control settings to all devices with a link"), we apply _HPX settings to *all* devices, not just those hot-added after boot. Before 7a1562d4f2d0, we didn't touch the Mellanox RCB, and the device worked. After 7a1562d4f2d0, we set its RCB to 128, and it failed. Set the RCB to 128 iff the Root Port supports a 128-byte RCB. Otherwise, set RCB to 64 bytes. This effectively ignores what _HPX tells us about RCB. Note that this change only affects _HPX handling. If we have no _HPX, this does nothing with RCB. [bhelgaas: changelog, clear RCB if not set for Root Port] Fixes: 6cd33649fa83 ("PCI: Add pci_configure_device() during enumeration") Fixes: 7a1562d4f2d0 ("PCI: Apply _HPX Link Control settings to all devices with a link") Link: https://bugzilla.kernel.org/show_bug.cgi?id=187781 Tested-by: Frank Danapfel <fdanapfe@redhat.com> Signed-off-by: Johannes Thumshirn <jthumshirn@suse.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Myron Stowe <myron.stowe@redhat.com> CC: stable@vger.kernel.org # v3.18+
2016-11-23PCI: Export pcie_find_root_portJohannes Thumshirn
Export pcie_find_root_port() so we can use it outside of PCIe-AER error injection. Signed-off-by: Johannes Thumshirn <jthumshirn@suse.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-11-24Merge remote-tracking branch 'remotes/powerpc/topic/ppc-kvm' into kvm-ppc-nextPaul Mackerras
This merges in the ppc-kvm topic branch to get changes to arch/powerpc code that are necessary for adding POWER9 KVM support. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2016-11-23Merge branch 'stable' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile Pull arch/tile bugfix from Chris Metcalf: "This fixes a bug that causes reboots after 208 days of uptime :-)" * 'stable' of git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile: tile: avoid using clocksource_cyc2ns with absolute cycle count
2016-11-23clk: sunxi-ng: enable so-said LDOs for A33 SoC's pll-mipi clockIcenowy Zheng
In the user manual of A33 SoC, the bit 22 and 23 of pll-mipi control register is called "LDO{1,2}_EN", and according to the BSP source code from Allwinner [1], the LDOs are enabled during the clock's enabling process. The clock failed to generate output if the two LDOs are not enabled. Add the two bits to the clock's gate bits, so that the LDOs are enabled when the PLL is enabled. [1] https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun8iw5.c#L429 Fixes: d05c748bd730 ("clk: sunxi-ng: Add A33 CCU support") Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-11-23tile: avoid using clocksource_cyc2ns with absolute cycle countChris Metcalf
For large values of "mult" and long uptimes, the intermediate result of "cycles * mult" can overflow 64 bits. For example, the tile platform calls clocksource_cyc2ns with a 1.2 GHz clock; we have mult = 853, and after 208.5 days, we overflow 64 bits. Since clocksource_cyc2ns() is intended to be used for relative cycle counts, not absolute cycle counts, performance is more importance than accepting a wider range of cycle values. So, just use mult_frac() directly in tile's sched_clock(). Commit 4cecf6d401a0 ("sched, x86: Avoid unnecessary overflow in sched_clock") by Salman Qazi results in essentially the same generated code for x86 as this change does for tile. In fact, a follow-on change by Salman introduced mult_frac() and switched to using it, so the C code was largely identical at that point too. Peter Zijlstra then added mul_u64_u32_shr() and switched x86 to use it. This is, in principle, better; by optimizing the 64x64->64 multiplies to be 32x32->64 multiplies we can potentially save some time. However, the compiler piplines the 64x64->64 multiplies pretty well, and the conditional branch in the generic mul_u64_u32_shr() causes some bubbles in execution, with the result that it's pretty much a wash. If tilegx provided its own implementation of mul_u64_u32_shr() without the conditional branch, we could potentially save 3 cycles, but that seems like small gain for a fair amount of additional build scaffolding; no other platform currently provides a mul_u64_u32_shr() override, and tile doesn't currently have an <asm/div64.h> header to put the override in. Additionally, gcc currently has an optimization bug that prevents it from recognizing the opportunity to use a 32x32->64 multiply, and so the result would be no better than the existing mult_frac() until such time as the compiler is fixed. For now, just using mult_frac() seems like the right answer. Cc: stable@kernel.org [v3.4+] Signed-off-by: Chris Metcalf <cmetcalf@mellanox.com>
2016-11-23Merge tip:ras/core to pick up dependent changesBorislav Petkov
tip:ras/core contains the respective Fam17h x86 RAS bits which amd64_edac is going to use. So merge it into the EDAC branch. Signed-off-by: Borislav Petkov <bp@suse.de>
2016-11-23drm/amdgpu: drop is_display_hung from display funcsAlex Deucher
Not used. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-11-23drm/amdgpu/uvd: reduce IB parsing overhead on UVD5+ (v2)Alex Deucher
UVD 5 and newer do not have the same placement limitations as older chips, so skip the first pass since it's just overhead on chips where we don't have to force placement. v2: fix inverted logic Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-11-23drm/amdgpu/uvd: consolidate code for fetching addr from ctxAlex Deucher
Same code duplicated in both functions. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-11-23drm/amdgpu: Disable DPM in virtualizationTrigger Huang
This patch is used for virtualization support. In virtualization, only SMU manager is needed, DPM should be disabled. This is a use case for commit 2f9346b6f984 ("drm/amdgpu/powerplay: pp module only enable smu when dpm disabled.") Signed-off-by: Trigger Huang <trigger.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-11-23drm/amdgpu: use AMDGPU_GEM_CREATE_VRAM_CLEARED for VM PD/PTs (v2)Christian König
Doesn't make much sense to have the same functionality twice. v2: rebase on dma_fence renaming Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-11-23drm/amdgpu: improve AMDGPU_GEM_CREATE_VRAM_CLEARED handling (v2)Christian König
Drop this whole reserve/unreserve dance, just lock the reservation object manually when creating the BO. v2: rebase on dma_fence renaming Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-11-23drm/amdgpu: fix error handling in amdgpu_bo_create_restrictedChristian König
Manually checking why a function could fail is not a good idea if you can just check the functions return code. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-11-23drm/amdgpu: fix amdgpu_fill_buffer (v2)Christian König
The mem start is relative to the domain in the address space, so this worked only when VRAM was mapped at offset 0. It also didn't handled multiple drm_mm_nodes for split VRAM. v2: rebase on dma_fence renaming Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-11-23drm/amdgpu: remove amdgpu_irq_get_delayedChristian König
Not used any more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-11-23amdgpu: Wrap dev_err() calls on vm faults with printk_ratelimit()Edward O'Callaghan
It can be the case that upon GPU page faults we start trashing the logs, and so let us ratelimit here to avoid that. V2. Fix issue where calling dev_err_ratelimited separately for each line means that some lines corresponding to a single VM fault may or may not appear depending on the rate. - Michel Dänzer. Reviewed-by: Christian König <christian.koenig@amd.com> (v1) Signed-off-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-11-23amdgpu: Use dev_err() over vanilla printk() in vm_decode_fault()Edward O'Callaghan
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-11-23drm/amd/amdgpu: port of DCE v6 to new headers (v3)Tom St Denis
Port of SI DCE v6 over to new AMDGPU headers. Tested on a Tahiti with GNOME through various hot plugs/rotations/sizes/fullscreen/windowed and staging drm/xf86-video-amdgpu. (v2) Re-factored to remove formatting changes to si_enums.h as well rename various defines. (v3) Rebase on upstream Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-11-23drm/amdgpu: cleanup unused iterator members for sdma v2.4Huang Rui
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-11-23drm/amdgpu: cleanup unused iterator members for sdma v3Huang Rui
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-11-23drm/amdgpu:impl vgt_flush for VI(V5)Monk Liu
when shadowing enabled, tesselation app will trigger vm fault because below three tesselation registers: VGT_TF_RING_SIZE__CI__VI, VGT_HS_OFFCHIP_PARAM__CI__VI, VGT_TF_MEMORY_BASE__CI__VI, need to be programed after vgt-flush. Tesselation picture vm fault disappeared after vgt-flush introduced. v2:implement vgt-flush for CI & SI. v3:move vgt flush inside of cntx_cntrl v4:count vgt flush in frame_size v5:squash in typo fix Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-11-23drm/amdgpu: enable uvd mgcg for Fiji.Rex Zhu
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-11-23drm/amdgpu: refine cz uvd clock gate logic.Rex Zhu
sw clockgate was used on uvd6.0. when uvd is idle, we gate the uvd clock. when decode, we ungate the uvd clock. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-11-23ath10k: fix monitor vdev for receiving other bss framesManoharan, Rajkumar
In order to receive other BSS entries in mesh mode, Monitor vdev is created whenever filter flag is set with OTHER_BSS. Recently it is root caused that setting promisc filter for Mesh interface is causing performance and stability issues. To fix this issue, firmware will configure appropriate rxfilters by default for mesh vdev during vdev creation. This change fixes monitor vdev creation based on firmware IE Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-11-23ath10k: add support for per sta tx bitrateAnilkumar Kolli
Per STA tx bitrate info is filled from peer stats. Export per sta txrate info to cfg80211/nl80211 Signed-off-by: Anilkumar Kolli <akolli@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-11-23ath10k: add per peer htt tx stats support for 10.4Anilkumar Kolli
Per peer tx stats are part of 'HTT_10_4_T2H_MSG_TYPE_PEER_STATS' event, Firmware sends one HTT event for every four PPDUs. HTT payload has success pkts/bytes, failed pkts/bytes, retry pkts/bytes and rate info per ppdu. Peer stats are enabled through 'WMI_SERVICE_PEER_STATS', which are nowadays enabled by default. Parse peer stats and update the tx rate information per STA. tx rate, Peer stats are tested on QCA4019 with Firmware version 10.4-3.2.1-00028. Signed-off-by: Anilkumar Kolli <akolli@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-11-23clk: bcm2835: Fix ->fixed_divider of pllh_auxBoris Brezillon
There is no fixed divider on pllh_aux. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Eric Anholt <eric@anholt.net> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-23clk: qcom: clk-rpm: Fix clk_hw referencesGeorgi Djakov
Fix the clk_hw references to the actual clocks and add a xlate function to return the hw pointers from the already existing static array. Reported-by: Michael Scott <michael.scott@linaro.org> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-23clk: qcom: clk-smd-rpm: Fix clk_hw referencesGeorgi Djakov
Fix the clk_hw references to the actual clocks and add a xlate function to return the hw pointers from the already existing static array. Reported-by: Michael Scott <michael.scott@linaro.org> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-23clk: qcom: Move all sdcc rcgs to use clk_rcg2_floor_opsRajendra Nayak
The sdcc driver for msm8996/msm8916/msm8974/msm8994 and apq8084 expects a clk_set_rate() on the sdcc rcg clk to set a floor value of supported clk rate closest to the requested rate, by looking up the frequency table. So move all the sdcc rcgs on all these platforms to use the newly introduced clk_rcg2_floor_ops Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-23clk: qcom: Add rcg ops to return floor value closest to the requested rateRajendra Nayak
The default behaviour with clk_rcg2_ops is for the clk_round_rate()/clk_set_rate() to return/set a ceil clock rate closest to the requested rate by looking up the corresponding frequency table. However, we do have some instances (mainly sdcc on various platforms) of clients expecting a clk_set_rate() to set a floor value instead. Add a new clk_rcg2_floor_ops to handle this for such specific rcg instances Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-23drm/radeon: fix power state when port pm is unavailable (v2)Peter Wu
When PCIe port PM is not enabled (system BIOS is pre-2015 or the pcie_port_pm=off parameter is set), legacy ATPX PM should still be marked as supported. Otherwise the GPU can fail to power on after runtime suspend. This affected a Dell Inspiron 5548. Ideally the BIOS date in the PCI core is lowered to 2013 (the first year where hybrid graphics platforms using power resources was introduced), but that seems more risky at this point and would not solve the pcie_port_pm=off issue. v2: agd: fix typo Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98505 Signed-off-by: Peter Wu <peter@lekensteyn.nl> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: <stable@vger.kernel.org> # 4.8+ Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2016-11-23drm/amdgpu: fix power state when port pm is unavailablePeter Wu
When PCIe port PM is not enabled (system BIOS is pre-2015 or the pcie_port_pm=off parameter is set), legacy ATPX PM should still be marked as supported. Otherwise the GPU can fail to power on after runtime suspend. This affected a Dell Inspiron 5548. Ideally the BIOS date in the PCI core is lowered to 2013 (the first year where hybrid graphics platforms using power resources was introduced), but that seems more risky at this point and would not solve the pcie_port_pm=off issue. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98505 Reported-and-tested-by: Nayan Deshmukh <nayan26deshmukh@gmail.com> Signed-off-by: Peter Wu <peter@lekensteyn.nl> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: <stable@vger.kernel.org> # 4.8+ Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2016-11-23arm64: Remove I-cache invalidation from flush_cache_range()Catalin Marinas
The flush_cache_range() function (similarly for flush_cache_page()) is called when the kernel is changing an existing VA->PA mapping range to either a new PA or to different attributes. Since ARMv8 has PIPT-like D-caches, this function does not need to perform any D-cache maintenance. The I-cache maintenance is already handled via set_pte_at() and flush_cache_range() cannot anyway guarantee that there are no cache lines left after invalidation due to the speculative loads. This patch makes flush_cache_range() a no-op. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-11-23arm64: Enable HIBERNATION in defconfigCatalin Marinas
This patch adds CONFIG_HIBERNATION to the arm64 defconfig. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-11-23EDAC, amd64: Don't force-enable ECC checking on newer systemsYazen Ghannam
It's not recommended for the OS to try and force-enable ECC checking. This is considered a firmware task since it includes memory training, etc, so don't change ECC settings on Fam17h or newer systems and inform the user. Signed-off-by: Yazen Ghannam <Yazen.Ghannam@amd.com> Cc: Aravind Gopalakrishnan <aravindksg.lkml@gmail.com> Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/1479850816-1595-1-git-send-email-Yazen.Ghannam@amd.com [ Put the "forcing" message in an else branch. ] Signed-off-by: Borislav Petkov <bp@suse.de>
2016-11-23HID: hid-sensor-hub: clear memory to avoid random dataSong Hongyan
When user tried to read some fields like hysteresis from IIO sysfs on some systems, it fails. The reason is that this field is a byte field and caller of sensor_hub_get_feature() passes a buffer of 4 bytes. Here the function sensor_hub_get_feature() copies the single byte from the report to the caller buffer and returns "1" as the number of bytes copied. So caller can use the return value. But this is done by multiple callers, so if we just change the sensor_hub_get_feature so that caller buffer is initialized with 0s then we don't to change all functions. Signed-off-by: Song Hongyan <hongyan.song@intel.com> Acked-by: Jonathan Cameron <jic23@kernel.org> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2016-11-23HID: rmi: make transfer buffers DMA capableBenjamin Tissoires
Kernel v4.9 strictly enforces DMA capable buffers, so we need to remove buffers allocated on the stack. Signed-off-by: Benjamin Tissoires <benjamin.tissoires@redhat.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2016-11-23HID: magicmouse: make transfer buffers DMA capableBenjamin Tissoires
Kernel v4.9 strictly enforces DMA capable buffers, so we need to remove buffers allocated on the stack. Signed-off-by: Benjamin Tissoires <benjamin.tissoires@redhat.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2016-11-23spi: ath79: Fix module autoload for OF registrationJavier Martinez Canillas
If the driver is built as a module, autoload won't work because the module alias information is not filled. So user-space can't match the registered device with the corresponding module. Export the module alias information using the MODULE_DEVICE_TABLE() macro. Before this patch: $ modinfo drivers/spi/spi-ath79.ko | grep alias alias: platform:ath79-spi After this patch: $ modinfo drivers/spi/spi-ath79.ko | grep alias alias: platform:ath79-spi alias: of:N*T*Cqca,ar7100-spiC* alias: of:N*T*Cqca,ar7100-spi Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-23HID: lg: make transfer buffers DMA capableBenjamin Tissoires
Kernel v4.9 strictly enforces DMA capable buffers, so we need to remove buffers allocated on the stack. [jkosina@suse.cz: fix up second usage of hid_hw_raw_request(), spotted by 0day build bot] Signed-off-by: Benjamin Tissoires <benjamin.tissoires@redhat.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2016-11-23spi: xlp: Fix module autoload for OF registrationJavier Martinez Canillas
If the driver is built as a module, autoload won't work because the module alias information is not filled. So user-space can't match the registered device with the corresponding module. Export the module alias information using the MODULE_DEVICE_TABLE() macro. Before this patch: $ modinfo drivers/spi/spi-xlp.ko | grep alias alias: acpi*:BRCM900D:* After this patch: $ modinfo drivers/spi/spi-xlp.ko | grep alias alias: acpi*:BRCM900D:* alias: of:N*T*Cnetlogic,xlp832-spiC* alias: of:N*T*Cnetlogic,xlp832-spi Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-23spi: jcore: Fix module autoload for OF registrationJavier Martinez Canillas
If the driver is built as a module, autoload won't work because the module alias information is not filled. So user-space can't match the registered device with the corresponding module. Export the module alias information using the MODULE_DEVICE_TABLE() macro. Before this patch: $ modinfo drivers/spi/spi-jcore.ko | grep alias alias: platform:jcore_spi After this patch: $ modinfo drivers/spi/spi-jcore.ko | grep alias alias: platform:jcore_spi alias: of:N*T*Cjcore,spi2C* alias: of:N*T*Cjcore,spi2 Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-23spi: spi-axi: Fix module autoloadJavier Martinez Canillas
If the driver is built as a module, autoload won't work because the module alias information is not filled. So user-space can't match the registered device with the corresponding module. Export the module alias information using the MODULE_DEVICE_TABLE() macro. Before this patch: $ modinfo drivers/spi/spi-axi-spi-engine.ko | grep alias $ After this patch: $ modinfo drivers/spi/spi-axi-spi-engine.ko | grep alias alias: of:N*T*Cadi,axi-spi-engine-1.00.aC* alias: of:N*T*Cadi,axi-spi-engine-1.00.a Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-11-23HID: cp2112: make transfer buffers DMA capableBenjamin Tissoires
Kernel v4.9 strictly enforces DMA capable buffers, so we need to remove buffers allocated on the stack. Use a spinlock to prevent concurrent accesses to the buffer. Signed-off-by: Benjamin Tissoires <benjamin.tissoires@redhat.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2016-11-23regulator: max77620: add documentation for MPOK propertyVenkat Reddy Talla
Adding documentation for maxim,power-ok-control dts property Signed-off-by: Venkat Reddy Talla <vreddytalla@nvidia.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
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