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2021-12-16arm64: dts: ls1028a: add ftm_alarm1 node to be used as wakeup sourceBiwen Li
Add flextimer2 based ftm_alarm1 node and enable it to be the default rtc wakeup source for rdb and qds boards instead of the original flextimer1 which is used by PWM. The ftm_alarm0 node hence is disabled by default. Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-16arm64: dts: ls1028a: Add PCIe EP nodesXiaowei Bao
Add PCIe EP nodes for ls1028a to support EP mode. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-16arm64: dts: lx2162a-qds: add interrupt line for RTC nodeBiwen Li
Add interrupt line for RTC node on lx2162a-qds Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-16arm64: dts: lx2162a-qds: support SD UHS-I and eMMC HS400 modesYangbo Lu
The default NXP SDHC adapter cards for LX2162AQDS are SD 2.0/3.0 adapter card for eSDHC1, and eMMC 5.1 adapter card for eSDHC2. Add speed modes properties supported by the two adapters in device tree node. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-16arm64: dts: lx2160a: enable usb3-lpm-capable for usb3 nodesRan Wang
Enable USB3 HW LPM feature for lx2160a. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-16arm64: dts: lx2160a-qds: Add mdio mux nodesPankaj Bansal
The two external MDIO buses used to communicate with phy devices that are external to SOC are muxed in LX2160AQDS board. These buses can be routed to any one of the eight IO slots on LX2160AQDS board depending on value in fpga register 0x54. Additionally the external MDIO1 is used to communicate to the onboard RGMII phy devices. The mdio1 is controlled by bits 4-7 of fpga register and mdio2 is controlled by bits 4-7 of fpga register. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-16arm64: dts: lx2160a: add optee-tz nodePankaj Gupta
Disabled by default in SoC dtsi and enables in board dts files. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-16arm64: dts: lx2160a-rdb: Add Inphi PHY nodeIoana Radulescu
DPMAC5 and DPMAC6 are connected to 25G Inphi PHY Signed-off-by: Vicentiu Galanopulo <vicentiu.galanopulo@nxp.com> Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-16arm64: dts: imx8mm: don't assign PLL2 in SoC dtsiLucas Stach
The base i.MX8MM dtsi changes the audio PLL2 rate, which gets in the way if it should be used for anything else than audio. As this PLL doesn't seem to be used by any upstream supported board, just remove the rate configuration to allow boards to set it up as they wish. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-16arm64: dts: nitrogen8-som: correct i2c1 pad-ctrlLucas Stach
The slew rate and drive-strength of the i2c1 pads were much too high. Bring them down to avoid signal quality issues. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-16arm64: dts: nitrogen8-som: correct network PHY resetLucas Stach
Add the missing reset-gpios property to allow Linux to fully reset the network PHY and fix the pinmux to add the neccessary pull-ups for the PHY strap configuration. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-14arm64: dts: imx8mn-bsh-smm-s2/pro: Add iMX8MN BSH SMM S2 boardsAriel D'Alessandro
Introduce BSH SystemMaster (SMM) S2 board family, which consists of: iMX8MN SMM S2 and iMX8MN SMM S2 PRO boards. Add support for iMX8MN BSH SMM S2 board: - 256 MiB DDR3 RAM - 512 MiB NAND - Megabit Ethernet PHY - Wi-Fi 802.11 a/b/g/n/ac with Bluetooth 5.0 - USB-OTG (peripheral mode) Add support for iMX8MN BSH SMM S2 PRO board: - 512 MiB DDR3 RAM - 8 GiB eMMC - Megabit Ethernet PHY - Wi-Fi 802.11 a/b/g/n/ac with Bluetooth 5.0 - USB-OTG (peripheral mode) Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-14arm64: dts: imx8mm/n: Remove the 'pm-ignore-notify' propertyFabio Estevam
The 'pm-ignore-notify' property is not a valid property and there is no documentation for it. Drop such invalid property. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-14arm64: dts: imx8ulp: add power domain entry for usdhcPeng Fan
Add power domain for USDHC node. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-14arm64: dts: imx8ulp: add scmi firmware nodePeng Fan
i.MX8ULP use scmi firmware based power domain and sensor support. So add the firmware node and the sram it uses. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-14dt-bindings: power: imx8ulp: add power domain header filePeng Fan
Add i.MX8ULP power domain header file Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-14arm64: dts: imx8mq-evk: link regulator to VPU domainAdam Ford
The SW1C regulator powers the VPU and the state isn't guaranteed to always be on. Link the VPU power-domain to the regulator to ensure it is turned on before using the power domain. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-14arm64: dts: ls1088a: add snps incr burst type adjustment for usb1Li Yang
This property could fix the defect that external usb device always prints this error log --- 'reset SuperSpeed USB device number n using xhci_hcd' when system power on. Signed-off-by: Pengbo Mu <pengbo.mu@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-14arm64: dts: ls1088a: Add reboot nodesLi Yang
ls1088a has a separate reset register block. Define it in dts and use it for reboot. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-14arm64: dts: ls1028a-rdb: update copyrightVladimir Oltean
Company policy requires that copyright is updated when a file is touched. Keeping the copyright change separate to reduce the noise in other patches. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-14arm64: dts: ls1028a-rdb: add aliases for the Ethernet portsVladimir Oltean
These are used by U-Boot, and are required for keeping the device trees in sync. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-14arm64: dts: ls1028a-rdb: add an alias for the FlexSPI controllerVladimir Oltean
This is used by U-Boot and is required for keeping the device trees in sync. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-14arm64: dts: ls1028a-rdb: sort nodes alphabetically by labelVladimir Oltean
In preparation for this board's device tree synchronization with U-Boot, we must find a common node ordering pattern. Alphabetical sounds about right. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-08arm64: dts: imx8mp: add mac address for EQOSJoakim Zhang
Add mac address in efuse, so that EQOS driver can parse it from nvmem cell. Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-08arm64: dts: imx8m: remove unused "nvmem_macaddr_swap" property for FECJoakim Zhang
Remove unused "nvmem_macaddr_swap" property for FEC, there is no info in both dt-binding and driver, so it's safe to remove it. Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-08arm64: dts: imx8mp-evk: disable CLKOUT clock for ENET PHYJoakim Zhang
According to commit 0a4355c2b7f8 ("net: phy: realtek: add dt property to disable CLKOUT clock"), diable CLKOUT clock for FEC PHY to save power on i.MX8MP EVK board. Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-08arm64: dts: imx8m: configure FEC PHY VDDIO voltageJoakim Zhang
As commit 2f664823a470 ("net: phy: at803x: add device tree binding") described, configure FEC PHY VDDIO voltage according to board design. Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-08arm64: dts: imx8m: disable smart eee for FEC PHYJoakim Zhang
As commit 390b4cad8148 ("net: phy: at803x: add support for configuring SmartEEE") described, disable PHY smart eee by default. Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-08arm64: dts: imx8mp-evk: add hardware reset for EQOS PHYJoakim Zhang
As commit 798a1807ab13 ("arm64: dts: imx8mp-evk: Improve the Ethernet PHY description") described, add hardware reset for EQOS PHY. Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-08arm64: dts: imx8mn-evk: add hardware reset for FEC PHYJoakim Zhang
Add hardware reset for FEC PHY. Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-06arm64: dts: freescale: add initial device tree for TQMa8Mx with i.MX8MAlexander Stein
This adds support for TQMa8Mx module on MBa8Mx board. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-06arm64: dts: freescale: add initial device tree for TQMa8MQNL with i.MX8MNAlexander Stein
This adds support for TQMa8MQNL module on MBa8Mx board. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-06arm64: dts: freescale: add initial device tree for TQMa8MQML with i.MX8MMAlexander Stein
This adds support for TQMa8MQML module on MBa8Mx board. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-06arm64: dts: imx8ulp: Add the basic dts for imx8ulp evk boardJacky Bai
Add the basic dts file for i.MX8ULP EVK board. Only the necessary devices for minimal system boot up are enabled: enet, emmc, usb, console uart. some of the devices' pin status may lost during low power mode, so additional sleep pinctrl properties are included by default. Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-06arm64: dts: imx8ulp: Add the basic dtsi file for imx8ulpJacky Bai
Add the basic dtsi support for i.MX8ULP. i.MX 8ULP is part of the ULP family with emphasis on extreme low-power techniques using the 28 nm fully depleted silicon on insulator process. Like i.MX 7ULP, i.MX 8ULP continues to be based on asymmetric architecture, however will add a third DSP domain for advanced voice/audio capability and a Graphics domain where it is possible to access graphics resources from the application side or the realtime side. Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-06arm64: dts: imx8mm-beacon: Enable OV5640 CameraAdam Ford
The baseboard has support for a TDNext 5640 Camera which uses an OV5640 connected to a 2-lane CSI2 interface. With the CSI and mipi_csi2 drivers pointing to an OV5640 camera, the media pipeline can be configured with the following: media-ctl --links "'ov5640 1-003c':0->'imx7-mipi-csis.0':0[1]" The camera and various nodes in the pipeline can be configured for UYVY: media-ctl -v -V "'ov5640 1-003c':0 [fmt:UYVY8_1X16/640x480 field:none]" media-ctl -v -V "'csi':0 [fmt:UYVY8_1X16/640x480 field:none]" Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-06arm64: dts: imx8mm: Add CSI nodesAdam Ford
There is a csi bridge and csis interface that tie together to allow csi2 capture. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Tim Harvey <tharvey@gateworks.com> Tested-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-06arm64: dts: imx8mq: fix the schema check errors for fsl,tmu-calibrationDavid Heidelberg
fsl,tmu-calibration is in u32-matrix. Use matching property syntax. No functional changes. Fixes warnings as: $ make dtbs_check ... arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dt.yaml: tmu@30260000: \ fsl,tmu-calibration:0: Additional items are not allowed (1, 41, 2, 47, \ 3, 53, 4, 61, 5, 67, 6, 75, 7, 81, 8, 87, 9, 95, 10, 103, 11, 111, 65536, \ 27, 65537, 35, 65538, 43, 65539, 51, 65540, 59, 65541, 67, 65542, 75, \ 65543, 85, 65544, 93, 65545, 103, 65546, 112, 131072, 23, 131073, 35, \ 131074, 45, 131075, 55, 131076, 65, 131077, 75, 131078, 87, 131079, 99, \ 131080, 111, 196608, 21, 196609, 33, 196610, 45, 196611, 57, 196612, 69, \ 196613, 83, 196614, 95, 196615, 113 were unexpected) From schema: Documentation/devicetree/bindings/thermal/qoriq-thermal.yaml ... Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-06arm64: dts: lx2162a: Add CAN nodes for LX2162A-QDSKuldeep Singh
Enable CAN support for LX2162A-QDS in board dts. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-11-23arm64: dts: imx8qxp: add cache infoPeng Fan
i.MX8QXP A35 Cluster has 32KB Icache, 32KB Dcache and 512KB L2 Cache - Icache is 2-way set associative - Dcache is 4-way set associative - L2cache is 8-way set associative - Line size are 64bytes Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-11-23arm64: dts: imx8qm: add cache infoPeng Fan
i.MX8QM A53 Cluster has 32KB Icache, 32KB Dcache and 1MB L2 Cache - Icache is 2-way set associative - Dcache is 4-way set associative - L2cache is 16-way set associative - Line size are 64bytes A72 Cluster has 48KB Icache, 32KB Dcache and 1MB L2 Cache - ICache is 3-way set-associative - Dcache is 2-way set-associative - L2Cache is 16-way set-associative - Line size are 64bytes Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-11-23arm64: dts: imx8m: add cache infoPeng Fan
i.MX8M Family use A53 Cores and has 32KB ICache with 32KB DCache. - Icache is 2-way set associative - Dcache is 4-way set associative - L2cache is 16-way set associative - Line size are 64bytes Except i.MX8MQ has 1MB L2 Cache, others has 512KB L2 Cache. So add the cache info in device tree and let use could see that from /sys/devices/system/cpu/cpu[x]/cache/ Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-11-22arm64: dts: imx8mq-librem5-r3.dtsi: describe selfie cam XSHUTDOWN pinMartin Kepplinger
The r3 and later revisions of the Librem 5 phone include an additional switch to control the hi846 XSHUTDOWN pin. Describe it. Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-11-22arm64: dts: imx8mq-librem5: describe the selfie camMartin Kepplinger
Enable the CSI1 MIPI RX controller and CSI1 bridge on the SoC. Describe the Librem 5 front-facing camera, connected to the CSI1 MIPI. the following sets formats, streams 10 frames and saves one: #!/bin/bash WIDTH=1632 HEIGHT=1224 SKIP=10 media-ctl -d "platform:30a90000.csi" --set-v4l2 "'csi':0 [fmt:SGBRG10/${WIDTH}x${HEIGHT} colorspace:raw]" media-ctl -d "platform:30a90000.csi" --set-v4l2 "'imx8mq-mipi-csi2 30a70000.csi':0 [fmt:SGBRG10/${WIDTH}x${HEIGHT} colorspace:raw]" media-ctl -d "platform:30a90000.csi" --set-v4l2 "'hi846 2-0020':0 [fmt:SGBRG10/${WIDTH}x${HEIGHT} colorspace:raw]" media-ctl -d "platform:30a90000.csi" -l "'hi846 2-0020':0 -> 'imx8mq-mipi-csi2 30a70000.csi':0 [1]" v4l2-ctl -d "/dev/v4l/by-path/platform-30a90000.csi-video-index0" --set-fmt-video=width=${WIDTH},height=${HEIGHT},pixelformat=GB16 --stream-mmap --stream-to=$WIDTH.raw --stream-skip=$SKIP --stream-count=1 Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-11-22arm64: dts: imx8mq-librem5: describe power supply for camerasMartin Kepplinger
CAMERA_PWR_EN controls two different power supplies that cameras will use. The hardware killswitch controls a third one. Describe that appropriately. The pinctrl that describes the gpio that is used in 2 places here is added to the pmic. This is done because pmic is powered early enough to make sure this will work. When we would have put the same pinctrl property into the 2 regulator nodes (instead of the pmic), we'd get: imx8mq-pinctrl 30330000.pinctrl: pin MX8MQ_IOMUXC_GPIO1_IO00 already requested by regulator-csi-1v8; cannot claim for regulator-vcam-2v8 imx8mq-pinctrl 30330000.pinctrl: pin-10 (regulator-vcam-2v8) status -22 imx8mq-pinctrl 30330000.pinctrl: could not request pin 10 (MX8MQ_IOMUXC_GPIO1_IO00) from group camerapwrgrp on device 30330000.pinctrl Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-11-22arm64: dts: split out a shared imx8mq-librem5-r3.dtsi descriptionMartin Kepplinger
The Librem 5 r3 ("Dogwood") and r4 ("Evergreen") revisions are quite similar. Add a shared imx8mq-librem5-r3.dtsi description to be included in r3 and later dts files in order to avoid duplication. This is no change in the descriptions but only refactoring. Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-11-22arm64: dts: imx8mm-beacon: Enable USB ControllersAdam Ford
The i.MX8M Mini has two available USB controllers. On the imx8mm-beacon board, USB1 is routed to a mini-USB port with OTG functionality. USB2 is routed to a USB hub which has three host-only ports connected to it. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-11-21arm64: dts: fsl-ls1043a-rdb: add delay between CS and CLK signal for flash ↵Meng Li
device Based on commit d59c90a2400f("spi: spi-fsl-dspi: Convert TCFQ users to XSPI FIFO mode ") and 6c1c26ecd9a3("spi: spi-fsl-dspi: Accelerate transfers using larger word size if possible"), on ls1043a-rdb platform, the spi work mode is changed from TCFQ mode to XSPI mode. In order to keep the transmission sequence matches with flash device, it is need to add delay between CS and CLK signal. The strategy of generating delay value refers to QorIQ LS1043A Reference Manual. Signed-off-by: Meng Li <Meng.Li@windriver.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-11-21arm64: dts: imx: imx8mn-beacon: Drop undocumented clock-names referenceGeert Uytterhoeven
The wlf,wm8962 Device Tree bindings do not specify a clock-names property. Drop it. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-11-21arm64: dts: freescale: add 'chassis-type' propertyArnaud Ferraris
A new 'chassis-type' root node property has recently been approved for the device-tree specification, in order to provide a simple way for userspace to detect the device form factor and adjust their behavior accordingly. This patch fills in this property for end-user devices (such as laptops, smartphones and tablets) based on NXP ARM64 processors. Signed-off-by: Arnaud Ferraris <arnaud.ferraris@collabora.com> Reviewed-by: Guido Günther <agx@sigxcpu.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
generated by cgit (git 2.34.1) at 2025-09-09 01:57:48 +0000