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2025-01-02ARM: dts: microchip: sam9x7: Add address/size to spi-controller nodesMihai Sain
Since these properties are common for all spi subnodes, add them to SoC dtsi instead of board dts. Signed-off-by: Mihai Sain <mihai.sain@microchip.com> Link: https://lore.kernel.org/r/20241218080333.2225-3-mihai.sain@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-01-02ARM: dts: microchip: sam9x60: Add address/size to spi-controller nodesMihai Sain
Since these properties are common for all spi subnodes, add them to SoC dtsi instead of board dts. Signed-off-by: Mihai Sain <mihai.sain@microchip.com> Link: https://lore.kernel.org/r/20241218080333.2225-2-mihai.sain@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-01-02ARM: dts: microchip: sama5d27_wlsom1_ek: Add no-1-8-v property to sdmmc0 nodeCristian Birsan
Add no-1-8-v property to sdmmc0 node to keep VDDSDMMC power rail at 3.3V. This property will stop the LDO regulator from switching to 1.8V when the MMC core detects an UHS SD Card. VDDSDMMC power rail is used by all the SDMMC interface pins in GPIO mode (PA0 - PA13). On this board, PA10 is used as GPIO to enable the power switch controlling USB Vbus for the USB Host. The change is needed to fix the PA10 voltage level to 3.3V instead of 1.8V. Fixes: 5d4c3cfb63fe ("ARM: dts: at91: sama5d27_wlsom1: add SAMA5D27 wlsom1 and wlsom1-ek") Suggested-by: Mihai Sain <mihai.sain@microchip.com> Signed-off-by: Cristian Birsan <cristian.birsan@microchip.com> Tested-by: Andrei Simion <andrei.simion@microchip.com> Link: https://lore.kernel.org/r/20241119160107.598411-3-cristian.birsan@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-01-02ARM: dts: microchip: sama5d29_curiosity: Add no-1-8-v property to sdmmc0 nodeCristian Birsan
Add no-1-8-v property to sdmmc0 node to keep VDDSDMMC power rail at 3.3V. This property will stop the LDO regulator from switching to 1.8V when the MMC core detects an UHS SD Card. VDDSDMMC power rail is used by all the SDMMC interface pins in GPIO mode (PA0 - PA13). On this board, PA6 is used as GPIO to enable the power switch controlling USB Vbus for the USB Host. The change is needed to fix the PA6 voltage level to 3.3V instead of 1.8V. Fixes: d85c4229e925 ("ARM: dts: at91: sama5d29_curiosity: Add device tree for sama5d29_curiosity board") Suggested-by: Mihai Sain <mihai.sain@microchip.com> Signed-off-by: Cristian Birsan <cristian.birsan@microchip.com> Tested-by: Andrei Simion <andrei.simion@microchip.com> Link: https://lore.kernel.org/r/20241119160107.598411-2-cristian.birsan@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-01-02ARM: dts: at91: Add sama7d65 pinmuxRyan Wanner
Add sama7d65 pin descriptions. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/a8f880b89cd4470526a2955a0b6aaaaa24ba65b8.1733505542.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2024-12-30ARM: dts: amlogic: meson: remove size and address cells from USB nodesMartin Blumenstingl
The only board that actually requires these properties is meson8b-odroidc1.dts but that already sets it on it's own. Drop these properties from meson.dtsi because otherwise they can cause dtc warnings: /soc/usb@c9040000: unnecessary #address-cells/#size-cells without "ranges", "dma-ranges" or child "reg" property Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241226220352.965505-1-martin.blumenstingl@googlemail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2024-12-30arm64: dts: freescale: imx93-9x9-qsb: enable fsl,ext-reset-output for wdog3Peng Fan
The WDOG_B is connected to external PMIC, so set "fsl,ext-reset-output" to enable triggering PMIC reset. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30arm64: dts: freescale: imx93-14x14-evk: enable fsl,ext-reset-output for wdog3Peng Fan
The WDOG_B is connected to external PMIC, so set "fsl,ext-reset-output" to enable triggering PMIC reset. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30arm64: dts: freescale: imx93-11x11-evk: enable fsl,ext-reset-output for wdog3Peng Fan
The WDOG_B is connected to external PMIC, so set "fsl,ext-reset-output" to enable triggering PMIC reset. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30arm64: dts: imx95-19x19-evk: add ENETC 0 supportWei Fang
Add ENETC 0 (1G ethernet port) support for i.MX95-19x19-EVK board. In addition, because all ENETC instances share MDIO bus, so enable EMDIO at the same time. Signed-off-by: Wei Fang <wei.fang@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30arm64: dts: imx95: add NETC related nodesWei Fang
Add NETC related nodes for i.MX95. Signed-off-by: Wei Fang <wei.fang@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30ARM: dts: imx: Use the correct mdio patternFabio Estevam
mdio-gpio is not a valid pattern according to mdio-gpio.yaml. Use the generic 'mdio' name to fix the following dt-schema warnings: 'mdio-gpio' does not match '^mdio(-(bus|external))?(@.+|-([0-9]+))?$' Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30ARM: dts: imx6qdl-sabresd: add dr_mode to usbotgHui Wang
Currently there are 3 type of boards (imx6q|imx6qp|imx6dl-sabresd) based on imx6qdl-sabresd.dtsi, they all do not set the dr_mode for usbotg device node. The chipidea usb driver will configure it to otg mode by default if the dr_mode is not set, but some testcases need to parse the dr_mode from DT and decide the follow-up test strategy, here set the dr_mode to otg explicitly for these 3 imx6qdl-sabresd based boards. Signed-off-by: Hui Wang <hui.wang@canonical.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30arm64: dts: imx8mm-phg: Add LVDS compatible stringFabio Estevam
The imx8mm-phg board has an AUO G084SN05 V9 8.4" 800x600 LVDS panel. Improve the devicetree description by passing the LVDS compatible string to fix the following dt-schema warning: imx8mm-phg.dtb: panel: compatible:0: 'panel-lvds' is not one of ['admatec,9904379', 'auo,b101ew05', 'auo,g084sn05', 'chunghwa,claa070wp03xg','edt,etml0700z9ndha', 'hannstar,hsd101pww2', 'hydis,hv070wx2-1e0', 'jenson,bl-jt60050-01a', 'tbs,a711-panel'] ... Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30arm64: dts: exynos8895: Add camera hsi2c nodesIvaylo Ivanov
Add nodes for hsi2c1-4 (CAM0-3), which allows using them. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Link: https://lore.kernel.org/r/20241221152803.1663820-1-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-30arm64: dts: exynos990: Add clock management unit nodesIgor Belwon
Add CMU nodes for: - cmu_top: provides clocks for other blocks - cmu_hsi0: provides clocks for usb31 Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Link: https://lore.kernel.org/r/20241224-cmu-v3-1-33ca24b2413c@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-30Merge branch 'for-v6.14/dt-bindings-clk-samsung' into next/dt64Krzysztof Kozlowski
2024-12-30arm64: dts: imx93: add pca9452 supportJoy Zou
Support pca9452 on imx93-14x14-evk. Signed-off-by: Joy Zou <joy.zou@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30arm64: dts: imx8mn-bsh-smm-s2/pro: add simple-framebufferDario Binacchi
Add a simple-framebuffer node for U-Boot to further fill and activate. Co-developed-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30arm64: dts: imx93-tqma9352-mba93xxla: enable Open Drain for MDIOMarkus Niebel
The board has a pull-up resistor for MDIO pin per PHY design guide. When MDIO is idle, it needs to be high and open drain is better to be used here for power saving. Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30arm64: dts: imx93-tqma9352-mba93xxca: enable Open Drain for MDIOMarkus Niebel
The board has a pull-up resistor for MDIO pin per PHY design guide. When MDIO is idle, it needs to be high and open drain is better to be used here for power saving. Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30ARM: dts: imx6qdl-apalis: Change to "adi,force-bt656-4"Fabio Estevam
According to adv7180.yaml, the correct property name is "adi,force-bt656-4". Update it accordingly to fix several dt-schema warnings: adv7280@21: 'adv,force-bt656-4' does not match any of the regexes: ... imx6qdl-apalis.dtsi is the only in-tree kernel user of this property. BSD does have a adv7180 driver, so should not be impacted. Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30ARM: dts: imx6sx: add phy-3p0-supply to usb physStefan Kerkmann
The integrated usb phys are supplied by the 3p0 regulator, which has a voltage range of 2.625V to 3.4V. Thus the min and max values are corrected and the regulator added as a proper supply for the usb phys. This fixes the following warnings during the probe of the mxs_phy driver: mxs_phy 20c9000.usbphy: supply phy-3p0 not found, using dummy regulator mxs_phy 20ca000.usbphy: supply phy-3p0 not found, using dummy regulator The regulator handling was introduced by commit `966d73152078 (usb: phy: mxs: enable regulator phy-3p0 to improve signal qualilty, 2024-07-26)`. Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30ARM: dts: imx6sl: add phy-3p0-supply to usb physStefan Kerkmann
The integrated usb phys are supplied by the 3p0 regulator, which has a voltage range of 2.625V to 3.4V. Thus the min and max values are corrected and the regulator added as a proper supply for the usb phys. This fixes the following warnings during the probe of the mxs_phy driver: mxs_phy 20c9000.usbphy: supply phy-3p0 not found, using dummy regulator mxs_phy 20ca000.usbphy: supply phy-3p0 not found, using dummy regulator The 3p0 regulator handling was introduced by commit 966d73152078 ("usb: phy: mxs: enable regulator phy-3p0 to improve signal qualilty")`. Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-30ARM: dts: imx6qdl: add phy-3p0-supply to usb physStefan Kerkmann
The integrated usb phys are supplied by the 3p0 regulator, which has a voltage range of 2.625V to 3.4V. Thus the min and max values are corrected and the regulator added as a proper supply for the usb phys. This fixes the following warnings during the probe of the mxs_phy driver: mxs_phy 20c9000.usbphy: supply phy-3p0 not found, using dummy regulator mxs_phy 20ca000.usbphy: supply phy-3p0 not found, using dummy regulator The 3p0 regulator handling was introduced by commit 966d73152078 ("usb: phy: mxs: enable regulator phy-3p0 to improve signal qualilty")`. Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-29ARM: dts: samsung: exynos4212-tab3: Drop interrupt from WM1811 codecArtur Weber
This was initially copied from the Midas DTSI, but there is no proof that the same interrupt is also used on the Tab 3. The pin listed as the interrupt here is GPIO_HDMI_CEC on the Midas, but for the Tab 3 it is the headset button GPIO - GPIO_EAR_SEND_END. Drop the interrupt, since there is no proof that it is used. Signed-off-by: Artur Weber <aweber.kernel@gmail.com> Link: https://lore.kernel.org/r/20240816-midas-audio-tab3-v2-5-48ee7f2293b3@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-29ARM: dts: samsung: exynos4212-tab3: Add MCLK2 clock to WM1811 codec configArtur Weber
In the schematics, the MCLK2 pin is shown as connected to CODEC_CLK32K, which is derived from the same 32KHZ_PMIC clock as Bluetooth/WiFi and GPS clocks. 32KHZ_PMIC is connected to the BTCLK pin, represented in mainline as S2MPS11_CLK_BT. Add the MCLK2 clock to the WM1811 codec clock property to properly describe the hardware. Signed-off-by: Artur Weber <aweber.kernel@gmail.com> Link: https://lore.kernel.org/r/20240816-midas-audio-tab3-v2-4-48ee7f2293b3@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-29ARM: dts: samsung: exynos4212-tab3: Fix headset mic, add jack detectionArtur Weber
Set up headset mic bias regulator and add the necessary properties to the samsung,midas-audio node to allow for headset jack detection. Signed-off-by: Artur Weber <aweber.kernel@gmail.com> Link: https://lore.kernel.org/r/20240816-midas-audio-tab3-v2-3-48ee7f2293b3@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-29ARM: dts: socfpga: remove non-existent DAC from CycloneV devkitConor Dooley
There is no Rohm DAC on the CycloneV devkit according to the online documentation for it that I could find, and it definitely does not have a dh2228fv as this device does not actually exist! Remove the DAC node from the devicetree as it is not acceptable to pretend to have a device on a board in order to bind the spidev driver in Linux. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240717-partake-antivirus-3347e415fb7d@spud Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-29arm64: dts: exynos: gs101-oriole: add pd-disable and typec-power-opmodeAndré Draszik
When the serial console is enabled, we need to disable power delivery since serial uses the SBU1/2 pins and appears to confuse the TCPCI, resulting in endless interrupts. For now, change the DT such that the serial console continues working. Note1: We can not have both typec-power-opmode and new-source-frs-typec-current active at the same time, as otherwise DT binding checks complain. Note2: When using a downstream DT, the Pixel boot-loader will modify the DT accordingly before boot, but for this upstream DT it doesn't know where to find the TCPCI node. The intention is for this commit to be reverted once an updated Pixel boot-loader becomes available. Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20241203-gs101-phy-lanes-orientation-dts-v2-5-1412783a6b01@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-29arm64: dts: exynos: gs101-oriole: enable Maxim max77759 TCPCiAndré Draszik
On Pixel 6 (and Pro), a max77759 companion PMIC for USB Type-C applications is used, which contains four functional blocks (at distinct I2C addresses): * top (including GPIO) * charger * fuel gauge * TCPCi While in the same package, TCPCi and Fuel Gauge have separate I2C addresses, interrupt lines and interrupt status registers and can be treated independently. The TCPCi is required to detect and handle connector orientation in Pixel's USB PHY driver, and to configure the USB controller's role (host vs device). This change adds the TCPCi part as it can be independent and doesn't need a top-level MFD. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20241203-gs101-phy-lanes-orientation-dts-v2-4-1412783a6b01@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-27arm64: dts: qcom: x1e80100: Fix interconnect tags for SDHC nodesAbel Vesa
The CPU-to-SDHC interconnect path for the SDHC_2 needs to have the active-only tags. The tags are missing entirely on for the SDHC_4 controller interconnect paths. Fix all tags for both controllers. Fixes: ffb21c1e19b1 ("arm64: dts: qcom: x1e80100: Describe the SDHC controllers") Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20241227-b4-x1e80100-qcp-sdhc-fixes-v1-1-cd971f7f0955@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: qrb4210-rb2: add HDMI audio playback supportAlexey Klimov
Add sound node and dsp-related piece to enable HDMI audio playback support on Qualcomm QRB4210 RB2 board. That is the only sound output supported for now. The audio playback is verified using the following commands: amixer -c0 cset iface=MIXER,name='SEC_MI2S_RX Audio Mixer MultiMedia1' 1 aplay -D hw:0,0 /usr/share/sounds/alsa/Front_Center.wav Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org> Link: https://lore.kernel.org/r/20241112025306.712122-5-alexey.klimov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm4250: add LPASS LPI pin controllerAlexey Klimov
Add the Low Power Audio SubSystem Low Power Island (LPASS LPI) pin controller device node required for audio subsystem on Qualcomm QRB4210 RB2. QRB4210 is based on sm4250 which has a slightly different lpass pin controller comparing to sm6115. While at this, also add description of lpi_i2s2 pins (active state) required for audio playback via HDMI. Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org> Link: https://lore.kernel.org/r/20241112025306.712122-4-alexey.klimov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm6115: add LPASS LPI pin controllerAlexey Klimov
Add the Low Power Audio SubSystem Low Power Island (LPASS LPI) pin controller device node required for audio subsystem on Qualcomm QRB4210 RB2. Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241112025306.712122-3-alexey.klimov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm6115: add apr and its servicesAlexey Klimov
Add apr (asynchronous packet router) node and its associated services required to enable audio on QRB4210 RB2 platform. Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org> Link: https://lore.kernel.org/r/20241112025306.712122-2-alexey.klimov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm8650: Fix CDSP context banks unit addressesKrzysztof Kozlowski
There is a mismatch between 'reg' property and unit address for last there CDSP compute context banks. Current values were taken as-is from downstream source. Considering that 'reg' is used by Linux driver as SID of context bank and that least significant bytes of IOMMU value match the 'reg', assume the unit-address is wrong and needs fixing. This also won't have any practical impact, except adhering to Devicetree spec. Fixes: dae8cdb0a9e1 ("arm64: dts: qcom: sm8650: Add three missing fastrpc-compute-cb nodes") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241104144204.114279-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26ARM: dts: qcom: sdx55: Add CPU PCIe EP interconnect pathKrishna chaitanya chundru
Add cpu-pcie interconnect path for PCIe EP to sdx55 platform. Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/1689751218-24492-4-git-send-email-quic_krichai@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26ARM: dts: qcom: sdx65: Add PCIe EP interconnect pathKrishna chaitanya chundru
Add pcie-mem & cpu-pcie interconnect path ifor PCIe EP to sdx65 platform. Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> Link: https://lore.kernel.org/r/1689751218-24492-3-git-send-email-quic_krichai@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: q[dr]u1000: move board clocks to qdu1000.dtsi fileDmitry Baryshkov
The QDU1000 and QRU1000 devices define XO and clocks completely in the board files, despite qdu1000.dtsi file referencing them directly. Follow the example of other platforms and move clock definitions to the qdu1000.dtsi file. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-21-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sdm670: move board clocks to sdm670.dtsi fileDmitry Baryshkov
The SDM670 devices define XO and clocks completely in the board files, despite sdm670.dtsi file referencing them directly. Follow the example of other platforms and move clock definitions to the sdm670.dtsi file. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-20-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sc8180x: drop extra XO clock frequenciesDmitry Baryshkov
sc8180x.dtsi already defines 38.4 MHz clock frequency for the XO clock. Drop duplicate overrides from Primus and Lenovo Flex 5G DT files. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-19-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: x1e80100: correct sleep clock frequencyDmitry Baryshkov
The X1E80100 platform uses PMK8550 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-18-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm8650: correct sleep clock frequencyDmitry Baryshkov
The SM8650 platform uses PMK8550 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 6fbdb3c1fac7 ("arm64: dts: qcom: sm8650: add initial SM8650 MTP dts") Fixes: a834911d50c1 ("arm64: dts: qcom: sm8650: add initial SM8650 QRD dts") Fixes: 01061441029e ("arm64: dts: qcom: sm8650: add support for the SM8650-HDK board") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-17-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm8550: correct sleep clock frequencyDmitry Baryshkov
The SM8550 platform uses PMK8550 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 0b12da4e28d8 ("arm64: dts: qcom: add base AIM300 dtsi") Fixes: b5e25ded2721 ("arm64: dts: qcom: sm8550: add support for the SM8550-HDK board") Fixes: 71342fb91eae ("arm64: dts: qcom: Add base SM8550 MTP dts") Fixes: d228efe88469 ("arm64: dts: qcom: sm8550-qrd: add QRD8550") Fixes: ba2c082a401f ("arm64: dts: qcom: sm8550: Add support for Samsung Galaxy Z Fold5") Fixes: 39c596304e44 ("arm64: dts: qcom: Add SM8550 Xperia 1 V") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-16-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm8450: correct sleep clock frequencyDmitry Baryshkov
The SM8450 platform uses PMK8350 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 5188049c9b36 ("arm64: dts: qcom: Add base SM8450 DTSI") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-15-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm8350: correct sleep clock frequencyDmitry Baryshkov
The SM8350 platform uses PMK8350 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: b7e8f433a673 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-14-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm8250: correct sleep clock frequencyDmitry Baryshkov
The SM8250 platform uses PM8150 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 9ff8b0591fcf ("arm64: dts: qcom: sm8250: use the right clock-freqency for sleep-clk") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-13-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm6375: correct sleep clock frequencyDmitry Baryshkov
The SM6375 platform uses PM6125 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 59d34ca97f91 ("arm64: dts: qcom: Add initial device tree for SM6375") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-12-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26arm64: dts: qcom: sm6125: correct sleep clock frequencyDmitry Baryshkov
The SM6125 platform uses PM6125 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-11-e9b08fbeadd3@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
generated by cgit (git 2.34.1) at 2025-09-12 13:35:15 +0000