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2024-12-10arm64: dts: renesas: white-hawk-single: Add R-Car Sound supportGeert Uytterhoeven
White Hawk Single boards can use the same ARD-AUDIO-DA7212 external audio board as the White Hawk board stack. Add support for building DTBs for them, and document the small differences in connector labels. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/7c840b6e08e0af8a6b9bd5516969eb585f16e10a.1733402907.git.geert+renesas@glider.be
2024-12-10arm64: dts: renesas: white-hawk-ard-audio: Drop SoC partGeert Uytterhoeven
The White Hawk with ARD-AUDIO-DA7212 external audio board stack is not specific to R8A779G0. Hence rename its DTS file name to drop the "r8a779g0-" prefix. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/0a72c67991828784066f76b61605d2f7913a353c.1733402907.git.geert+renesas@glider.be
2024-12-10arm64: dts: renesas: r8a779g3: Add White Hawk Single supportGeert Uytterhoeven
The White Hawk Single board with R-Car V4H ES3.0 (R8A779G3) uses an updated version of the R-Car V4H (R8A779G0) SoC. For now, there are no visible differences compared to the variant equipped with an R-Car V4H ES2.0 (R8A779G2) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/66d0fe78c393e6df2775287c730464e91732ec56.1733156661.git.geert+renesas@glider.be
2024-12-10arm64: dts: renesas: Add R8A779G3 SoC supportGeert Uytterhoeven
Add support for the Renesas R-Car V4H ES3.0 (R8A779G3) SoC, which is an updated version of the R-Car V4H (R8A779G0) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/978c41f932aa2dccd46ad91fc1ddfabacd1c254c.1733156661.git.geert+renesas@glider.be
2024-12-10arm64: dts: renesas: Factor out White Hawk Single board supportGeert Uytterhoeven
Move the common parts for the Renesas White Hawk Single board to white-hawk-single.dtsi, to enable future reuse. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/1661743b18a9ff9fac716f98a663b39fc8488d7e.1733156661.git.geert+renesas@glider.be
2024-12-10dt-bindings: soc: renesas: Document R8A779G3 White Hawk SingleGeert Uytterhoeven
Document the compatible value for the Renesas R-Car V4H ES3.0 (R8A779G3) SoC, as used on the Renesas White Hawk Single board. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/1d2d2a6cbf31c817f574f6eed310a960e6175afe.1733156661.git.geert+renesas@glider.be
2024-12-10dt-bindings: soc: renesas: Move R8A779G0 White Hawk upGeert Uytterhoeven
Move the R8A779G0-only White Hawk board stack section up, just below the R8A779G0-only White Hawk CPU section, to improve sort order. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/d553ef4b1f969f72e384f274d42ac7a62fe45fd4.1733156661.git.geert+renesas@glider.be
2024-12-10arm64: dts: renesas: rzg3s-smarc: Enable I2C1 and connected power monitorWolfram Sang
Enable I2C1 for the carrier board and the connected power monitor ISL28022. Limit the bus speed to the maximum the power monitor supports. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://lore.kernel.org/20241120085345.24638-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-10arm64: dts: renesas: rzg3s-smarc: Fix the debug serial aliasClaudiu Beznea
The debug serial of the RZ/G3S is SCIF0 which is routed on the Renesas RZ SMARC Carrier II board on the SER3_UART. Use serial3 alias for it for better hardware description. Along with it, the chosen properties were moved to the device tree corresponding to the RZ SMARC Carrier II board. Fixes: adb4f0c5699c ("arm64: dts: renesas: Add initial support for RZ/G3S SMARC SoM") Fixes: d1ae4200bb26 ("arm64: dts: renesas: Add initial device tree for RZ SMARC Carrier-II Board") Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241115134401.3893008-6-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-10arm64: dts: renesas: r9a08g045: Add the remaining SCIF interfacesClaudiu Beznea
The Renesas RZ/G3S SoC has 6 SCIF interfaces. SCIF0 is used as debug console. Add the remaining ones. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241115134401.3893008-5-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-10arm64: dts: mediatek: mt8183: Disable DSI display output by defaultChen-Yu Tsai
Most SoC dtsi files have the display output interfaces disabled by default, and only enabled on boards that utilize them. The MT8183 has it backwards: the display outputs are left enabled by default, and only disabled at the board level. Reverse the situation for the DSI output so that it follows the normal scheme. For ease of backporting the DPI output is handled in a separate patch. Fixes: 88ec840270e6 ("arm64: dts: mt8183: Add dsi node") Fixes: 19b6403f1e2a ("arm64: dts: mt8183: add mt8183 pumpkin board") Cc: stable@vger.kernel.org Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Fei Shao <fshao@chromium.org> Link: https://lore.kernel.org/r/20241025075630.3917458-2-wenst@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-12-10arm64: dts: mediatek: mt8183: Disable DPI display output by defaultChen-Yu Tsai
This reverts commit 377548f05bd0905db52a1d50e5b328b9b4eb049d. Most SoC dtsi files have the display output interfaces disabled by default, and only enabled on boards that utilize them. The MT8183 has it backwards: the display outputs are left enabled by default, and only disabled at the board level. Reverse the situation for the DPI output so that it follows the normal scheme. For ease of backporting the DSI output is handled in a separate patch. Fixes: 009d855a26fd ("arm64: dts: mt8183: add dpi node to mt8183") Fixes: 377548f05bd0 ("arm64: dts: mediatek: mt8183-kukui: Disable DPI display interface") Cc: stable@vger.kernel.org Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Fei Shao <fshao@chromium.org> Link: https://lore.kernel.org/r/20241025075630.3917458-1-wenst@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-12-10ARM: dts: stm32: lxa-tac: Add support for generation 3 devicesLeonard Göhrs
Add support for the lxa-tac generation 3 board based on the STM32MP153c. Signed-off-by: Leonard Göhrs <l.goehrs@pengutronix.de> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-10ARM: dts: stm32: lxa-tac: move adc and gpio{e,g} to gen{1,2} boardsLeonard Göhrs
This is a preparation patch in order to add lxa-tac generation 3 board. As the gen3 board has a different adc and gpio{e,g} setups, move these from the stm32mp15xc-lxa-tac.dtsi to the gen{1,2}.dts files. Signed-off-by: Leonard Göhrs <l.goehrs@pengutronix.de> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-10dt-bindings: arm: stm32: add compatible strings for Linux Automation LXA TAC ↵Leonard Göhrs
gen 3 The Linux Automation LXA TAC generation 3 is built around an OSD32MP153x SiP with CPU, RAM, PMIC, Oscillator and EEPROM. LXA TACs are a development tool for embedded devices with a focus on embedded Linux devices. Add compatible for the generation 3 based on the STM32MP153c. Signed-off-by: Leonard Göhrs <l.goehrs@pengutronix.de> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-10ARM: dts: stm32: lxa-tac: adjust USB gadget fifo sizes for multi functionLeonard Göhrs
Allow providing the Ethernet and mass storage functions on the USB peripheral port at the same time. Signed-off-by: Leonard Göhrs <l.goehrs@pengutronix.de> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-10ARM: dts: stm32: lxa-tac: extend the alias tableLeonard Göhrs
Some of the userspace software and tests depend on the can/i2c/spi devices having the same name on every boot. This may not always be the case based on e.g. parallel probe order. Assign static device numbers to all can/i2c/spi devices. Signed-off-by: Leonard Göhrs <l.goehrs@pengutronix.de> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-10ARM: dts: stm32: lxa-tac: disable the real time clockLeonard Göhrs
The RTC was enabled under the false assumption that the SoM already contains a suitable 32.768 kHz crystal. It does however not contain such a crystal and since none is fitted externally to the SoM the RTC can not be used on the hardware. Reflect that in the devicetree. Signed-off-by: Leonard Göhrs <l.goehrs@pengutronix.de> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-10ARM: dts: stm32: Fix IPCC EXTI declaration on stm32mp151Arnaud Pouliquen
The GIC IRQ type used for IPCC RX should be IRQ_TYPE_LEVEL_HIGH. Replacing the interrupt with the EXTI event changes the type to the numeric value 1, meaning IRQ_TYPE_EDGE_RISING. The issue is that EXTI event 61 is a direct event.The IRQ type of direct events is not used by EXTI and is propagated to the parent IRQ controller of EXTI, the GIC. Align the IRQ type to the value expected by the GIC by replacing the second parameter "1" with IRQ_TYPE_LEVEL_HIGH. Fixes: 7d9802bb0e34 ("ARM: dts: stm32: remove the IPCC "wakeup" IRQ on stm32mp151") Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-09arm64: dts: exynos: Add initial support for Samsung Galaxy S20 (x1slte)Umer Uddin
Add initial support for the Samsung Galaxy S20 (x1slte/SM-G980F) phone. It was launched in 2020, and it's based on the Exynos 990 SoC. It has only one configuration with 8GB of RAM and 128GB of UFS 3.0 storage. This device tree adds support for the following: - SimpleFB - 8GB RAM - Buttons Signed-off-by: Umer Uddin <umer.uddin@mentallysanemainliners.org> Link: https://lore.kernel.org/r/20241209080059.11891-5-umer.uddin@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-09arm64: dts: exynos: Add initial support for Samsung Galaxy S20 5G (x1s)Umer Uddin
Add initial support for the Samsung Galaxy S20 5G (x1s/SM-G981B) phone. It was launched in 2020, and it's based on the Exynos 990 SoC. It has only one configuration with 12GB of RAM and 128GB of UFS 3.0 storage. This device tree adds support for the following: - SimpleFB - 12GB RAM - Buttons Signed-off-by: Umer Uddin <umer.uddin@mentallysanemainliners.org> Link: https://lore.kernel.org/r/20241209080059.11891-4-umer.uddin@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-09arm64: dts: exynos: Add initial support for Samsung Galaxy S20 Series boards ↵Umer Uddin
(x1s-common) Add initial support for the Samsung Galaxy S20 Series (x1s-common) phones. They were launched in 2020, and are based on the Exynos 990 SoC. The devices have multiple RAM configurations, starting from 8GB going all the way up to 16GB for the S20 Ultra devices. This device tree adds support for the following: - SimpleFB - 8GB RAM (Any more will be mapped in device trees) - Buttons Signed-off-by: Umer Uddin <umer.uddin@mentallysanemainliners.org> Link: https://lore.kernel.org/r/20241209080059.11891-3-umer.uddin@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-09dt-bindings: arm: samsung: samsung-boards: Add bindings for SM-G981B and ↵Umer Uddin
SM-G980F board Add devicetree bindings for Samsung Galaxy S20 5G and Samsung Galaxy S20 board. Signed-off-by: Umer Uddin <umer.uddin@mentallysanemainliners.org> Link: https://lore.kernel.org/r/20241209080059.11891-2-umer.uddin@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-09arm64: dts: exynos: gs101: allow stable USB phy Vbus detectionAndré Draszik
For the DWC3 core to reliably detect the connected phy's Vbus state, we need to disable phy suspend. Add snps,dis_u2_susphy_quirk snps,dis_u3_susphy_quirk to do that. While at it, also add snps,has-lpm-erratum as this is set downstream which implies that the core was configured with LPM Erratum. We should do the same here. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20241203-gs101-phy-lanes-orientation-dts-v2-3-1412783a6b01@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-09arm64: dts: exynos: gs101: phy region for exynos5-usbdrd is largerAndré Draszik
Turns out there are some additional registers in the phy region, update the DT accordingly. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20241203-gs101-phy-lanes-orientation-dts-v2-2-1412783a6b01@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-09ARM: dts: stm32: Sort M24256E write-lockable page in DH STM32MP13xx DHCOR SoM DTMarek Vasut
Move the M24256E write-lockable page subnode after RTC subnode in DH STM32MP13xx DHCOR SoM DT to keep the list of nodes sorted by I2C address. No functional change. Fixes: 3f2e7d167307 ("ARM: dts: stm32: Describe M24256E write-lockable page in DH STM32MP13xx DHCOR SoM DT") Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-09ARM: dts: stm32: Increase CPU core voltage on STM32MP13xx DHCOR SoMMarek Vasut
The STM32MP13xx DHCOR DHSBC is populated with STM32MP13xx part capable of 1 GHz operation, increase the CPU core voltage to 1.35 V to make sure the SoC is stable even if the blobs unconditionally force the CPU to 1 GHz operation. It is not possible to make use of CPUfreq on the STM32MP13xx because the SCMI protocol 0x13 is not implemented by upstream OpTee-OS which is the SCMI provider. Fixes: 6331bddce649 ("ARM: dts: stm32: Add support for STM32MP13xx DHCOR SoM and DHSBC board") Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-09ARM: dts: stm32: Deduplicate serial aliases and chosen node for STM32MP15xx ↵Marek Vasut
DHCOM SoM Deduplicate /aliases { serialN = ... } and /chosen node into stm32mp15xx-dhcom-som.dtsi , since the content is identical on all carrier boards using the STM32MP15xx DHCOM SoM. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Christoph Niedermaier <cniedermaier@dh-electronics.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-09arm64: dts: st: Enable COMBOPHY on the stm32mp257f-ev1 boardChristian Bruel
Enable the COMBOPHY with external pad clock on stm32mp257f-ev1 board, to be used for the PCIe clock provider. Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-09arm64: dts: st: Add combophy node on stm32mp251Christian Bruel
Add support for COMBOPHY which is used either by the USB3 and PCIe controller. USB3 or PCIe mode is done with phy_set_mode(). PCIe internal reference clock can be generated from the internal clock source or optionnaly from an external 100Mhz pad. Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-09arm64: dts: st: add spdifrx support on stm32mp251Olivier Moysan
Add S/PDIFRX support to STM32MP25 SoC family. Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-09arm64: dts: st: add sai support on stm32mp251Olivier Moysan
Add SAI support to STM32MP25 SoC family. Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-09arm64: dts: st: add i2s support to stm32mp251Olivier Moysan
Add I2S support to STM32MP25 SoCs. Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-09arm64: dts: imx93-9x9-qsb: add temp-sensor nxp,p3t1085Frank Li
Add temp-sensor nxp,p3t1085 for imx93-9x9-qsb boards. Signed-off-by: Frank Li <Frank.Li@nxp.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-09arm64: dts: mediatek: mt8516: reserve 192 KiB for TF-AVal Packett
The Android DTB for the related MT8167 reserves 0x30000. This is likely correct for MT8516 Android devices as well, and there's never any harm in reserving 64KiB more. Fixes: 5236347bde42 ("arm64: dts: mediatek: add dtsi for MT8516") Signed-off-by: Val Packett <val@packett.cool> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20241204190524.21862-5-val@packett.cool Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-12-09arm64: dts: mediatek: mt8516: add i2c clock-div propertyVal Packett
Move the clock-div property from the pumpkin board dtsi to the SoC's since it belongs to the SoC itself and is required on other devices. Fixes: 5236347bde42 ("arm64: dts: mediatek: add dtsi for MT8516") Signed-off-by: Val Packett <val@packett.cool> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20241204190524.21862-4-val@packett.cool Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-12-09arm64: dts: mediatek: mt8516: fix wdt irq typeVal Packett
The GICv2 does not support EDGE_FALLING interrupts, so the watchdog would refuse to attach due to a failing check coming from the GIC driver. Fixes: 5236347bde42 ("arm64: dts: mediatek: add dtsi for MT8516") Signed-off-by: Val Packett <val@packett.cool> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20241204190524.21862-3-val@packett.cool Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-12-09arm64: dts: mediatek: mt8516: fix GICv2 rangeVal Packett
On the MT8167 which is based on the MT8516 DTS, the following error was appearing on boot, breaking interrupt operation: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set Similar to what's been proposed for MT7622 which has the same issue, fix by using the range reported by force_probe. Link: https://lore.kernel.org/all/YmhNSLgp%2Fyg8Vr1F@makrotopia.org/ Fixes: 5236347bde42 ("arm64: dts: mediatek: add dtsi for MT8516") Signed-off-by: Val Packett <val@packett.cool> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20241204190524.21862-2-val@packett.cool Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-12-09arm64: dts: mediatek: mt8186: Add Starmie deviceWojciech Macek
Add support for Starmie Chromebooks. Signed-off-by: Wojciech Macek <wmacek@chromium.org> Link: https://lore.kernel.org/r/20241129055720.3328681-3-wmacek@chromium.org Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-12-09dt-bindings: arm: mediatek: Add MT8186 Starmie ChromebooksWojciech Macek
Add an entry for the MT8186 based Starmie Chromebooks, also known as the ASUS Chromebook Enterprise CM30 Detachable (CM3001). The device is a tablet style chromebook. Signed-off-by: Wojciech Macek <wmacek@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20241129055720.3328681-2-wmacek@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-12-09arm64: dts: mediatek: Introduce MT8188 Geralt platform based CiriFei Shao
Introduce MT8188-based Chromebook Ciri, also known commercially as Lenovo Chromebook Duet (11", 9). Ciri is a detachable device based on the Geralt design, where Geralt is the codename for the MT8188 platform. Ciri offers 8 SKUs to accommodate different combinations of second-source components, including: - audio codecs (RT5682S and ES8326) - speaker amps (TAS2563 and MAX98390) - MIPI-DSI panels (BOE nv110wum-l60 and IVO t109nw41) Signed-off-by: Fei Shao <fshao@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20241124085739.290556-3-fshao@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-12-09dt-bindings: arm: mediatek: Add MT8188 Lenovo Chromebook Duet (11", 9)Fei Shao
Add entries for the MT8188-based Chromebook "Ciri", also known as Lenovo Chromebook Duet (11", 9). This device features a detachable design with touchscreen, detachable keyboard and USI 2.0 Stylus support, and has 8 SKUs to accommodate the combinations of second-source components. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Fei Shao <fshao@chromium.org> Link: https://lore.kernel.org/r/20241124085739.290556-2-fshao@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-12-09arm64: dts: mt8183: set DMIC one-wire mode on DamuHsin-Yi Wang
Sets DMIC one-wire mode on Damu. Fixes: cabc71b08eb5 ("arm64: dts: mt8183: Add kukui-jacuzzi-damu board") Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Hsin-Te Yuan <yuanhsinte@chromium.org> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/r/20241113-damu-v4-1-6911b69610dd@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-12-09arm64: dts: mediatek: mt8186: Move wakeup to MTU3 to get working suspendNícolas F. R. A. Prado
The current DT has the wakeup-source and mediatek,syscon-wakeup properties in the XHCI nodes, which configures USB wakeup after powering down the XHCI hardware block. However, since the XHCI controller is behind an MTU3 (USB3 DRD controller), the MTU3 only gets powered down after USB wakeup has been configured, causing the system to detect a wakeup, and results in broken suspend support as the system resumes immediately. Move the wakeup properties to the MTU3 nodes so that USB wakeup is only enabled after the MTU3 has powered down. With this change in place, it is possible to suspend and resume, and also to wakeup through USB, as tested on the Google Steelix (Lenovo 300e Yoga Chromebook Gen 4). Fixes: f6c3e61c5486 ("arm64: dts: mediatek: mt8186: Add MTU3 nodes") Reported-by: Wojciech Macek <wmacek@google.com> Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20241106-mt8186-suspend-with-usb-wakeup-v1-1-07734a4c8236@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-12-09arm64: dts: mediatek: mt8183-kukui: align thermal node names with bindingsKrzysztof Kozlowski
Bindings expect thermal zones node name to follow certain pattern. This fixes dtbs_check warning: mt8183-kukui-jacuzzi-burnet.dtb: thermal-zones: 'tboard1', 'tboard2' do not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-]{1,10}-thermal$', 'pinctrl-[0-9]+' Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241209112920.70060-1-krzysztof.kozlowski@linaro.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2024-12-09MAINTAINERS: add myself and Tudor as reviewers for Google Tensor SoCAndré Draszik
Add myself and Tudor as reviewers for the Google Tensor SoC alongside Peter. While at it, also add our IRC channel. Signed-off-by: André Draszik <andre.draszik@linaro.org> Acked-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20241203-gs101-maintainers-v1-1-f287036dbde5@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-09arm64: dts: exynos990: Add pmu and syscon-reboot nodesIgor Belwon
Add PMU syscon, and syscon-reboot nodes to the Exynos990 dtsi. Reboot of the Exynos990 SoC is handled by setting bit(SWRESET_TRIGGER[1]) of SWRESET register (PMU + 0x3a00). Tested using the "reboot" command. Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20241204145559.524932-3-igor.belwon@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-09arm64: dts: imx8mp-evk: Add NXP LVDS to HDMI adapter cardsLiu Ying
One ITE IT6263 LVDS to HDMI converter is populated on NXP IMX-LVDS-HDMI and IMX-DLVDS-HDMI adapter cards. Card IMX-LVDS-HDMI supports single LVDS link(IT6263 link1). Card IMX-DLVDS-HDMI supports dual LVDS links(IT6263 link1 and link2). Only one card can be enabled with one i.MX8MP EVK. Add dedicated overlays to support the below four connections: 1) imx8mp-evk-lvds0-imx-lvds-hdmi.dtso: i.MX8MP EVK LVDS0 connector <=> LVDS adapter card J6(IT6263 link1) 2) imx8mp-evk-lvds1-imx-lvds-hdmi.dtso: i.MX8MP EVK LVDS1 connector <=> LVDS adapter card J6(IT6263 link1) 3) imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtso: i.MX8MP EVK LVDS0 connector <=> DLVDS adapter card channel0(IT6263 link1) i.MX8MP EVK LVDS1 connector <=> DLVDS adapter card channel1(IT6263 link2) 4) imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtso: i.MX8MP EVK LVDS1 connector <=> DLVDS adapter card channel0(IT6263 link1) i.MX8MP EVK LVDS0 connector <=> DLVDS adapter card channel1(IT6263 link2) Part links: https://www.nxp.com/part/IMX-LVDS-HDMI https://www.nxp.com/part/IMX-DLVDS-HDMI Signed-off-by: Liu Ying <victor.liu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-09arm64: dts: imx8mp-skov-revb-mi1010ait-1cp1: Set "media_disp2_pix" clock ↵Liu Ying
rate to 70MHz The LVDS panel "multi-inno,mi1010ait-1cp" used on this platform has a typical pixel clock rate of 70MHz. Set "media_disp2_pix" clock rate to that rate, instead of the original 68.9MHz. The LVDS serial clock is controlled by "media_ldb" clock. It should run at 490MHz(7-fold the pixel clock rate due to single LVDS link). Set "video_pll1" clock rate and "media_ldb" to 490MHz to achieve that. This should be able to suppress this LDB driver warning: [ 17.206644] fsl-ldb 32ec0000.blk-ctrl:bridge@5c: Configured LDB clock (70000000 Hz) does not match requested LVDS clock: 490000000 Hz This also makes the display mode used by the panel pass mode validation against pixel clock rate and "media_ldb" clock rate in a certain display driver. Signed-off-by: Liu Ying <victor.liu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-12-09MAINTAINERS: Update entry for DH electronics DHSOM SoMs and boardsMarek Vasut
Update the MAINTAINERS entry to cover all DH electronics DHSOM SoMs and boards. The DHSOM is the name which covers all modules, DHCOM is the SODIMM seated SoM, DHCOR is the solder on module. Use glob pattern to match on every DT file which contains either of those three module substrings in lowercase. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
generated by cgit (git 2.34.1) at 2025-09-13 10:01:34 +0000