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2021-12-16arm64: tegra: Add NVENC and NVJPG nodes for Tegra186 and Tegra194Jon Hunter
Populate the device-tree nodes for NVENC and NVJPG Host1x engines on Tegra186 and Tegra194. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Add support to enumerate SD in UHS modePrathamesh Shete
Add support to enumerate SD in UHS mode on Tegra194. Add required device-tree properties in SDMMC1 and SDMMC3 instances to enable dynamic pad voltage switching and enumerate SD card in UHS-I modes. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Add NVIDIA Jetson AGX Orin Developer Kit supportMikko Perttunen
The Jetson AGX Orin Developer Kit is a continuation of the Jetson Developer Kit line using the new NVIDIA Tegra234 (Orin) SoC. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Describe Tegra234 CPU hierarchyThierry Reding
The NVIDIA Tegra234 SoC has 3 clusters of 4 Cortex-A78AE CPU cores each, for a total of 12 CPUs. Each CPU has 64 KiB instruction and data caches with each cluster having an additional 256 KiB unified L2 cache and a 2 MiB L3 cache. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Add main and AON GPIO controllers on Tegra234Thierry Reding
These two controllers expose general purpose I/O pins that can be used to control or monitor a variety of signals. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Add Tegra234 TCU deviceMikko Perttunen
Add a device for TCU (Tegra Combined UART) used for serial console. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Fill in properties for Tegra234 eMMCMikko Perttunen
Add missing properties to the eMMC controller, as required to use it on actual hardware. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Update Tegra234 BPMP channel addressesMikko Perttunen
On final Tegra234 systems, shared memory for communication with BPMP is located at offset 0x70000 in SYSRAM. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Add clock for Tegra234 RTCMikko Perttunen
The RTC device requires a clock. Add it. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Fixup SYSRAM referencesThierry Reding
The json-schema bindings for SRAM expect the nodes to be called "sram" rather than "sysram" or "shmem". Furthermore, place the brackets around the SYSRAM references such that a two-element array is created rather than a two-element array nested in a single-element array. This is not relevant for device tree itself, but allows the nodes to be properly validated against json-schema bindings. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16Merge tag 'tegra-for-5.17-dt-bindings-memory' into for-5.17/arm64/dtThierry Reding
dt-bindings: memory: Add Tegra234 support This stable tag contains the addition of the EMC clock ID and an initial list of memory client IDs for Tegra234 and will be shared between the memory and ARM SoC trees.
2021-12-16dt-bindings: misc: Convert Tegra MISC to json-schemaThierry Reding
Convert the device tree bindings for the MISC register block found on NVIDIA Tegra SoCs from plain text to json-schema format. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16dt-bindings: memory: tegra: Add Tegra234 supportThierry Reding
Document the variant of the memory controller and external memory controllers found on Tegra234 and add some memory client and SMMU stream ID definitions for use in device tree files. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16dt-bindings: Add YAML bindings for NVENC and NVJPGJon Hunter
Add YAML device tree bindings for the Tegra NVENC and NVJPG Host1x engines. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16dt-bindings: memory: tegra: Update for Tegra194Thierry Reding
The #interconnect-cells properties are required to hook up memory clients to the MC/EMC in interconnects properties. Add a description for these properties. For the nested EMC controller, the list of required properties was missing. Add it so that the validation can be more strict. Also, allow multiple reg entries required by Tegra194 and later. While at it, also remove the dummy BPMP node from the example because it is incomplete and fails validation. It's also not necessary for this file and the BPMP DT schema already has a full example. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16dt-bindings: sram: Document NVIDIA Tegra SYSRAMThierry Reding
Tegra SoCs have extra on-chip RAM that can be used for inter-processor communication. Tegra186 and later make use of it to establish a two-way channel between the CCPLEX and BPMP. Add missing compatible strings for Tegra186 and Tegra194 as well as a new compatible string for Tegra234. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16dt-bindings: Update headers for Tegra234Mikko Perttunen
Add a few more clocks that will be used in follow-up patches to enable more functionality on Tegra234. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16dt-bindings: tegra: Document Jetson AGX Orin (and devkit)Thierry Reding
Add the compatible strings for the Jetson AGX Orin and the corresponding developer kit. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16dt-bindings: tegra: Describe recent developer kits consistentlyThierry Reding
Add descriptions to entries that were missing one and don't try to combine multiple entries into one to avoid confusion. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: dts: renesas: rzg2l-smarc-som: Add vdd core regulatorBiju Das
Add vdd core regulator (1.1 V). This patch add regulator support for gpu. The H/W manual mentions nothing about a gpu regulator. So using vdd core regulator for gpu. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211208104026.421-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-12-16arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU nodeBiju Das
Add Mali-G31 GPU node to SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211208104026.421-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-12-16Merge tag 'omap-for-v5.17/dt-signed' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt Devicetree changes for omaps for v5.17 merge window These changes are mostly minor non-urgent fixes for typos and binding checks. The system-power-controller gets configured for more am3 devices as it's not am335x-boneblack speicif. For for am437x we add magnetic card reader support. Note that the asahi-kasei,ak8975 binding changes may produce a new binding check warning as the binding related change is merged separately. * tag 'omap-for-v5.17/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: am335x: Use correct vendor prefix for Asahi Kasei Corp. ARM: dts: motorola-mapphone: Drop second ti,wlcore compatible value ARM: dts: am437x-gp-evm: enable ADC1 ARM: dts: am43xx: Describe the magnetic reader/ADC1 hardware module ARM: dts: am437x-cm-t43: Use a correctly spelled DT property ARM: dts: am335x-icev2: Add system-power-controller to RTC node ARM: dts: am335x-boneblack-common: move system-power-controller ARM: dts: elpida_ecb240abacn: Change Elpida compatible Link: https://lore.kernel.org/r/pull-1639659798-679261@atomide.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-16Merge tag 'socfpga_dts_update_for_v5.17' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt SoCFPGA dts updates for v5.17 - Update N5X to include qspi, usb and ethernet - Adjust NAND partition size for Agilex and Stratix10 * tag 'socfpga_dts_update_for_v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: arm64: dts: Update NAND MTD partition for Agilex and Stratix 10 arm64: dts: n5x: add qspi, usb, and ethernet support Link: https://lore.kernel.org/r/20211215164545.300273-1-dinguyen@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-16ARM: tegra: Add OPP tables and power domains to Tegra20 device-treesDmitry Osipenko
Add OPP tables and power domains to all peripheral devices which support power management on Tegra20 SoC. Tested-by: Paul Fertser <fercerpav@gmail.com> # PAZ00 T20 Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16ARM: tegra: Add 500 MHz entry to Tegra30 memory OPP tableDmitry Osipenko
Extend memory OPPs with 500 MHz entry. This clock rate is used by ASUS Transformer tablets. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: dts: imx8mp-evk: configure multiple queues on eqosXiaoliang Yang
Eqos ethernet support five queues on hardware, enable these queues and configure the priority of each queue. Uses Strict Priority as scheduling algorithms to ensure that the TSN function works. The priority of each queue is a bitmask value that maps VLAN tag priority to the queue. Since the hardware only supports five queues, this patch maps priority 0-4 to queues one by one, and priority 5-7 to queue 4. The total fifo size of 5 queues is 8192 bytes, if enable 5 queues with store-and-forward mode, it's not enough for large packets, which would trigger fifo overflow frequently. This patch set DMA to thresh mode to enable all 5 queues. Signed-off-by: Xiaoliang Yang <xiaoliang.yang_1@nxp.com> Reviewed-by: Joakim Zhang <qiangqing.zhang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-16ARM: dts: imx6qdl: phytec: Add support for optional PEB-AV-02 LCD adapterYunus Bas
The PEB-AV-02 expansion adapter extends the phyBOARD-Mira boards to connect parallel LCD displays, either with capacitive or resistive touch. Signed-off-by: Yunus Bas <y.bas@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-16ARM: dts: imx6qdl: phytec: Add support for optional PEB-EVAL-01 boardYunus Bas
The PHYTEC PEV-EVAL-01 expansion board adds support for additional gpio-triggered user-leds and gpio-key support. Signed-off-by: Yunus Bas <y.bas@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-16arm64: dts: ls1028a-qds: add overlays for various serdes protocolsAlex Marginean
Add overlays for various serdes protocols on LS1028A QDS board using different PHY cards. These should be applied at boot, based on serdes configuration. If no overlay is applied, only the RGMII interface on the QDS is available in Linux. Building device tree fragments requires passing the "-@" argument to dtc, which increases the base dtb size and might cause some platforms to fail to store the new binary. To avoid that, it would be nice to only pass "-@" for the platforms where fragments will be used, aka LS1028A-QDS. One approach suggested by Rob Herring is used here: https://lore.kernel.org/patchwork/patch/821645/ Also moved the enet* override nodes in dts file to be in alphabetic order. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Jason Liu <jason.hui.liu@nxp.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-16arm64: dts: ls1028a-qds: enable lpuart1Vabhav Sharma
LPUART nodes by default are disabled in LS1028A device tree, Enabling LPUART1 node. Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Acked-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-16arm64: dts: ls1028a-qds: move rtc node to the correct i2c busBiwen Li
The i2c rtc is on i2c2 bus not i2c1 bus, so fix it in dts. Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Li Yang <leoyang.lil@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-16arm64: dts: ls1028a-rdb: enable pwm0Biwen Li
Enable pwm0 on ls1028a-rdb board which uses flextimer1. Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-16arm64: dts: ls1028a: add flextimer based pwm nodesBiwen Li
Add pwm nodes using flextimer controller. Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-16arm64: dts: ls1028a: add ftm_alarm1 node to be used as wakeup sourceBiwen Li
Add flextimer2 based ftm_alarm1 node and enable it to be the default rtc wakeup source for rdb and qds boards instead of the original flextimer1 which is used by PWM. The ftm_alarm0 node hence is disabled by default. Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-16arm64: dts: ls1028a: Add PCIe EP nodesXiaowei Bao
Add PCIe EP nodes for ls1028a to support EP mode. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-16ARM: dts: imx6qdl-dhcom: Add USB overcurrent pin on SoM layerChristoph Niedermaier
Add USB overcurrent pin muxing on SoM layer. On DRC02 and PDK2 the USB overcurrent pin isn't connected, but a USB hub on the board takes care of the USB overcurrent instead. Therefore disable it there with the property disable-over-current. Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <festevam@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: kernel@dh-electronics.com To: linux-arm-kernel@lists.infradead.org Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-16arm64: dts: lx2162a-qds: add interrupt line for RTC nodeBiwen Li
Add interrupt line for RTC node on lx2162a-qds Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-16arm64: dts: lx2162a-qds: support SD UHS-I and eMMC HS400 modesYangbo Lu
The default NXP SDHC adapter cards for LX2162AQDS are SD 2.0/3.0 adapter card for eSDHC1, and eMMC 5.1 adapter card for eSDHC2. Add speed modes properties supported by the two adapters in device tree node. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-16arm64: dts: lx2160a: enable usb3-lpm-capable for usb3 nodesRan Wang
Enable USB3 HW LPM feature for lx2160a. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-16arm64: dts: lx2160a-qds: Add mdio mux nodesPankaj Bansal
The two external MDIO buses used to communicate with phy devices that are external to SOC are muxed in LX2160AQDS board. These buses can be routed to any one of the eight IO slots on LX2160AQDS board depending on value in fpga register 0x54. Additionally the external MDIO1 is used to communicate to the onboard RGMII phy devices. The mdio1 is controlled by bits 4-7 of fpga register and mdio2 is controlled by bits 4-7 of fpga register. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-16arm64: dts: lx2160a: add optee-tz nodePankaj Gupta
Disabled by default in SoC dtsi and enables in board dts files. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-16arm64: dts: lx2160a-rdb: Add Inphi PHY nodeIoana Radulescu
DPMAC5 and DPMAC6 are connected to 25G Inphi PHY Signed-off-by: Vicentiu Galanopulo <vicentiu.galanopulo@nxp.com> Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-16arm64: dts: imx8mm: don't assign PLL2 in SoC dtsiLucas Stach
The base i.MX8MM dtsi changes the audio PLL2 rate, which gets in the way if it should be used for anything else than audio. As this PLL doesn't seem to be used by any upstream supported board, just remove the rate configuration to allow boards to set it up as they wish. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-16arm64: dts: allwinner: h6: Add Hantro G2 nodeJernej Skrabec
H6 SoC has a second VPU, dedicated to VP9 decoding. It's a slightly older design, though. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20211129182633.480021-10-jernej.skrabec@gmail.com
2021-12-16arm64: dts: nitrogen8-som: correct i2c1 pad-ctrlLucas Stach
The slew rate and drive-strength of the i2c1 pads were much too high. Bring them down to avoid signal quality issues. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-16arm64: dts: nitrogen8-som: correct network PHY resetLucas Stach
Add the missing reset-gpios property to allow Linux to fully reset the network PHY and fix the pinmux to add the neccessary pull-ups for the PHY strap configuration. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-16ARM: dts: imx7d-remarkable2: add wacom digitizer deviceAlistair Francis
Add Wacom I2C support for the reMarkable 2 eInk tablet using the generic I2C HID framework. Signed-off-by: Alistair Francis <alistair@alistair23.me> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-16ARM: dts: imx6ulz-bsh-smm-m2: Add BSH SMM-M2 IMX6ULZ SystemMasterMichael Trimarchi
Add DTS of BSH SMM-M2 SystemMaster. This version comes with: - 128 MiB DDR3 RAM - 256 MiB Nand - wifi - bluetooth Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-15ARM: dts: qcom: Drop input-name propertyDang Huynh
This property doesn't seem to exist in the documentation nor in source code, but for some reason it is defined in a bunch of device trees. Signed-off-by: Dang Huynh <danct12@riseup.net> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211123161919.1506755-1-danct12@riseup.net
2021-12-15arm64: dts: mediatek: add pinctrl support for mt7986bSam Shih
Add mt7986b pinctrl node Signed-off-by: Sam Shih <sam.shih@mediatek.com> Link: https://lore.kernel.org/r/20211122123552.8218-3-sam.shih@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
generated by cgit (git 2.34.1) at 2025-10-02 10:27:42 +0000