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Add the host1x memory client hotflush reset on Tegra124.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add the host1x, gr2d and gr3d memory client hotflush resets on Tegra114.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Align all pin controller node names with the expectations of the DT
bindings in Documentation/devicetree/bindings/pinctrl/pinctrl.yaml.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/09a09c8ac9cb1a11b859c1ab9d9eae84cfefb1bb.1639666967.git.geert+renesas@glider.be
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Add the DT binding for the i.MX8MN DISP blk-ctrl.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The PEB-WLBT-05 is equipped with a Sterling-LWB radio module, which is
capable of Wi-Fi 802.11 b/g/n and Bluetooth 4.2.
Signed-off-by: Yunus Bas <y.bas@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The properties have been commented out to prevent a regression a while
ago. The first regression should be resolved by commit 44af7927316e
("spi: Map SPI OF client IRQ at probe time").
The second regression is probably addressed by commit 494fd7b7ad10
("PM / core: fix deferred probe breaking suspend resume order") and/or
maybe others. Readd the gpio-ranges properties to see whether
regressions still get reported.
This reverts commit 4f1d841475e1 ("ARM: tegra: Comment out gpio-ranges
properties").
Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Dmitry Osipenko <digetx@gmail.com>
[treding@nvidia.com: drop redundant gpio-ranges from Ouya DTS file]
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Enable S/PDIF controller to enable HDMI audio support on Toshiba AC100.
Use nvidia,fixed-parent-rate property that prevents audio rate conflict
between S/PDIF and I2S.
Tested-by: Agneli <poczt@protonmail.ch>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Enable S/PDIF controller to enable HDMI audio support on Acer A500.
Use nvidia,fixed-parent-rate property that prevents audio rate conflict
between S/PDIF and I2S.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add HDMI audio graph to Tegra20 device-tree to enable HDMI audio on
Tegra20 devices.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add S/PDIF node to Tegra20 device-tree. It's needed for enabling HDMI
audio support.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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MPE, VI, EPP and ISP were never used and we don't have drivers for them.
Since these modules are enabled by default in a device-tree, a device is
created for them, blocking voltage scaling because there is no driver to
bind, and thus, state of PMC driver is never synced. Disable them.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Memory access must be blocked before hardware reset is asserted and before
power is gated, otherwise a serious hardware fault is inevitable. Add
reset for memory clients to the GR2D, GR3D and Host1x nodes.
Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30
Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Memory access must be blocked before hardware reset is asserted and before
power is gated, otherwise a serious hardware fault is inevitable. Add
reset for memory clients to the GR2D, GR3D and Host1x nodes.
Tested-by: Paul Fertser <fercerpav@gmail.com> # PAZ00 T20
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add OPP tables and power domains to all peripheral devices which
support power management on Tegra30 SoC.
Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30
Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Use the interconnects property to hook up the MMC and BPMP to the memory
controller. This is needed to set the correct bus-level DMA mask, which
is a prerequisite for adding IOMMU support.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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This adds the memory controller and the embedded external memory
controller found on the Tegra234 SoC.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add the missing EMC general interrupt for the external memory controller
on Tegra194.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add required device-tree properties to populate all speed
modes supported by SDMMC4 instance of Tegra194 SDHCI controller.
Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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DMA operations for the Tegra194 Video Image Compositor (VIC) are
coherent and so populate the 'dma-coherent' property.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Name the Ethernet PHY device tree nodes as expected by the DT schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The only-1-8-v property is not support by an DT schema, so drop it.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Make the order of the clocks and clock-names properties match the order
in the device tree bindings. This isn't strictly necessary from a point
of view of the operating system because matching will be done based on
the clock-names, but it makes it easier to validate the device trees
against the DT schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add missing interrupts, clocks, clock-names, reset and reset-names
properties for the TSEC blocks found on Tegra210.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The XUSB pad controller handles the various PLL power supplies, so
remove any references to them from the PCIe and XUSB controller device
tree nodes.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The XUSB pad controller handles the various PLL power supplies, so
remove any references to them from the XUSB controller device tree
node.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The XUSB pad controller handles the various PLL power supplies, so
remove any references to them from the PCIe and XUSB controller device
tree nodes.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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GPIO hog nodes must have a "hog-" prefix or "-hog" suffix according to
the DT schema. Rename all such nodes to allow validation to pass.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Remove the unsupported "regulator-disable-ramp-delay" properties which
ended up in various DTS files for some reason.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The TCU is basically a serial port (albeit a fancy one), so it should be
named "serial".
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The "core_m" clock is not documented in the Tegra194 PCIe device tree
bindings, so remove it.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The num-viewport property is never used and can be dropped, whereas the
"iommus" property is not needed since we use "iommu-map-mask" and
"iommu-map" already.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The HSP instances on Tegra194 are not fully compatible with the version
found on Tegra186, so drop the fallback compatible string from the list.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The Tegra194 pinmux DT bindings do not define the nvidia,lpdr property,
so drop them from the device trees that have listed them.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The standard "jedec," vendor prefix should be used for SPI NOR flash
chips. This allows the right DT schema to be picked for validation.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Audio graph endpoints don't have a "reg" property, so they shouldn't
have a unit-address either.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The Tegra186 CCPLEX cluster register region is 4 MiB is length, not 4
MiB - 1. This was likely presumed to be the "limit" rather than length.
Fix it up.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The I2C controller found on Tegra186 is not fully compatible with the
Tegra210 version, so drop the fallback compatible string from the list.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Child nodes of the TI INA3221 power monitor device tree node should be
called input@* according to the DT schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The DT schema requires that nodes representing thermal zones include a
"-thermal" suffix in their name.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Make the order of the clocks and clock-names properties match the order
in the device tree bindings. This isn't strictly necessary from a point
of view of the operating system because matching will be done based on
the clock-names, but it makes it easier to validate the device trees
against the DT schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The CML1 and PLL_E clocks are never explicitly used by the AHCI
controller found on Tegra132, so drop them from the corresponding device
tree node.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The I2C controller found on Tegra124 is not fully compatible with the
Tegra114 version, so drop the fallback compatible string from the list.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add peripheral OPP tables on Tegra132 and wire them up to ACTMON and the
EMC. While at it, add the missing "#interconnect-cells" properties to
the memory controller and external memory controller nodes. Also set the
"#reset-cells" property for the memory controller because it exports the
hotflush reset controls.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The TKE (time-keeping engine) found on Tegra132 is not backwards
compatible with the version found on Tegra20, so update the compatible
string list accordingly.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The Tegra PMC device tree bindings don't support the "#wake-cells" and
"nvidia,reset-gpio" properties, so remove them.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The AS3722 pinmux device tree node doesn't have a "reg" property and
therefore must not have a unit-address, so drop it.
While at it, add missing unit-addresses for the charger and smart
battery IC's on the ChromeOS embedded controller's I2C tunnel bus.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The native timers IP block found on NVIDIA Tegra SoCs implements a
watchdog timer that can be used to recover from system hangs. Add the
device tree node on Tegra186.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Regulators defined at the top level in device tree are no longer part of
a simple bus and therefore don't have a reg property. Nodes without a
reg property shouldn't have a unit-address either, so drop the unit
address from the node names. To ensure nodes aren't duplicated (in which
case they would end up merged in the final DTB), append the name of the
regulator to the node name.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Clocks defined at the top level in device tree are no longer part of a
simple bus and therefore don't have a reg property. Nodes without a reg
property shouldn't have a unit-address either, so drop the unit address
from the node names. To ensure nodes aren't duplicated (in which case
they would end up merged in the final DTB), append the name of the clock
to the node name.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The display controllers are attached to a separate ARM SMMU instance
that is dedicated to servicing isochronous memory clients. Add this ISO
instance of the ARM SMMU to device tree.
Please note that the display controllers are not hooked up to this SMMU
yet, because we are still missing a means to transition framebuffers
used by the bootloader to the kernel.
This based upon an initial patch by Thierry Reding <treding@nvidia.com>.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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