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The num-viewport property is never used and can be dropped, whereas the
"iommus" property is not needed since we use "iommu-map-mask" and
"iommu-map" already.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The HSP instances on Tegra194 are not fully compatible with the version
found on Tegra186, so drop the fallback compatible string from the list.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The Tegra194 pinmux DT bindings do not define the nvidia,lpdr property,
so drop them from the device trees that have listed them.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The standard "jedec," vendor prefix should be used for SPI NOR flash
chips. This allows the right DT schema to be picked for validation.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Audio graph endpoints don't have a "reg" property, so they shouldn't
have a unit-address either.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The Tegra186 CCPLEX cluster register region is 4 MiB is length, not 4
MiB - 1. This was likely presumed to be the "limit" rather than length.
Fix it up.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The I2C controller found on Tegra186 is not fully compatible with the
Tegra210 version, so drop the fallback compatible string from the list.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Child nodes of the TI INA3221 power monitor device tree node should be
called input@* according to the DT schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The DT schema requires that nodes representing thermal zones include a
"-thermal" suffix in their name.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Make the order of the clocks and clock-names properties match the order
in the device tree bindings. This isn't strictly necessary from a point
of view of the operating system because matching will be done based on
the clock-names, but it makes it easier to validate the device trees
against the DT schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The CML1 and PLL_E clocks are never explicitly used by the AHCI
controller found on Tegra132, so drop them from the corresponding device
tree node.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The I2C controller found on Tegra124 is not fully compatible with the
Tegra114 version, so drop the fallback compatible string from the list.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add peripheral OPP tables on Tegra132 and wire them up to ACTMON and the
EMC. While at it, add the missing "#interconnect-cells" properties to
the memory controller and external memory controller nodes. Also set the
"#reset-cells" property for the memory controller because it exports the
hotflush reset controls.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The TKE (time-keeping engine) found on Tegra132 is not backwards
compatible with the version found on Tegra20, so update the compatible
string list accordingly.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The Tegra PMC device tree bindings don't support the "#wake-cells" and
"nvidia,reset-gpio" properties, so remove them.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The AS3722 pinmux device tree node doesn't have a "reg" property and
therefore must not have a unit-address, so drop it.
While at it, add missing unit-addresses for the charger and smart
battery IC's on the ChromeOS embedded controller's I2C tunnel bus.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The native timers IP block found on NVIDIA Tegra SoCs implements a
watchdog timer that can be used to recover from system hangs. Add the
device tree node on Tegra186.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Regulators defined at the top level in device tree are no longer part of
a simple bus and therefore don't have a reg property. Nodes without a
reg property shouldn't have a unit-address either, so drop the unit
address from the node names. To ensure nodes aren't duplicated (in which
case they would end up merged in the final DTB), append the name of the
regulator to the node name.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Clocks defined at the top level in device tree are no longer part of a
simple bus and therefore don't have a reg property. Nodes without a reg
property shouldn't have a unit-address either, so drop the unit address
from the node names. To ensure nodes aren't duplicated (in which case
they would end up merged in the final DTB), append the name of the clock
to the node name.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The display controllers are attached to a separate ARM SMMU instance
that is dedicated to servicing isochronous memory clients. Add this ISO
instance of the ARM SMMU to device tree.
Please note that the display controllers are not hooked up to this SMMU
yet, because we are still missing a means to transition framebuffers
used by the bootloader to the kernel.
This based upon an initial patch by Thierry Reding <treding@nvidia.com>.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Populate the device-tree nodes for NVENC and NVJPG Host1x engines on
Tegra186 and Tegra194.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add support to enumerate SD in UHS mode on Tegra194. Add required
device-tree properties in SDMMC1 and SDMMC3 instances to enable dynamic
pad voltage switching and enumerate SD card in UHS-I modes.
Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The Jetson AGX Orin Developer Kit is a continuation of the Jetson
Developer Kit line using the new NVIDIA Tegra234 (Orin) SoC.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The NVIDIA Tegra234 SoC has 3 clusters of 4 Cortex-A78AE CPU cores each,
for a total of 12 CPUs. Each CPU has 64 KiB instruction and data caches
with each cluster having an additional 256 KiB unified L2 cache and a 2
MiB L3 cache.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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These two controllers expose general purpose I/O pins that can be used
to control or monitor a variety of signals.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add a device for TCU (Tegra Combined UART) used for serial console.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add missing properties to the eMMC controller, as required to use it on
actual hardware.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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On final Tegra234 systems, shared memory for communication with BPMP is
located at offset 0x70000 in SYSRAM.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The RTC device requires a clock. Add it.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The json-schema bindings for SRAM expect the nodes to be called "sram"
rather than "sysram" or "shmem". Furthermore, place the brackets around
the SYSRAM references such that a two-element array is created rather
than a two-element array nested in a single-element array. This is not
relevant for device tree itself, but allows the nodes to be properly
validated against json-schema bindings.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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dt-bindings: memory: Add Tegra234 support
This stable tag contains the addition of the EMC clock ID and an initial
list of memory client IDs for Tegra234 and will be shared between the
memory and ARM SoC trees.
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Convert the device tree bindings for the MISC register block found on
NVIDIA Tegra SoCs from plain text to json-schema format.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Document the variant of the memory controller and external memory
controllers found on Tegra234 and add some memory client and SMMU
stream ID definitions for use in device tree files.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add YAML device tree bindings for the Tegra NVENC and NVJPG Host1x
engines.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The #interconnect-cells properties are required to hook up memory
clients to the MC/EMC in interconnects properties. Add a description for
these properties.
For the nested EMC controller, the list of required properties was
missing. Add it so that the validation can be more strict.
Also, allow multiple reg entries required by Tegra194 and later.
While at it, also remove the dummy BPMP node from the example because it
is incomplete and fails validation. It's also not necessary for this
file and the BPMP DT schema already has a full example.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Tegra SoCs have extra on-chip RAM that can be used for inter-processor
communication. Tegra186 and later make use of it to establish a two-way
channel between the CCPLEX and BPMP. Add missing compatible strings for
Tegra186 and Tegra194 as well as a new compatible string for Tegra234.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add a few more clocks that will be used in follow-up patches to enable
more functionality on Tegra234.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add the compatible strings for the Jetson AGX Orin and the
corresponding developer kit.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add descriptions to entries that were missing one and don't try to
combine multiple entries into one to avoid confusion.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The prima driver facilitates the direct programming of beacon filter tables via
SMD commands.
The purpose of beacon filters is quote:
/* When beacon filtering is enabled, firmware will
* analyze the selected beacons received during BMPS,
* and monitor any changes in the IEs as listed below.
* The format of the table is:
* - EID
* - Check for IE presence
* - Byte offset
* - Byte value
* - Bit Mask
* - Byte reference
*/
The default filter table looks something like this:
tBeaconFilterIe gaBcnFilterTable[12] =
{
{ WLAN_EID_DS_PARAMS, 0u, { 0u, 0u, 0u, 0u } },
{ WLAN_EID_ERP_INFO, 0u, { 0u, 0u, 248u, 0u } },
{ WLAN_EID_EDCA_PARAM_SET, 0u, { 0u, 0u, 240u, 0u } },
{ WLAN_EID_QOS_CAPA, 0u, { 0u, 0u, 240u, 0u } },
{ WLAN_EID_CHANNEL_SWITCH, 1u, { 0u, 0u, 0u, 0u } },
{ WLAN_EID_QUIET, 1u, { 0u, 0u, 0u, 0u } },
{ WLAN_EID_HT_OPERATION, 0u, { 0u, 0u, 0u, 0u } },
{ WLAN_EID_HT_OPERATION, 0u, { 1u, 0u, 248u, 0u } },
{ WLAN_EID_HT_OPERATION, 0u, { 2u, 0u, 235u, 0u } },
{ WLAN_EID_HT_OPERATION, 0u, { 5u, 0u, 253u, 0u } },
{ WLAN_EID_PWR_CONSTRAINT, 0u, { 0u, 0u, 0u, 0u } },
{ WLAN_EID_OPMODE_NOTIF, 0u, { 0u, 0u, 0u, 0u } }
};
Add in an equivalent filter set as present in the prima Linux driver.
For now omit the beacon filter "rem" command as the driver does not have an
explicit call to that SMD command. The filter mask should only count when
we are inside BMPS anyway.
Replicating the ability to program the filter table gives us scope to add and
remove elements in future. For now though this patch makes the rote-copy of the
downstream Linux beacon filter table, which we can tweak as desired from now
on.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com>
Link: https://lore.kernel.org/r/20211214134630.2214840-4-bryan.odonoghue@linaro.org
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The comment in the header with respect to beacon filtering makes a
reference to "the structure above" and "the structure below" which would be
informative if the comment appeared in the right place but, it does not.
Fix the comment location so that it a least makes sense w/r/t the physical
location statements.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com>
Link: https://lore.kernel.org/r/20211214134630.2214840-3-bryan.odonoghue@linaro.org
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The beacon filter structures need to be packed. Right now its fine because
we don't yet use these structures so just pack them without marking it for
backporting.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Loic Poulain <loic.poulain@linaro.org>
Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com>
Link: https://lore.kernel.org/r/20211214134630.2214840-2-bryan.odonoghue@linaro.org
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Host DDR memory (contiguous 45 MB in mode-0 or 15 MB in mode-2)
is reserved through DT entries for firmware usage. Send the base
address from DT entries.
If DT entry is available, PCI device will work with
fixed_mem_region else host allocates multiple segments.
IPQ8074 on HK10 board supports multiple PCI devices.
IPQ8074 + QCN9074 is tested with this patch.
Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.4.0.1-01838-QCAHKSWPL_SILICONZ-1
Signed-off-by: Anilkumar Kolli <akolli@codeaurora.org>
Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com>
Link: https://lore.kernel.org/r/1638789319-2950-2-git-send-email-akolli@codeaurora.org
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Ath11k driver supports PCI devices such as QCN9074/QCA6390.
Ath11k firmware uses host DDR memory, DT entry is used to
reserve host DDR memory regions, send these memory base
addresses using DT entries.
Signed-off-by: Anilkumar Kolli <akolli@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com>
Link: https://lore.kernel.org/r/1638789319-2950-1-git-send-email-akolli@codeaurora.org
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Florian Westphal says:
====================
fib: merge nl policies
v4: resend with fixed subject line. I preserved review tags
from David Ahern.
v3: drop first two patches, otherwise unchanged.
This series merges the different (largely identical) nla policies.
v2 also squashed the ->suppress() implementation, I've dropped this.
Problem is that it needs ugly ifdef'ry to avoid build breakage
with CONFIG_INET=n || IPV6=n.
Given that even microbenchmark doesn't show any noticeable improvement
when ->suppress is inlined (it uses INDIRECT_CALLABLE) i decided to toss
the patch instead of adding more ifdefs.
====================
Link: https://lore.kernel.org/r/20211216120507.3299-1-fw@strlen.de
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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Now that there is only one fib nla_policy there is no need to
keep the macro around. Place it where its used.
Signed-off-by: Florian Westphal <fw@strlen.de>
Reviewed-by: David Ahern <dsahern@kernel.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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The attributes are identical in all implementations so move the ipv4 one
into the core and remove the per-family nla policies.
Signed-off-by: Florian Westphal <fw@strlen.de>
Reviewed-by: David Ahern <dsahern@kernel.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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For the gdb command lx-dmesg, the entire descriptor, info, and text
data regions are read into memory before printing any records. For
large kernel log buffers, this not only causes a huge delay before
seeing any records, but it may also lead to python errors of too
much memory allocation.
Rather than reading in all these regions in advance, read them as
needed and only read the regions for the particular record that is
being printed.
The gdb macro "dmesg" in Documentation/admin-guide/kdump/gdbmacros.txt
already prints out the kernel log buffer like this.
Signed-off-by: John Ogness <john.ogness@linutronix.de>
Signed-off-by: Petr Mladek <pmladek@suse.com>
Link: https://lore.kernel.org/r/874k79c3a9.fsf@jogness.linutronix.de
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Add vdd core regulator (1.1 V).
This patch add regulator support for gpu.
The H/W manual mentions nothing about a gpu regulator. So using vdd
core regulator for gpu.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211208104026.421-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Add Mali-G31 GPU node to SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211208104026.421-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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