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2017-08-30mmc: sdhci: enable/disable the clock in sdhci_pltfm_suspend/resumeMasahiro Yamada
This commit provides similar cleanups as commit 83eacdfa2529 ("mmc: sdhci: disable the clock in sdhci_pltfm_unregister()") did for unregister hooks. sdhci-brcmstb.c and sdhci-sirf.c implement their own suspend/resume hooks to handle pltfm_host->clk. Move clock handling to sdhci_pltfm.c so that the drivers can reuse sdhci_pltfm_pmops. The following drivers did not previously touch pltfm_host->clk during suspend/resume, but now do: - sdhci-bcm-kona.c - sdhci-dove.c - sdhci-iproc.c - sdhci-pxav2.c - sdhci-tegra.c - sdhci-xenon.c Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Al Cooper <alcooperx@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: sdhci-pxav2: switch to managed clk and sdhci_pltfm_unregister()Masahiro Yamada
The difference between sdhci_pxav2_remove() and sdhci_pltfm_unregister() is clk_put(). It will go away by using the managed resource clk, then sdhci_pltfm_unregister() can be reused. Also, rename the jump labels to say what the goto does. (Coding style suggested by Documentation/process/coding-style.rst) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: sdhci-cadence: add suspend / resume supportMasahiro Yamada
Currently, the probe function initializes the PHY, but PHY settings are lost during the sleep state. Restore the PHY registers when resuming. To facilitate this, split sdhci_cdns_phy_init() into the DT parse part and PHY update part so that the latter can be invoked from the resume hook. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: sdhci-xenon: Support HS400 Enhanced Strobe featureHu Ziji
Support HS400 Enhanced Strobe feature in Xenon. Enable Enhanced Strobe together with Data Strobe. Disable Enhanced Strobe when eMMC is not in HS400 mode. Signed-off-by: Hu Ziji <huziji@marvell.com> Signed-off-by: Zhoujie Wu <zjwu@marvell.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: sdhci: Add quirk to indicate MMC_RSP_136 has CRCKishon Vijay Abraham I
TI's implementation of sdhci controller used in DRA7 SoC's has CRC in responses with length 136 bits. Add quirk to indicate the controller has CRC in MMC_RSP_136. If this quirk is set sdhci library shouldn't shift the response present in SDHCI_RESPONSE register. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: sdhci: Tidy reading 136-bit responsesAdrian Hunter
Read each register only once and move the code to a separate function so that it is not jammed against the 80 column margin. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: clean up some constantsJerome Brunet
Remove unused clock rate defines. These should not be defined but requested from the clock framework. Also correct typo on the DELAY register Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: remove CLK_DIVIDER_ALLOW_ZERO clock flagJerome Brunet
Remove CLK_DIVIDER_ALLOW_ZERO. This flag means that a 1 based divider with a 0 value will behave as a bypass clock The mmc divider does not behave like this, a 0 value disables the clock Remove this flag so CCF never allows a 0 value on this clock Fixes: 51c5d8447bd7 ("MMC: meson: initial support for GX platforms") Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: fix mux mask definitionJerome Brunet
CCF generic mux will shift the mask using the value defined in shift Define the mask accordingly Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: block: Reparametrize mmc_blk_ioctl_[multi]_cmd()Linus Walleij
Instead of passing a block device to mmc_blk_ioctl[_multi]_cmd(), let's pass struct mmc_blk_data() so we operate ioctl()s on the MMC block device representation rather than the vanilla block device. This saves a little duplicated code and makes it possible to issue ioctl()s not targeted for a specific block device but rather for a specific partition/area. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: block: Refactor mmc_blk_part_switch()Linus Walleij
Instead of passing a struct mmc_blk_data * to mmc_blk_part_switch() let's pass the actual partition type we want to switch to. This is necessary in order not to have a block device with a backing mmc_blk_data and request queue and all for every hardware partition, such as RPMB. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: block: Move duplicate checkLinus Walleij
mmc_blk_ioctl() calls either mmc_blk_ioctl_cmd() or mmc_blk_ioctl_multi_cmd() and each of these make the same check. Factor it into a new helper function, call it on both branches of the switch() statement and save a chunk of duplicate code. Cc: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: debugfs: Move block debugfs into block moduleLinus Walleij
If we don't have the block layer enabled, we do not present card status and extcsd in the debugfs. Debugfs is not ABI, and maintaining files of no relevance for non-block devices comes at a high maintenance cost if we shall support it with the block layer compiled out. The debugfs entries suffer from all the same starvation issues as the other userspace things, under e.g. a heavy dd operation. The expected number of debugfs users utilizing these two debugfs files is already low as there is an ioctl() to get the same information using the mmc-tools, and of these few users the expected number of people using it on SDIO or combo cards are expected to be zero. It is therefore logical to move this over to the block layer when it is enabled, using the new custom requests and issue it using the block request queue. On the other hand it moves some debugfs code from debugfs.c and into block.c. Tested during heavy dd load by cat:in the status file. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: ops: export mmc_get_status()Linus Walleij
This function retrieves the status of the card with the default number of retries. Since the block layer wants to use this, and since the block layer is a loadable kernel module, we need to export this symbol. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: block: Anonymize the drv op data pointerLinus Walleij
We have a data pointer for the ioctl() data, but we need to pass other data along with the DRV_OP:s, so make this a void * so it can be reused. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: cavium-octeon: Convert to use module_platform_driverAxel Lin
Get rid of boilerplate code by using module_platform_driver macro. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30dt-bindings: mmc: sh_mmcif: Document r8a7745 DT bindingsFabrizio Castro
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Chris Paterson <chris.paterson2@renesas.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: test: reduce stack usage in mmc_test_nonblock_transferArnd Bergmann
The new lockdep annotations for completions cause a warning in the mmc test module, in a function that now has four 150 byte structures on the stack: drivers/mmc/core/mmc_test.c: In function 'mmc_test_nonblock_transfer.constprop': drivers/mmc/core/mmc_test.c:892:1: error: the frame size of 1360 bytes is larger than 1024 bytes [-Werror=frame-larger-than=] The mmc_test_ongoing_transfer function evidently had a similar problem, and worked around it by using dynamic allocation. This generalizes the approach used by mmc_test_ongoing_transfer() and applies it to mmc_test_nonblock_transfer() as well. Fixes: cd8084f91c02 ("locking/lockdep: Apply crossrelease to completions") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Tested-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: sdhci-of-esdhc: support ESDHC_CAPABILITIES_1 accessingyangbo lu
eSDHC is not a standard SD host controller. SDHCI_CAPABILITIES_1 register address is 0x44 while it's 0x114 (ESDHC_CAPABILITIES_1) for eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: sdhci: fix SDHCI_QUIRK_NO_HISPD_BIT handlingyangbo lu
SD controller with SDHCI_QUIRK_NO_HISPD_BIT quirk probably use high speed enable bit for other purpose. So this bit shouldn't be changed for high speed enabling for this type of SD controller. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: sdhci-s3c: use generic sdhci_set_bus_width()Michał Mirosław
Now that sdhci_set_bus_width() supports 8-bit bus widths based on the MMC_CAP_8_BIT_DATA capability flag, replace the sdhci-s3c version with the generic sdhci version. Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: sdhci-pci: use generic sdhci_set_bus_width()Michał Mirosław
Now that sdhci_set_bus_width() supports 8-bit bus widths based on the MMC_CAP_8_BIT_DATA capability flag, replace the sdhci-pci version with the generic sdhci version. Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: sdhci-tegra: use generic sdhci_set_bus_width()Michał Mirosław
Now that sdhci_set_bus_width() supports 8-bit bus widths based on the MMC_CAP_8_BIT_DATA capability flag, replace the tegra version with the generic sdhci version. Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: sdhci: key 8BITBUS bit off MMC_CAP_8_BIT_DATAMichał Mirosław
Hosts supporting 8-bit bus are marked accordingly. If MMC_CAP_8_BIT_DATA is not among host capabilities, 8BITBUS bit will never be set and it is not cleared in case some non-SDHCI3 host uses it for something else. Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: renesas_sdhi: Add r8a7743/5 supportBiju Das
Add support for r8a7743/5 SoC. Renesas RZ/G1[ME] (R8A7743/5) SDHI is identical to the R-Car Gen2 family. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: core: Turn off CQE before sending commandsAdrian Hunter
CQE needs to be off for the host controller to accept non-CQ commands. Turn off the CQE before sending commands, and ensure it is off in any reset or power management paths, or re-tuning. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: host: Add CQE interfaceAdrian Hunter
Add CQE host operations, capabilities, and host members. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30perf report: Calculate the average cycles of iterationsJin Yao
The branch history code has a loop detection function. With this, we can get the number of iterations by calculating the removed loops. While it would be nice for knowing the average cycles of iterations. This patch adds up the cycles in branch entries of removed loops and save the result to the next branch entry (e.g. branch entry A). Finally it will display the iteration number and average cycles at the "from" of branch entry A. For example: perf record -g -j any,save_type ./div perf report --branch-history --no-children --stdio --22.63%--main div.c:42 (RET CROSS_2M) compute_flag div.c:28 (cycles:2 iter:173115 avg_cycles:2) | --10.73%--compute_flag div.c:27 (RET CROSS_2M) rand rand.c:28 (cycles:1) rand rand.c:28 (RET CROSS_2M) __random random.c:298 (cycles:1) __random random.c:297 (COND_BWD CROSS_2M) __random random.c:295 (cycles:1) __random random.c:295 (COND_BWD CROSS_2M) __random random.c:295 (cycles:1) __random random.c:295 (RET CROSS_2M) Signed-off-by: Yao Jin <yao.jin@linux.intel.com> Reviewed-by: Andi Kleen <ak@linux.intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kan Liang <kan.liang@intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Link: http://lkml.kernel.org/r/1502111115-18305-1-git-send-email-yao.jin@linux.intel.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2017-08-30nvme: Use metadata for passthrough commandsKeith Busch
The ioctls' struct allows the user to provide a metadata address and length for a passthrough command. This patch uses these values that were previously ignored and deletes the now unused wrapper function. Signed-off-by: Keith Busch <keith.busch@intel.com> Reviewed-by: Sagi Grimberg <sagi@grimberg.me> Reviewed-by: Max Gurtovoy <maxg@mellanox.com> Signed-off-by: Christoph Hellwig <hch@lst.de>
2017-08-30nvme: Make nvme user functions staticKeith Busch
These functions are used only locally in the nvme core. Signed-off-by: Keith Busch <keith.busch@intel.com> Reviewed-by: Sagi Grimberg <sagi@grimberg.me> Reviewed-by: Max Gurtovoy <maxg@mellanox.com> Signed-off-by: Christoph Hellwig <hch@lst.de>
2017-08-30nvme/pci: Use req_op to determine DIF remappingKeith Busch
Only read and write commands need DIF remapping. Everything else uses a passthrough integrity payload. Signed-off-by: Keith Busch <keith.busch@intel.com> Reviewed-by: Sagi Grimberg <sagi@grimberg.me> Reviewed-by: Max Gurtovoy <maxg@mellanox.com> Signed-off-by: Christoph Hellwig <hch@lst.de>
2017-08-30nvme: factor metadata handling out of __nvme_submit_user_cmdChristoph Hellwig
Keep the metadata code in a separate helper instead of making the main function more complicated. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Sagi Grimberg <sagi@grimberg.me> Reviewed-by: Max Gurtovoy <maxg@mellanox.com> Signed-off-by: Christoph Hellwig <hch@lst.de>
2017-08-30nvme-fabrics: Convert nvmf_transports_mutex to an rwsemRoland Dreier
The mutex protects against the list of transports changing while a controller is being created, but using a plain old mutex means that it also serializes controller creation. This unnecessarily slows down creating multiple controllers - for example for the RDMA transport, creating a controller involves establishing one connection for every IO queue, which involves even more network/software round trips, so the delay can become significant. The simplest way to fix this is to change the mutex to an rwsem and only hold it for writing when the list is being mutated. Since we can take the rwsem for reading while creating a controller, we can create multiple controllers in parallel. Signed-off-by: Roland Dreier <roland@purestorage.com> Reviewed-by: Sagi Grimberg <sagi@grimberg.me> Signed-off-by: Christoph Hellwig <hch@lst.de>
2017-08-30nvme: fix the definition of the doorbell buffer config support bitChangpeng Liu
NVMe 1.3 specification defines the Optional Admin Command Support feature flags, bit 8 set to '1' then the controller supports the Doorbell Buffer Config command. Bit 7 is used for Virtualization Mangement command. Signed-off-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-by: Sagi Grimberg <sagi@grimberg.me> Reviewed-by: Max Gurtovoy <maxg@mellanox.com> Reviewed-by: Johannes Thumshirn <jthumshirn@suse.de> Signed-off-by: Christoph Hellwig <hch@lst.de> Fixes: f9f38e33 ("nvme: improve performance for virtual NVMe devices") Cc: stable@vger.kernel.org
2017-08-30nvme-pci: use dma memory for the host memory buffer descriptorsChristoph Hellwig
The NVMe 1.3 specification says in section 5.21.1.13: "After a successful completion of a Set Features enabling the host memory buffer, the host shall not write to the associated host memory region, buffer size, or descriptor list until the host memory buffer has been disabled." While this doesn't state that the descriptor list must remain accessible to the device it certainly implies it must remaing readable by the device. So switch to a dma coherent allocation for the descriptor list just to be safe - it's not like the cost for it matters compared to the actual memory buffers. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Keith Busch <keith.busch@intel.com> Reviewed-by: Sagi Grimberg <sagi@grimberg.me> Reviewed-by: Johannes Thumshirn <jthumshirn@suse.de> Fixes: 87ad72a59a38 ("nvme-pci: implement host memory buffer support")
2017-08-30nvme-rdma: default MR page size to 4kMax Gurtovoy
Due to various page sizes in the system (IOMMU/device/kernel), we set the fabrics controller page size to 4k and block layer boundaries accordinglly. In architectures that uses different kernel page size we'll have a mismatch to the MR page size that may cause a mapping error. Update the MR page size to correspond to the core ctrl settings. Signed-off-by: Max Gurtovoy <maxg@mellanox.com> Reviewed-by: Sagi Grimberg <sagi@grimberg.me> Signed-off-by: Christoph Hellwig <hch@lst.de>
2017-08-30efi: switch to use new generic UUID APIAndy Shevchenko
There are new types and helpers that are supposed to be used in new code. As a preparation to get rid of legacy types and API functions do the conversion here. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Christoph Hellwig <hch@lst.de>
2017-08-30clocksource: mips-gic-timer: Use new GIC accessor functionsPaul Burton
Switch from calling functions exported by the GIC interrupt controller to using new accessors provided by asm/mips-gic.h. This will allow the counter-handling functionality to be removed from the interrupt controller driver, where it doesn't really belong, and also allow for inlining of the accesses to the GIC. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17021/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30mmc: sdhci-xenon: add set_power callbackZhoujie Wu
Xenon sdh controller requests proper SD bus voltage select bits programmed even with vmmc power supply. Any reserved value(100b-000b) programmed in this field will lead to controller ignore SD bus power bit and keep its value at zero. Add set_power callback to handle this. Signed-off-by: Zhoujie Wu <zjwu@marvell.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Fixes: 3a3748dba881 ("mmc: sdhci-xenon: Add Marvell Xenon SDHC core functionality") Cc: <stable@vger.kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30MIPS: GIC: Introduce asm/mips-gic.h with accessor functionsPaul Burton
This patch introduces a new header providing accessor functions for the MIPS Global Interrupt Controller (GIC) mirroring those provided for the other 2 components of the MIPS Coherent Processing System (CPS) - the Coherence Manager (CM) & Cluster Power Controller (CPC). This header makes use of the new standardised CPS accessor macros where possible, but does require some custom accessors for cases where we have either a bit or a register per interrupt. A major advantage of this over the existing include/linux/irqchip/mips-gic.h definitions is that code performing accesses can become much simpler, for example this: gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_TRIGGER) + GIC_INTR_OFS(intr), 1ul << GIC_INTR_BIT(intr), (unsigned long)trig << GIC_INTR_BIT(intr)); ...can become simply: change_gic_trig(intr, trig); The accessors handle 32 vs 64 bit in the same way as for CM & CPC code, which means that GIC code will also not need to worry about the access size in most cases. They are also accessible outside of drivers/irqchip/irq-mips-gic.c which will allow for simplification in the use of the non-interrupt portions of the GIC (eg. counters) which currently require the interrupt controller driver to expose helper functions for access. This patch doesn't change any existing code over to use the new accessors yet, since a wholesale change would be invasive & difficult to review. Instead follow-on patches will convert code piecemeal to use this new header. The one change to existing code is to rename gic_base to mips_gic_base & make it global, in order to fit in with the naming expected by the standardised CPS accessor macros. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17020/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-30mmc: core: Add members to mmc_request and mmc_data for CQE'sAdrian Hunter
Most of the information needed to issue requests to a CQE is already in struct mmc_request and struct mmc_data. Add data block address, some flags, and the task id (tag), and allow for cmd being NULL which it is for CQE tasks. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: core: Add mmc_retune_hold_now()Adrian Hunter
mmc_return_hold() / mmc_retune_release() are used around a group of commands to prevent re-tuning between the commands. Re-tuning can still happen before the first command. In some cases, re-tuning must be prevented entirely. Add mmc_retune_hold_now() for that purpose. It is added in preparation for CQE support where it will be used by CQE recovery. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: core: Remove unused MMC_CAP2_PACKED_CMDAdrian Hunter
Packed commands support was removed but some bits got left behind. Remove them. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: sunxi: Fix clock rate passed to sunxi_mmc_clk_set_phaseChen-Yu Tsai
sunxi_mmc_clk_set_phase expects the actual card clock rate to be passed to it. When the internal divider code was reworked in change ("mmc: sunxi: Support MMC DDR52 transfer mode with new timing mode"), this requirement was missed, and the module clock rate was passed in instead. This broke 8 bit DDR MMC on old controllers, as the module clock rate is double the card clock rate, for which we have no valid delay settings. Fix this by applying the internal divider to the clock rate right after we configure it in hardware. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: sdhi: use maximum width for the sdbuf registerWolfram Sang
Make use of the 64 bit sdbuf width on Renesas R-Car Gen3. If the registers are 8 byte apart, the width is also 64 bit. For all others, the width is 32 bit, even if the registers are only 16 bit apart. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: renesas_sdhi: document version of RZ/A1 instanceWolfram Sang
We don't use this new define yet, but it is helpful to document which versions we know of. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Chris Brandt <Chris.Brandt@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: renesas_sdhi: enably CBSY bit for RZ platformWolfram Sang
It is documented, so enable it to follow the recommendation in the docs and also save a few cycles. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Chris Brandt <Chris.Brandt@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: renesas_sdhi: use extra flag for CBSY usageWolfram Sang
There is one SDHI instance on Gen2 which does not have the CBSY bit. So, turn CBSY usage into an extra flag and set it accordingly. This has the additional advantage that we can also set it for other incarnations later. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Chris Brandt <Chris.Brandt@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: vub300: constify usb_device_idArvind Yadav
usb_device_id are not supposed to change at runtime. All functions working with usb_device_id provided by <linux/usb.h> work with const usb_device_id. So mark the non-const structs as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: sdhci-xenon: Add Xenon SDHCI specific system-level PM supportHu Ziji
Add Xenon specific system-level suspend and resume support. Especially during resume, re-configure Xenon specific registers since registers setting will be lost in suspend if Xenon is power off. Signed-off-by: Hu Ziji <huziji@marvell.com> Signed-off-by: Zhoujie Wu <zjwu@marvell.com> Tested-by: Jisheng Zhang <jszhang@marvell.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
generated by cgit (git 2.34.1) at 2025-09-23 10:08:23 +0000