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2021-12-31net: hns3: refactor PF cmdq init and uninit APIs with new common APIsJie Wang
This patch uses common cmdq init and uninit APIs to replace the old APIs in PF cmdq module init and uninit modules. Then the old PF init and uninit APIs is deleted. Signed-off-by: Jie Wang <wangjie125@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-31net: hns3: create common cmdq init and uninit APIsJie Wang
The PF and VF cmdq init and uninit APIs are also almost same espect the suffixes of API names. This patch creates common cmdq init and uninit APIs needed by PF and VF cmdq modules. The next patch will use the new unified APIs to replace init and uninit APIs in PF module. Signed-off-by: Jie Wang <wangjie125@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-31net: hns3: refactor VF cmdq resource APIs with new common APIsJie Wang
This patch uses common cmdq resource allocate/free/query APIs to replace the old APIs in VF cmdq module and deletes the old cmdq resource APIs. Still we kept hclgevf_cmd_setup_basic_desc name as a seam API to avoid too many meaningless replacement. Signed-off-by: Jie Wang <wangjie125@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-31net: hns3: refactor PF cmdq resource APIs with new common APIsJie Wang
This patch uses common cmdq resource allocate/free/query APIs to replace the old APIs in PF cmdq module and deletes the old cmdq resource APIs. Still we kept hclge_cmd_setup_basic_desc name as a seam API to avoid too many meaningless replacement. Signed-off-by: Jie Wang <wangjie125@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-31net: hns3: create common cmdq resource allocate/free/query APIsJie Wang
The PF and VF cmdq module resource allocate/free/query APIs are almost the same espect the suffixes of API names. These same implementations bring double development and bugfix work. This patch creates common cmdq resource allocate/free/query APIs called by PF and VF cmdq init/uninit APIs. The next patch will use the new unified APIs to replace init/uninit APIs. Signed-off-by: Jie Wang <wangjie125@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-31net: hns3: refactor hclgevf_cmd_send with new hclge_comm_cmd_send APIJie Wang
This patch firstly uses new hardware description struct hclge_comm_hw as child member of hclgevf_hw and deletes the old hardware description child members. All the hclgevf_hw variables used in VF module is modified according to the new hclgevf_hw. Secondly hclgevf_cmd_send is refactored to use hclge_comm_cmd_send APIs. The old functions called by hclgevf_cmd_send are all deleted. Still we kept hclgevf_cmd_send to avoid too many meaningless modifications. Signed-off-by: Jie Wang <wangjie125@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-31net: hns3: refactor hclge_cmd_send with new hclge_comm_cmd_send APIJie Wang
This patch firstly uses new hardware description struct hclge_comm_hw as child member of hclge_hw and deletes the original child memebers of hclge_hw. All the hclge_hw variables used in PF module is modified according to the new hclge_hw. Secondly hclge_cmd_send is refactored to use hclge_comm_cmd_send APIs. The old functions called by hclge_cmd_send are deleted and hclge_cmd_send is kept to avoid too many meaningless modifications. Signed-off-by: Jie Wang <wangjie125@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-31net: hns3: create new set of unified hclge_comm_cmd_send APIsJie Wang
This patch create new set of unified hclge_comm_cmd_send APIs for PF and VF cmdq module. Subfunctions called by hclge_comm_cmd_send are also created include cmdq result check, cmdq return code conversion and ring space opertaion APIs. These new common cmdq APIs will be used to replace the old PF and VF cmdq APIs in next patches. Signed-off-by: Jie Wang <wangjie125@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-31net: hns3: use struct hclge_desc to replace hclgevf_desc in VF cmdq moduleJie Wang
This patch use new common struct hclge_desc to replace struct hclgevf_desc in VF cmdq module and then delete the old struct hclgevf_desc. Signed-off-by: Jie Wang <wangjie125@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-31net: hns3: create new cmdq hardware description structure hclge_comm_hwJie Wang
Currently PF and VF cmdq APIs use struct hclge(vf)_hw to describe cmdq hardware information needed by hclge(vf)_cmd_send. There are a little differences between its child struct hclge_cmq_ring and hclgevf_cmq_ring. It is redundent to use two sets of structures to support same functions. So this patch creates new set of common cmdq hardware description structures(hclge_comm_hw) to unify PF and VF cmdq functions. The struct hclge_desc is still kept to avoid too many meaningless replacement. These new structures will be used to unify hclge(vf)_hw structures in PF and VF cmdq APIs in next patches. Signed-off-by: Jie Wang <wangjie125@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-31net: hns3: refactor hns3 makefile to support hns3_common moduleJie Wang
Currently we plan to refactor PF and VF cmdq module. A new file folder hns3_common will be created to store new common APIs used by PF and VF cmdq module. Thus the PF and VF compilation process will both depends on the hns3_common. This may cause parallel building problems if we add a new makefile building unit. So this patch combined the PF and VF makefile scripts to the top level makefile to support the new hns3_common which will be created in the next patch. Signed-off-by: Jie Wang <wangjie125@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-31drm/amdgpu: disable runpm if we are the primary adapterAlex Deucher
If we are the primary adapter (i.e., the one used by the firwmare framebuffer), disable runtime pm. This fixes a regression caused by commit 55285e21f045 which results in the displays waking up shortly after they go to sleep due to the device coming out of runtime suspend and sending a hotplug uevent. v2: squash in reworked fix from Evan Fixes: 55285e21f045 ("fbdev/efifb: Release PCI device's runtime PM ref during FB destroy") Bug: https://bugzilla.kernel.org/show_bug.cgi?id=215203 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1840 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-31fbdev: fbmem: add a helper to determine if an aperture is used by a fw fbAlex Deucher
Add a function for drivers to check if the a firmware initialized fb is corresponds to their aperture. This allows drivers to check if the device corresponds to what the firmware set up as the display device. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=215203 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1840 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-31drm/amd/pm: keep the BACO feature enabled for suspendEvan Quan
To pair with the workaround which always reset the ASIC in suspend. Otherwise, the reset which relies on BACO will fail. Fixes: daf8de0874ab5b ("drm/amdgpu: always reset the asic in suspend (v2)") Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-31Docs: Fixes link to I2C specificationDeep Majumder
The link to the I2C specification is broken. Although "https://www.nxp.com" hosts Rev 7 (2021) of this specification, it is behind a login-wall. Thus, an additional link has been added (which doesn't require a login) and the NXP official docs link has been updated. Signed-off-by: Deep Majumder <deep@fastmail.in> [wsa: minor updates to text and commit message] Signed-off-by: Wolfram Sang <wsa@kernel.org>
2021-12-31i2c: validate user data in compat ioctlPavel Skripkin
Wrong user data may cause warning in i2c_transfer(), ex: zero msgs. Userspace should not be able to trigger warnings, so this patch adds validation checks for user data in compact ioctl to prevent reported warnings Reported-and-tested-by: syzbot+e417648b303855b91d8a@syzkaller.appspotmail.com Fixes: 7d5cb45655f2 ("i2c compat ioctls: move to ->compat_ioctl()") Signed-off-by: Pavel Skripkin <paskripkin@gmail.com> Signed-off-by: Wolfram Sang <wsa@kernel.org>
2021-12-31ASoC: Merge fixesMark Brown
So we can send to Linus.
2021-12-31ASoC: cs35l41: Create shared function for boost configurationLucas Tanure
ASoC and HDA will use the same registers to configure internal boost for the device Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Link: https://lore.kernel.org/r/20211217115708.882525-7-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-12-31ASoC: cs35l41: Create shared function for setting channelsLucas Tanure
ASoC and HDA will use the same register to set channels for the device Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Link: https://lore.kernel.org/r/20211217115708.882525-6-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-12-31ASoC: cs35l41: Create shared function for errata patchesLucas Tanure
ASoC and HDA systems require the same errata patches, so move it to the shared code using a function the correctly applies the patches by revision Also, move CS35L41_DSP1_CCM_CORE_CTRL write to errata patch function as is required to be written at boot, but not in regmap_register_patch sequence as will affect waking up from hibernation Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Link: https://lore.kernel.org/r/20211217115708.882525-5-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-12-31ASoC: cs35l41: Move power initializations to reg_sequenceLucas Tanure
ASoC and HDA systems for all revisions of CS35L41 will benefit from having this initialization, so add it to reg_sequence of each revision By moving to reg_sequence all gains are set to zero. And boost, monitoring parts, and class D amplifier are disabled. Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Link: https://lore.kernel.org/r/20211217115708.882525-4-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-12-31ASoC: cs35l41: Move cs35l41_otp_unpack to shared codeLucas Tanure
ASoC and HDA will do the same cs35l41_otp_unpack, so move it to shared code Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Link: https://lore.kernel.org/r/20211217115708.882525-3-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-12-31ASoC: cs35l41: Convert tables to shared source codeLucas Tanure
To support CS35L41 in HDA systems the HDA driver for CS35L41 would have to duplicate some functions that already exist on ASoC driver So instead of duplicate the code, use the new lib source as a shared resource for both ASoC and HDA Also, change the way CONFIG_SND_SOC_CS35L41 is selected, as reported by Intel Kernel test robot, it is possible to build SND_SOC_CS35L41_SPI/I2C without the main driver, which would lead to build failures. Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Reported-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/r/20211217115708.882525-2-tanureal@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-12-31ASoC: mediatek: mt8195: add playback support to PCM1_BE dai_linkTrevor Wu
PCM1_BE should be a dai_link for both playback and capture. In the patch, the missing DPCM playback support is added. Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> Link: https://lore.kernel.org/r/20211230084731.31372-3-trevor.wu@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-12-31ASoC: mediatek: mt8195: correct pcmif BE dai control flowTrevor Wu
Originally, the conditions for preventing reentry are not correct. dai->component->active is not the state specifically for pcmif dai, so it is not a correct condition to indicate the status of pcmif dai. On the other hand, snd_soc_dai_stream_actvie() in prepare ops for both playback and capture possibly return true at the first entry when these two streams are opened at the same time. In the patch, I refer to the implementation in mt8192-dai-pcm.c. Clock and enabling bit for PCMIF are managed by DAPM, and the condition for prepare ops is replaced by the status of dai widget. Fixes: 1f95c019115c ("ASoC: mediatek: mt8195: support pcm in platform driver") Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> Link: https://lore.kernel.org/r/20211230084731.31372-2-trevor.wu@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-12-31Revert "serdev: BREAK/FRAME/PARITY/OVERRUN notification prototype V2"Greg Kroah-Hartman
This reverts commit d8e9a406a931f687945703a4bac45042eb81ce92. It needs some future changes as pointed out by Johan and is not ready to be merged just yet. Reported-by: Johan Hovold <johan@kernel.org> Cc: Magnus Damm <damm+renesas@opensource.se> Link: https://lore.kernel.org/r/Yc7oZ/1tu95Z4wPS@hovoldconsulting.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-12-31Merge tag 'nand/for-5.17' into mtd/nextMiquel Raynal
Raw NAND core: * Export nand_read_page_hwecc_oob_first() GPMC memory controller for OMAP2 NAND controller: * GPMC: - Add support for AM64 SoC and allow build on K3 platforms - Use a compatible match table when checking for NAND controller - Use platform_get_irq() to get the interrupt Raw NAND controller drivers: * OMAP2 NAND controller: - Document the missing 'rb-gpios' DT property - Drop unused variable - Fix force_8bit flag behaviour for DMA mode - Move to exec_op interface - Use platform_get_irq() to get the interrupt * Renesas: - Add new NAND controller driver with its bindings and MAINTAINERS entry * Onenand: - Remove redundant variable ooblen * MPC5121: - Remove unused variable in ads5121_select_chip() * GPMI: - Add ERR007117 protection for nfc_apply_timings - Remove explicit default gpmi clock setting for i.MX6 - Use platform_get_irq_byname() to get the interrupt - Remove unneeded variable * Ingenic: - JZ4740 needs 'oob_first' read page function * Davinci: - Rewrite function description - Avoid duplicated page read - Don't calculate ECC when reading page Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2021-12-31Merge tag 'spi-nor/for-5.17' into mtd/nextMiquel Raynal
SPI NOR core changes: - Add Pratyush as SPI NOR co-maintainer. - Flash parameters initialization was done in a spaghetti way. Clean flash parameters initialization. - Rework the flash_info flags and clarify where one should be used. - Initialize all flash parameters based on JESD216 SFDP where possible. Flash parameters and settings that are SFDP discoverable should not be duplicated via flash_info flags at flash declaration. - Remove debugfs entries that duplicate sysfs entries. SPI NOR manufacturer drivers changes: - Use late_init() hook in various drivers to make it clear that those flash parameters are either not declared in the JESD216 SFDP standard, or the SFDP tables which define those flash parameters are not defined by the flash. - Fix mtd size for s3an flashes. - Write 2 bytes when disabling Octal DTR mode: 1 byte long transactions are not allowed in 8D-8D-8D mode. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2021-12-31Merge tag 'cfi/for-5.17' into mtd/nextMiquel Raynal
Hyperbus changes for v5.17-rc1 Hyperbus changes: Couple of fixes in Renesas hyperbus rpc-if driver to avoid crash on module remove and for missing check for error value in probe. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2021-12-31Merge tag 'memory-controller-drv-omap-5.17' into nand/nextMiquel Raynal
Memory controller drivers for v5.17 - OMAP GPMC 1. Add support for AM64 SoC. 2. Minor improvement: use platform_get_irq(). [miquel.raynal@bootlin.com: A first commit introduced a new omap compatible and another moved the IDs to a header which created a conflict: moving the new ID as well in the header fixed it.] Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2021-12-31net/mlx5: Set SMFS as a default steering mode if device supports itYevgeny Kliteynik
Set SMFS (SW-managed flow steering) as a default steering mode instead of DMFS (device-managed flow steering) In SMFS, the driver writes the STEs (Steering Table Entries) directly to the device's ICM, which allows for a higher rule insertion rate than through using FW command interface, as it is done in DMFS. SMFS/DMFS steering modes can be configured through devlink param 'flow_steering_mode'. The possible values are 'smfs' or 'dmfs'. The desired 'flow_steering_mode' param value should be set before enabling switchdev mode. Example: # devlink dev param set pci/0000:05:00.0 name flow_steering_mode smfs # devlink dev eswitch set pci/0000:05:00.0 mode switchdev Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Ignore modify TTL if device doesn't support itYevgeny Kliteynik
When modifying TTL, packet's csum has to be recalculated. Due to HW issue in ConnectX-5, csum recalculation for modify TTL is supported through a work-around that is specifically enabled by configuration. If the work-around isn't enabled, ignore the modify TTL action rather than adding an unsupported action. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Improve steering for empty or RX/TX-only matchersYevgeny Kliteynik
Every matcher has RX and TX paths. When a new matcher is created, its RX and TX start/end anchors are connected to the respective RX and TX anchors of the previous and next matchers. This creates a potential performance issue: when a certain rule is added to a matcher, in many cases it is RX or TX only rule, which may create a long chain of RX/TX-only paths w/o the actual rules. This patch aims to handle this issue. RX and TX matchers are now handled separately: matcher connection in the matchers chain is split into two separate lists: RX only and TX only. when a new matcher is created, it is initially created 'detached' - its RX/TX members are not inserted into the table's matcher list. When an actual rule is added, only its appropriate RX or TX nic matchers are then added to the table's nic matchers list and inserted into its place in the chain of matchers. I.e., if the rule that is being added is an RX-only rule, only the RX part of the matcher will be connected to the chain, while TX part of the matcher remains detached and doesn't prolong the TX chain of the matchers. Same goes for rule deletion: when the last RX/TX rule of the nic matcher is destroyed, the nic matcher is removed from its list. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Add support for matching on geneve_tlv_option_0_exist fieldYevgeny Kliteynik
Match on geneve_tlv_option_0_exist field on devices that support STEv1. Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Support matching on tunnel headers 0 and 1Muhammad Sammar
Tunnel headers are generic encapsulation headers, applies for all tunneling protocols identified by the device native parser or by the programmable parser, this support will enable raw matching headers 0 and 1. Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Add misc5 to match_param structsMuhammad Sammar
Add misc5 match params to enable matching tunnel headers. Signed-off-by: Muhammad Sammar <muhammads@nvidia.com>
2021-12-31net/mlx5: Add misc5 flow table match parametersMuhammad Sammar
Add support for misc5 match parameter as per HW spec, this will allow matching on tunnel_header fields. Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Warn on failure to destroy objects due to refcountYevgeny Kliteynik
Add WARN_ON_ONCE on refcount checks in SW steering object destructors Signed-off-by: Paul Blakey <paulb@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Add support for UPLINK destination typeYevgeny Kliteynik
Add support for a new destination type - UPLINK. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Add support for dumping steering infoMuhammad Sammar
Extend mlx5 debugfs support to present Software Steering resources: dr_domain including it's tables, matchers and rules. The interface is read-only. While dump is being presented, new steering rules cannot be inserted/deleted. The steering information is dumped in the CSV form with the following format: <object_type>,<object_ID>, <object_info>,...,<object_info> This data can be read at the following path: /sys/kernel/debug/mlx5/<BDF>/steering/fdb/<domain_handle> Example: # cat /sys/kernel/debug/mlx5/0000:82:00.0/steering/fdb/dmn_000018644 3100,0x55caa4621c50,0xee802,4,65533 3101,0x55caa4621c50,0xe0100008 Changes in V2: - Reduce temp hex buffer size and avoid unnecessary memset - Use bin2hex() instead of DIY loop - Don't check debugfs functions return values Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Add missing reserved fields to dr_match_paramMuhammad Sammar
Add the reserved fields to dr_match_param and arrange as mlx5_ifc_dr_match_param_bits. Signed-off-by: Muhammad Sammar <muhammads@nvidia.com>
2021-12-31net/mlx5: DR, Add check for flex parser ID valueYevgeny Kliteynik
Allow only legal values for flex parser ID - values from 0 to 7. For other values skip the parser, and as a result the matcher creation will fail for using invalid flex parser ID. Signed-off-by: Hamdan Igbaria <hamdani@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Rename list field in matcher struct to list_nodeYevgeny Kliteynik
In dr_types structs, some list fields are list heads, and some are just list nodes that are stored on the other structs' lists. Rename the appropriate list field to reflect this distinction. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Remove unused struct member in matcherYevgeny Kliteynik
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Fix lower case macro prefix "mlx5_" to "MLX5_"Yevgeny Kliteynik
Macros prefix should be capital letters - fix the prefix in mlx5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31net/mlx5: DR, Fix error flow in creating matcherYevgeny Kliteynik
The error code of nic matcher init functions wasn't checked. This patch improves the matcher init function and fix error flow bug: the handling of match parameter is moved into a separate function and error flow is simplified. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
2021-12-31crypto: qat - fix definition of ring reset resultsGiovanni Cabiddu
The ring reset result values are defined starting from 0x1 instead of 0. This causes out-of-tree drivers that support this message to understand that a ring reset failed even if the operation was successful. Fix by starting the definition of ring reset result values from 0. Fixes: 0bba03ce9739 ("crypto: qat - add PFVF support to enable the reset of ring pairs") Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reported-by: Adam Guerin <adam.guerin@intel.com> Reviewed-by: Marco Chiappero <marco.chiappero@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-12-31crypto: hisilicon - cleanup warning in qm_get_qos_value()Tom Rix
Building with clang static analysis returns this warning: qm.c:4382:11: warning: The left operand of '==' is a garbage value if (*val == 0 || *val > QM_QOS_MAX_VAL || ret) { ~~~~ ^ The call to qm_qos_value_init() can return an error without setting *val. So check ret before checking *val. Fixes: 72b010dc33b9 ("crypto: hisilicon/qm - supports writing QoS int the host") Signed-off-by: Tom Rix <trix@redhat.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-12-31crypto: kdf - select SHA-256 required for self-testStephan Müller
The self test of the KDF is based on SHA-256. Thus, this algorithm must be present as otherwise a warning is issued. Reported-by: kernel test robot <oliver.sang@intel.com> Signed-off-by: Stephan Mueller <smueller@chronox.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-12-31crypto: x86/aesni - don't require alignment of dataJakub Kicinski
x86 AES-NI routines can deal with unaligned data. Crypto context (key, iv etc.) have to be aligned but we take care of that separately by copying it onto the stack. We were feeding unaligned data into crypto routines up until commit 83c83e658863 ("crypto: aesni - refactor scatterlist processing") switched to use the full skcipher API which uses cra_alignmask to decide data alignment. This fixes 21% performance regression in kTLS. Tested by booting with CONFIG_CRYPTO_MANAGER_EXTRA_TESTS=y (and running thru various kTLS packets). CC: stable@vger.kernel.org # 5.15+ Fixes: 83c83e658863 ("crypto: aesni - refactor scatterlist processing") Signed-off-by: Jakub Kicinski <kuba@kernel.org> Acked-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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