summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2023-10-10arm64: dts: freescale: Add support for LX2162 SoM & Clearfog BoardJosua Mayer
Add support for the SolidRun LX2162A System on Module (SoM), and the Clearfog evaluation board. The SoM has few software-controllable features: - AR8035 Ethernet PHY - eMMC - SPI Flash - fan controller - various eeproms The Clearfog evaluation board provides: - microSD connector - USB-A - 2x 10Gbps SFP+ - 2x 25Gbps SFP+ with a retimer - 8x 2.5Gbps RJ45 - 2x mPCI (assembly option / disables 2xRJ45) The 8x RJ45 ports are connected with an 8-port PHY: Marvell 88E2580 supporting up to 5Gbps, while SoC and magnetics are limited to 2.5Gbps. However 2500 speed is untested due to documentation and drivier limitations. To avoid confusion the phy nodes have been explicitly limited to 1000 for now. The PCI nodes are disabled, but explicitly added to mark that this board can have pci. It is expected that the bootloader will patch the status property "okay" and disable 2x RJ45 ports, according to active serdes configuration. Signed-off-by: Josua Mayer <josua@solid-run.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: lx2160a: describe the SerDes block #2Josua Mayer
Add description for the LX2160A second SerDes block. It is functionally identical to the first one already added in commit 3cbe93a1f540 ("arch: arm64: dts: lx2160a: describe the SerDes block #1"). The SerDes driver currently updates the registers of all 8 lanes by default during probe. Because currently this driver only supports configuration of network protocols, this can lead to problems with certain configurations. Set status property to "disabled" by default so that existing boards are not impacted. Signed-off-by: Josua Mayer <josua@solid-run.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx93: update gpio nodePeng Fan
Per binding doc, i.MX93 GPIO supports two interrupts and one register base, compatible with i.MX8ULP. The current fsl,imx7ulp-gpio compatible could work for i.MX93 in gpio-vf610.c driver, it is based on the base address are splited into two with offset added in device tree node. Now following hardware design, using one register base in device tree node. This may break users who use compatible fsl,imx7ulp-gpio to enable i.MX93 GPIO. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8ulp: update gpio nodePeng Fan
The i.MX8ULP GPIO supports two interrupts and one register base, the current fsl,imx7ulp-gpio compatible could work for i.MX8ULP in gpio-vf610.c driver, it is based on the base address are splited into two with offset added in device tree node. Now following hardware design, using one register base in device tree node. This may break users who use compatible fsl,imx7ulp-gpio to enable i.MX8ULP GPIO. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8mq-librem5: Fix tps65132 compatibleFabio Estevam
The valid compatible string for the tps65132 regulator is "ti,tps65132". Change it. Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8mp-debix-model-a: Remove USB hub reset-gpiosFabio Estevam
The SAI2_TXC pin is left unconnected per the imx8mp-debix-model-a schematics: https://debix.io/Uploads/Temp/file/20230331/DEBIX%20Model%20A%20Schematics.pdf Also, the RTS5411E USB hub chip does not have a reset pin. Remove this pin description to properly describe the hardware. This also fixes the following schema warning: hub@1: 'reset-gpios' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/usb/realtek,rts5411.yaml# Fixes: 0253e1cb6300 ("arm64: dts: imx8mp-debix: add USB host support") Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8-apalis-v1.1: Fix Ethernet PHY reset-namesFabio Estevam
Per ethernet-phy.yaml, the expected value for the 'reset-names' property is "phy". Change it accordingly to fix the following schema warning: imx8qm-apalis-ixora-v1.1.dtb: ethernet-phy@7: reset-names:0: 'phy' was expected from schema $id: http://devicetree.org/schemas/net/ethernet-phy.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8mm-venice-gw790: Remove phy-mode from switch nodeFabio Estevam
Per microchip,ksz.yaml, phy-mode is not a valid property in the top-level switch node. phy-mode = "rgmii-id" is already passed in the CPU port switch (port@5). Remove it from the top-level switch node to fix the following schema warning: switch@5f: Unevaluated properties are not allowed ('phy-mode' was unexpected) from schema $id: http://devicetree.org/schemas/net/dsa/microchip,ksz.yaml Signed-off-by: Fabio Estevam <festevam@denx.de> Acked-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8mp-venice-gw73xx: add TPM deviceTim Harvey
Add the TPM device found on the GW73xx revision F PCB. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8mm-venice-gw73xx: add TPM deviceTim Harvey
Add the TPM device found on the GW73xx revision F PCB. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8mp-verdin: Remove invalid property from eqosFabio Estevam
Per nxp,dwmac-imx.yaml, it is not valid to pass 'phy-supply'. The reg_module_eth1phy regulator is marked with 'regulator-always-on', so it is safe to remove it from the eqos node. Remove it to fix the following schema warning: imx8mp-verdin-nonwifi-dahlia.dtb: ethernet@30bf0000: Unevaluated properties are not allowed ('phy-supply' was unexpected) from schema $id: http://devicetree.org/schemas/net/nxp,dwmac-imx.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8qm-ss-img: Fix jpegenc compatible entryFabio Estevam
The first compatible entry for the jpegenc should be 'nxp,imx8qm-jpgenc'. Change it accordingly to fix the following schema warning: imx8qm-apalis-eval.dtb: jpegenc@58450000: compatible: 'oneOf' conditional failed, one must be fixed: 'nxp,imx8qm-jpgdec' is not one of ['nxp,imx8qxp-jpgdec', 'nxp,imx8qxp-jpgenc'] 'nxp,imx8qm-jpgenc' was expected 'nxp,imx8qxp-jpgdec' was expected Fixes: 5bb279171afc ("arm64: dts: imx8: Add jpeg encoder/decoder nodes") Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Mirela Rabulea <mirela.rabulea@nxp.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx93: Fix the dmas entries orderFabio Estevam
Per fsl-lpuart.yaml, the dmas and dma-names entries should be 'rx' followed by 'tx'. Change the order to fix the following schema warning: imx93-11x11-evk.dtb: serial@44380000: dma-names:0: 'rx' was expected from schema $id: http://devicetree.org/schemas/serial/fsl-lpuart.yaml# imx93-11x11-evk.dtb: serial@44380000: dma-names:1: 'tx' was expected from schema $id: http://devicetree.org/schemas/serial/fsl-lpuart.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8mm-venice-gw790: Pass GSC address/size-cellsFabio Estevam
Per gateworks-gsc.yaml, #address-cells and #size-cells are mandatory properties. Pass them to fix the following schema warning: imx8mm-venice-gw7903.dtb: gsc@20: '#address-cells' is a required property from schema $id: http://devicetree.org/schemas/mfd/gateworks-gsc.yaml# imx8mm-venice-gw7903.dtb: gsc@20: '#size-cells' is a required property from schema $id: http://devicetree.org/schemas/mfd/gateworks-gsc.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Acked-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8dxl: Pass fsl,imx8dxl-sc-wdtFabio Estevam
Pass 'fsl,imx8dxl-sc-wdt' to fix the following schema warning: system-controller: watchdog:compatible:0: 'fsl,imx8qxp-sc-wdt' was expected from schema $id: http://devicetree.org/schemas/firmware/fsl,scu.yaml# system-controller: watchdog:compatible: ['fsl,imx-sc-wdt'] is too short from schema $id: http://devicetree.org/schemas/firmware/fsl,scu.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8dxl: Pass fsl,imx8dxl-sc-thermalFabio Estevam
Pass 'fsl,imx8dxl-sc-thermal' to fix the following schema warning: system-controller: thermal-sensor:compatible:0: 'fsl,imx8qxp-sc-thermal' was expected from schema $id: http://devicetree.org/schemas/firmware/fsl,scu.yaml# system-controller: thermal-sensor:compatible: ['fsl,imx-sc-thermal'] is too short from schema $id: http://devicetree.org/schemas/firmware/fsl,scu.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8dxl: Remove wakeup-irqFabio Estevam
wakeup-irq is not documented, and not used anywhere. Remove it. Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8dxl: Pass fsl,imx8dl-scu-pdFabio Estevam
Pass 'fsl,imx8dl-scu-pd' to fix the following schema warning: system-controller: power-controller:compatible:0: 'fsl,scu-pd' is not one of ['fsl,imx8qm-scu-pd', 'fsl,imx8qxp-scu-pd'] from schema $id: http://devicetree.org/schemas/firmware/fsl,scu.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8qm-mek: enable 8qm lpuart2 and lpuart3Frank Li
Enable uart2 and uart3 for imx8qm-mek board. Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8qxp-mek: enable 8qxp lpuart2 and lpuart3Frank Li
Enable uart2 and uart3 for imx8qxp-mek board. Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8: update lpuart[0..3] irq numberFrank Li
Original irq number combined UART irq and DMA irq. These doesn't match uart driver and dma engine's expection. Update to the irq numbers, which just uart can trigger. Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8qm: Update edma channel for uart[0..3]Frank Li
imx8qm have difference dma channel number for uart[0..3]. Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8: add edma for uart[0..3]Frank Li
Add dma support uart[0..3]. Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: imx8: add edma[0..3]Frank Li
edma<n> is missed, add them. Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: ls208xa: use a pseudo-bus to constrain usb dma sizeLaurentiu Tudor
Wrap the usb controllers in an intermediate simple-bus and use it to constrain the dma address size of these usb controllers to the 40b that they generate toward the interconnect. This is required because the SoC uses 48b address sizes and this mismatch would lead to smmu context faults [1] because the usb generates 40b addresses while the smmu page tables are populated with 48b wide addresses. [1] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1 xhci-hcd xhci-hcd.0.auto: hcc params 0x0220f66d hci version 0x100 quirks 0x0000000002000010 xhci-hcd xhci-hcd.0.auto: irq 108, io mem 0x03100000 xhci-hcd xhci-hcd.0.auto: xHCI Host Controller xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2 xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed arm-smmu 5000000.iommu: Unhandled context fault: fsr=0x402, iova=0xffffffb000, fsynr=0x0, cbfrsynra=0xc01, cb=3 Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: freescale: add phyGATE-Tauri i.MX 8M Mini SupportYannic Moog
phyGATE-Tauri uses a phyCORE-i.MX8MM SoM. Add device tree for the board. Signed-off-by: Yannic Moog <y.moog@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10Merge tag 'imx-fixes-6.6' into imx/dt64Shawn Guo
i.MX fixes for 6.6: - A couple of i.MX8MP device tree changes from Adam Ford to fix clock configuration regressions caused by 16c984524862 ("arm64: dts: imx8mp: don't initialize audio clocks from CCM node"). - Fix pmic-irq-hog GPIO line in imx93-tqma9352 device tree. - Fix a mmemory leak with error handling path of imx_dsp_setup_channels() in imx-dsp driver. - Fix HDMI node in imx8mm-evk device tree. - Add missing clock enable functionality for imx8mm_soc_uid() function in soc-imx8m driver. - Add missing imx8mm-prt8mm.dtb build target.
2023-10-10dt-bindings: arm: fsl: Add TQ-Systems LS1088 based boardsGregor Herburger
TQMLS1088a uses a common board layout with TQMLS1043A/TQMLS1046A. MBLS10XXA is a starterkit baseboard usable for these SOMs. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Gregor Herburger <gregor.herburger@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10dt-bindings: arm: fsl: Add TQ-Systems LS1043A/LS1046A based boardsGregor Herburger
TQMLS1043A and TQMLS1046A use the LS1043A LS1046A SOC on a common layout. MBLS10XXA is a starterkit baseboard usable for both SOMs. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Gregor Herburger <gregor.herburger@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10dt-bindings: arm: Add SolidRun LX2162A SoM & Clearfog BoardJosua Mayer
SolidRun now have 2 product lines around NXP Layerscape SoC: - LX2160A COM Express 7 - LX2162A System on Module LX2162 is a smaller package and reduced feature set to LX2160A; LX2162 SoM is also a smaller form factor and reduced feature set to CEX. Since both product lines are physically incompatible, the existing group "SolidRun LX2160A based Boards" has been renamed to include "CEX" in its name, meaning products based on LX2160A COM Express Module, following this pattern: "solidrun,<board>", "solidrun,lx2160a-cex", "fsl,lx2160a" Add DT compatible for both SolidRun LX2162A SoM, and LX2162 Clearfog boards to a new group based on LX2162A SoM, following this pattern: "solidrun,<board>", "solidrun,lx2162a-som", "fsl,lx2160a" Signed-off-by: Josua Mayer <josua@solid-run.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-10arm64: dts: rockchip: Add board device tree for rk3588-orangepi-5-plusOndrej Jirman
Orange Pi 5 Plus is RK3588 based SBC featuring: - 2x 2.5G ethernet ports – onboard NIC hooked to PCIe 2.0 interface - 2x USB 2.0 host ports - 2x USB 3.0 host ports (exposed over USB 3.0 hub) - Type-C port featuring USB 2.0/3.0 and Alt-DP mode - PCIe 2.0/USB 2.0/I2S/I2C/UART on E.KEY socket - RTC - ES8388 on-board sound codec – jack in/out, onboard mic, speaker amplifier - SPI NOR flash - RGB LED (R is always on) - IR receiver - PCIe 3.0 on the bottom for NVMe, etc. - 40pin GPIO header (with gpio, I2C, SPI, PWM, UART) - Power, recovery and Mask ROM buttons - 2x HDMI out, 1x HDMI in - Slots/connectors for eMMC, uSD card, fan, MIPI CSI/DSI Signed-off-by: Ondrej Jirman <megi@xff.cz> Link: https://lore.kernel.org/r/20231008130515.1155664-5-megi@xff.cz Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-10-10dt-bindings: arm: rockchip: Add Orange Pi 5 PlusOndrej Jirman
Add devicetree binding documentation for Orange Pi 5 Plus SBC made by Xunlong. Signed-off-by: Ondrej Jirman <megi@xff.cz> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231008130515.1155664-4-megi@xff.cz Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-10-10arm64: dts: rockchip: Add UART9 M0 pin definitions to rk3588sOndrej Jirman
This is used on Orange Pi 5 Plus. Signed-off-by: Ondrej Jirman <megi@xff.cz> Link: https://lore.kernel.org/r/20231008130515.1155664-3-megi@xff.cz Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-10-10arm64: dts: rockchip: Add I2S2 M0 pin definitions to rk3588sOndrej Jirman
This is used on Orange Pi 5 Plus. Signed-off-by: Ondrej Jirman <megi@xff.cz> Link: https://lore.kernel.org/r/20231008130515.1155664-2-megi@xff.cz Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-10-10arm64: dts: rockchip: Add Orange Pi 5Muhammed Efe Cetin
Add initial support for OPi5 that includes support for USB2, PCIe2, Sata, Sdmmc, SPI Flash, PMIC. Signed-off-by: Muhammed Efe Cetin <efectn@6tel.net> Reviewed-by: Ondřej Jirman <megi@xff.cz> Link: https://lore.kernel.org/r/4212da199c9c532b60d380bf1dfa83490e16bc13.1696878787.git.efectn@6tel.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-10-10arm64: dts: rockchip: Add sfc node to rk3588sMuhammed Efe Cetin
Add SFC (SPI Flash) to RK3588S SOC. Reviewed-by: Dhruva Gole <d-gole@ti.com> Signed-off-by: Muhammed Efe Cetin <efectn@6tel.net> Link: https://lore.kernel.org/r/d36a64edfaede92ce2e158b0d9dc4f5998e019e3.1696878787.git.efectn@6tel.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-10-10dt-bindings: arm: rockchip: Add Orange Pi 5 boardMuhammed Efe Cetin
Add Orange Pi 5 SBC from Xunlong. Signed-off-by: Muhammed Efe Cetin <efectn@6tel.net> Reviewed-by: Dhruva Gole <d-gole@ti.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/89e92c8df546a0b926ba7481aa83c1945e81e8a4.1696878787.git.efectn@6tel.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-10-09ARM: dts: ixp4xx: Use right restart keycodeLinus Walleij
The "reset" key on a few IXP4xx routers were sending KEY_ESC but what we want to send is KEY_RESTART which will make OpenWrt and similar userspace do a controlled reboot. Link: https://lore.kernel.org/r/20230908-ixp4xx-dts-v1-2-98d36264ed6d@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-10-09ARM: dts: ixp4xx-nslu2: Enable write on flashLinus Walleij
To upgrade the firmware and similar, the flash needs write access. Link: https://lore.kernel.org/r/20230908-ixp4xx-dts-v1-1-98d36264ed6d@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-10-09ARM: dts: ixp4xx: Add USRobotics USR8200 device treeLinus Walleij
This is a USRobotics NAS/Firewall/router that has been supported by OpenWrt in the past. It had dedicated users so let's get it properly supported. Some debugging and fixing was provided by Howard Harte. Link: https://lore.kernel.org/r/20231007-ixp4xx-usr8200-v1-1-aded3d6ff6f1@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-10-09ARM: dts: Use only the Linksys compatible for nowLinus Walleij
The Gemtek users can just use the Linksys device tree, triplet compatible is overdoing it. Link: https://lore.kernel.org/r/20231007-ixp4xx-usr8200-v3-3-ec46edd1ff0e@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-10-09dt-bindings: arm: List more IXP4xx devicesLinus Walleij
The ixp4xx bindings are lacking some of the devices we have out there in the wild, so let's add them. Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231007-ixp4xx-usr8200-v3-2-ec46edd1ff0e@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-10-09dt-bindings: Add vendor prefixesLinus Walleij
These vendor prefixes are used by some routers supported by e.g. OpenWrt. - ADI Engineering is a US telecom equipment company. - Arcom Controllers is a US manufacturer of repeaters. - Freecom Gmbh is a german telecom equipment company. - Gemtek Technology is a Taiwan telecom company. - Gateway Communications was a telecommunication company, now acquired by HKT Limited/PCCW. - Goramo Gorecki is a privately owned Polish telecom company. - U.S. Robotics Corporation, known through their brand name USRobotics is generally referred to as "USR" so use this prefix for the company's device tree bindings. Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231007-ixp4xx-usr8200-v3-1-ec46edd1ff0e@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-10-09Merge initial Sophgo patches into riscv-dt-for-nextConor Dooley
Two series, from Chen and Jisheng, to add support for some of Sophgo's offerings - albeit on vastly different ends of the spectrum. The sg2042 is a "developer motherboard" with a 64 core SoC. The cv1800 series are aimed for use in IP cameras, as far as I can tell, and have one core for running Linux on. I expect that Chen Wang will take over maintenance of these SoCs once they have got more used to the process etc, and in the meantime I will apply the patches and send them to the soc maintainers. At least, that was what they requested I do :) Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-10-09ARM: dts: imx27-phytec: Use eeprom as the node nameFabio Estevam
Node names should be generic, so use 'eeprom' to fix the following schema warnings: at24@52: $nodename:0: 'at24@52' does not match '^eeprom@[0-9a-f]{1,2}$' from schema $id: http://devicetree.org/schemas/eeprom/at24.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-09ARM: dts: imx51: Remove invalid sahara compatibleFabio Estevam
Per fsl-imx-sahara.yaml, there should not be a 'fsl,imx51-sahara' compatible. Remove it to fix the following schema warning: imx51-apf51.dtb: crypto@83ff8000: compatible: ['fsl,imx53-sahara', 'fsl,imx51-sahara'] is too long from schema $id: http://devicetree.org/schemas/crypto/fsl-imx-sahara.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-09dt-bindings: arm: fsl: add phyGATE-Tauri-L boardYannic Moog
Add dt compatible for the phyGATE-Tauri-L board. It uses the phyCORE-i.MX8MM SoM Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Yannic Moog <y.moog@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-10-09ARM: dts: stm32: add SDIO pinctrl sleep support on stm32f7 boardsBen Wolsieffer
Use the new analog mode SDIO pin definitions on the STM32F7 boards. Signed-off-by: Ben Wolsieffer <ben.wolsieffer@hefring.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2023-10-09ARM: dts: stm32: add stm32f7 SDIO sleep pinsBen Wolsieffer
Add SDIO sleep pin definitions that place the pins in analog mode to save power. Signed-off-by: Ben Wolsieffer <ben.wolsieffer@hefring.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2023-10-09ARM: dts: stm32: add RNG node for STM32MP13x platformsGatien Chevallier
The RNG on STM32MP13 offers upgrades like customization of its configuration and the conditional reset. The hardware RNG should be managed in the secure world for but it is supported on Linux. Therefore, is it not default enabled. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
generated by cgit (git 2.34.1) at 2025-09-28 09:44:35 +0000