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2017-04-24sparc64: Improve 64-bit constant loading in eBPF JIT.David S. Miller
Doing a full 64-bit decomposition is really stupid especially for simple values like 0 and -1. But if we are going to optimize this, go all the way and try for all 2 and 3 instruction sequences not requiring a temporary register as well. First we do the easy cases where it's a zero or sign extended 32-bit number (sethi+or, sethi+xor, respectively). Then we try to find a range of set bits we can load simply then shift up into place, in various ways. Then we try negating the constant and see if we can do a simple sequence using that with a xor at the end. (f.e. the range of set bits can't be loaded simply, but for the negated value it can) The final optimized strategy involves 4 instructions sequences not needing a temporary register. Otherwise we sadly fully decompose using a temp.. Example, from ALU64_XOR_K: 0x0000ffffffff0000 ^ 0x0 = 0x0000ffffffff0000: 0000000000000000 <foo>: 0: 9d e3 bf 50 save %sp, -176, %sp 4: 01 00 00 00 nop 8: 90 10 00 18 mov %i0, %o0 c: 13 3f ff ff sethi %hi(0xfffffc00), %o1 10: 92 12 63 ff or %o1, 0x3ff, %o1 ! ffffffff <foo+0xffffffff> 14: 93 2a 70 10 sllx %o1, 0x10, %o1 18: 15 3f ff ff sethi %hi(0xfffffc00), %o2 1c: 94 12 a3 ff or %o2, 0x3ff, %o2 ! ffffffff <foo+0xffffffff> 20: 95 2a b0 10 sllx %o2, 0x10, %o2 24: 92 1a 60 00 xor %o1, 0, %o1 28: 12 e2 40 8a cxbe %o1, %o2, 38 <foo+0x38> 2c: 9a 10 20 02 mov 2, %o5 30: 10 60 00 03 b,pn %xcc, 3c <foo+0x3c> 34: 01 00 00 00 nop 38: 9a 10 20 01 mov 1, %o5 ! 1 <foo+0x1> 3c: 81 c7 e0 08 ret 40: 91 eb 40 00 restore %o5, %g0, %o0 Signed-off-by: David S. Miller <davem@davemloft.net>
2017-04-25Bluetooth: convert smp and selftest to crypto kpp APISalvatore Benedetto
* Convert both smp and selftest to crypto kpp API * Remove module ecc as no more required * Add ecdh_helper functions for wrapping kpp async calls This patch has been tested *only* with selftest, which is called on module loading. Signed-off-by: Salvatore Benedetto <salvatore.benedetto@intel.com> Signed-off-by: Marcel Holtmann <marcel@holtmann.org>
2017-04-24hexagon: switch to RAW_COPY_USERAl Viro
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2017-04-24Input: i8042 - add Clevo P650RS to the i8042 reset listDmitry Torokhov
Clevo P650RS and other similar devices require i8042 to be reset in order to detect Synaptics touchpad. Reported-by: Paweł Bylica <chfast@gmail.com> Tested-by: Ed Bordin <edbordin@gmail.com> Cc: stable@vger.kernel.org Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=190301 Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2017-04-24sparc64: Support cbcond instructions in eBPF JIT.David S. Miller
cbcond combines a compare with a branch into a single instruction. The limitations are: 1) Only newer chips support it 2) For immediate compares we are limited to 5-bit signed immediate values 3) The branch displacement is limited to 10-bit signed 4) We cannot use it for JSET Also, cbcond (unlike all other sparc control transfers) lacks a delay slot. Currently we don't have a useful instruction we can push into the delay slot of normal branches. So using cbcond pretty much always increases code density, and is therefore a win. Signed-off-by: David S. Miller <davem@davemloft.net>
2017-04-24Merge branch 'dsa-b53-58xx-fixes'David S. Miller
Florian Fainelli says: ==================== net: dsa: b53: BCM58xx devices fixes This patch series contains fixes for the 58xx devices (Broadcom Northstar Plus), which were identified thanks to the help of Eric Anholt. ==================== Tested-by: Eric Anholt <eric@anholt.net> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-04-24net: dsa: b53: Fix CPU port for 58xx devicesFlorian Fainelli
The 58xx devices (Northstar Plus) do actually have their CPU port wired at port 8, it was unfortunately set to port 5 (B53_CPU_PORT_25) which is incorrect, since that is the second possible management port. Fixes: 991a36bb4645 ("net: dsa: b53: Add support for BCM585xx/586xx/88312 integrated switch") Reported-by: Eric Anholt <eric@anholt.net> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-04-24net: dsa: b53: Implement software reset for 58xx devicesFlorian Fainelli
Implement the correct software reset sequence for 58xx devices by setting all 3 reset bits and polling for the SW_RST bit to clear itself without a given timeout. We cannot use is58xx() here because that would also include the 7445/7278 Starfighter 2 which have their own driver doing the reset earlier on due to the HW specific integration. Fixes: 991a36bb4645 ("net: dsa: b53: Add support for BCM585xx/586xx/88312 integrated switch") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-04-24net: dsa: b53: Include IMP/CPU port in dumb forwarding modeFlorian Fainelli
Since Broadcom tags are not enabled in b53 (DSA_PROTO_TAG_NONE), we need to make sure that the IMP/CPU port is included in the forwarding decision. Without this change, switching between non-management ports would work, but not between management ports and non-management ports thus breaking the default state in which DSA switch are brought up. Fixes: 967dd82ffc52 ("net: dsa: b53: Add support for Broadcom RoboSwitch") Reported-by: Eric Anholt <eric@anholt.net> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-04-24Merge tag 'perf-core-for-mingo-4.12-20170424' of ↵Ingo Molnar
git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/core Pull perf/core improvements and fixes from Arnaldo Carvalho de Melo: User visible changes: - Fix display of data source snoop indication in 'perf mem' (Andi Kleen) - Fix the code to strip command name from /proc/PID/stat (Jiri Olsa) Infrastructure changes: - Continue the disentanglement of headers, specially util.h (Arnaldo Carvalho de Melo) - Synchronize some header files with the kernel (Arnaldo Carvalho de Melo) Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com> Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-04-24Merge tag 'scsi-fixes' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi Pull SCSI fix from James Bottomley: "Our final fix before the 4.12 release (hopefully). It's an error leg again: the fix to not bug on empty DMA transfers is returning the wrong code and confusing the block layer" * tag 'scsi-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi: scsi: return correct blkprep status code in case scsi_init_io() fails.
2017-04-24Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds
Pull MIPS fixes from Ralf Baechle: "Another round of 4.11 for the MIPS architecture. This time around it's mostly arch but little platforms-specific code. - PCI: Register controllers in the right order to aoid a PCI error - KGDB: Use kernel context for sleeping threads - smp-cps: Fix potentially uninitialised value of core - KASLR: Fix build - ELF: Fix BUG() warning in arch_check_elf - Fix modversioning of _mcount symbol - fix out-of-tree defconfig target builds - cevt-r4k: Fix out-of-bounds array access - perf: fix deadlock - Malta: Fix i8259 irqchip setup" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: MIPS: PCI: add controllers before the specified head MIPS: KGDB: Use kernel context for sleeping threads MIPS: smp-cps: Fix potentially uninitialised value of core MIPS: KASLR: Add missing header files MIPS: Avoid BUG warning in arch_check_elf MIPS: Fix modversioning of _mcount symbol MIPS: generic: fix out-of-tree defconfig target builds MIPS: cevt-r4k: Fix out-of-bounds array access MIPS: perf: fix deadlock MIPS: Malta: Fix i8259 irqchip setup
2017-04-24Merge branch 'bpf-misc-cleanups'David S. Miller
Alexander Alemayhu says: ==================== Misc BPF cleanup while looking into making the Makefile in samples/bpf better handle O= I saw several warnings when running `make clean && make samples/bpf/`. This series reduces those warnings. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2017-04-24samples/bpf: check before defining offsetofAlexander Alemayhu
Fixes the following warning samples/bpf/test_lru_dist.c:28:0: warning: "offsetof" redefined #define offsetof(TYPE, MEMBER) ((size_t)&((TYPE *)0)->MEMBER) In file included from ./tools/lib/bpf/bpf.h:25:0, from samples/bpf/libbpf.h:5, from samples/bpf/test_lru_dist.c:24: /usr/lib/gcc/x86_64-redhat-linux/6.3.1/include/stddef.h:417:0: note: this is the location of the previous definition #define offsetof(TYPE, MEMBER) __builtin_offsetof (TYPE, MEMBER) Signed-off-by: Alexander Alemayhu <alexander@alemayhu.com> Acked-by: Daniel Borkmann <daniel@iogearbox.net> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-04-24samples/bpf: add static to function with no prototypeAlexander Alemayhu
Fixes the following warning samples/bpf/cookie_uid_helper_example.c: At top level: samples/bpf/cookie_uid_helper_example.c:276:6: warning: no previous prototype for ‘finish’ [-Wmissing-prototypes] void finish(int ret) ^~~~~~ HOSTLD samples/bpf/per_socket_stats_example Signed-off-by: Alexander Alemayhu <alexander@alemayhu.com> Acked-by: Daniel Borkmann <daniel@iogearbox.net> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-04-24samples/bpf: add -Wno-unknown-warning-option to clangAlexander Alemayhu
I was initially going to remove '-Wno-address-of-packed-member' because I thought it was not supposed to be there but Daniel suggested using '-Wno-unknown-warning-option'. This silences several warnings similiar to the one below warning: unknown warning option '-Wno-address-of-packed-member' [-Wunknown-warning-option] 1 warning generated. clang -nostdinc -isystem /usr/lib/gcc/x86_64-redhat-linux/6.3.1/include -I./arch/x86/include -I./arch/x86/include/generated/uapi -I./arch/x86/include/generated -I./include -I./arch/x86/include/uapi -I./include/uapi -I./include/generated/uapi -include ./include/linux/kconfig.h \ -D__KERNEL__ -D__ASM_SYSREG_H -Wno-unused-value -Wno-pointer-sign \ -Wno-compare-distinct-pointer-types \ -Wno-gnu-variable-sized-type-not-at-end \ -Wno-address-of-packed-member -Wno-tautological-compare \ -O2 -emit-llvm -c samples/bpf/xdp_tx_iptunnel_kern.c -o -| llc -march=bpf -filetype=obj -o samples/bpf/xdp_tx_iptunnel_kern.o $ clang --version clang version 3.9.1 (tags/RELEASE_391/final) Target: x86_64-unknown-linux-gnu Thread model: posix InstalledDir: /usr/bin Signed-off-by: Alexander Alemayhu <alexander@alemayhu.com> Acked-by: Daniel Borkmann <daniel@iogearbox.net> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-04-24bpf: make bpf_xdp_adjust_head support mandatoryDaniel Borkmann
Now that also the last in-tree user of the xdp_adjust_head bit has been removed, we can remove the flag from struct bpf_prog altogether. This, at the same time, also makes sure that any future driver for XDP comes with bpf_xdp_adjust_head() support right away. A rejection based on this flag would also mean that tail calls couldn't be used with such driver as per c2002f983767 ("bpf: fix checking xdp_adjust_head on tail calls") fix, thus lets not allow for it in the first place. Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Acked-by: Alexei Starovoitov <ast@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-04-24qlcnic: fix unchecked return valuePan Bian
Function pci_find_ext_capability() may return 0, which is an invalid address. In function qlcnic_sriov_virtid_fn(), its return value is used without validation. This may result in invalid memory access bugs. This patch fixes the bug. Signed-off-by: Pan Bian <bianpan2016@163.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-04-24Merge tag 'mlx5-fixes-2017-04-22' of ↵David S. Miller
git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux Saeed Mahameed says: ==================== Mellanox, mlx5 fixes 2017-04-22 This series contains some mlx5 fixes for net. For your convenience, the series doesn't introduce any conflict with the ongoing net-next pull request. Please pull and let me know if there's any problem. For -stable: ("net/mlx5: E-Switch, Correctly deal with inline mode on ConnectX-5") kernels >= 4.10 ("net/mlx5e: Fix ETHTOOL_GRXCLSRLALL handling") kernels >= 4.8 ("net/mlx5e: Fix small packet threshold") kernels >= 4.7 ("net/mlx5: Fix driver load bad flow when having fw initializing timeout") kernels >= 4.4 ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2017-04-24wan: pc300too: abort path on failurePan Bian
In function pc300_pci_init_one(), on the ioremap error path, function pc300_pci_remove_one() is called to free the allocated memory. However, the path is not terminated, and the freed memory will be used later, resulting in use-after-free bugs. This path fixes the bug. Signed-off-by: Pan Bian <bianpan2016@163.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-04-24tipc: check return value of nlmsg_newPan Bian
Function nlmsg_new() will return a NULL pointer if there is no enough memory, and its return value should be checked before it is used. However, in function tipc_nl_node_get_monitor(), the validation of the return value of function nlmsg_new() is missed. This patch fixes the bug. Signed-off-by: Pan Bian <bianpan2016@163.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-04-24lwtunnel: check return value of nla_nest_startPan Bian
Function nla_nest_start() may return a NULL pointer on error. However, in function lwtunnel_fill_encap(), the return value of nla_nest_start() is not validated before it is used. This patch checks the return value of nla_nest_start() against NULL. Signed-off-by: Pan Bian <bianpan2016@163.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-04-24mmc: cavium: Add MMC support for Octeon SOCs.Steven J. Hill
Add platform driver for Octeon SOCs. Signed-off-by: Steven J. Hill <Steven.Hill@cavium.com> Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24mmc: cavium: Fix detection of block or byte addressing.Steven J. Hill
Use the mmc_card_is_blockaddr() function to properly detect if the card uses byte or block addressing. Signed-off-by: Steven J. Hill <Steven.Hill@cavium.com> Acked-by: David Daney <david.daney@cavium.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24mmc: core: Export API to allow hosts to get the card addressUlf Hansson
Some hosts controllers, like Cavium, needs to know whether the card operates in byte- or block-address mode. Therefore export a new API, mmc_card_is_blockaddr(), which provides this information. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Steven J. Hill <Steven.Hill@cavium.com> Acked-by: David Daney <david.daney@cavium.com>
2017-04-24mmc: sdio: Fix sdio wait busy implement limitationjiajie.hao@mediatek.com
The host may issue an I/O abort by writing to the CCCR at any time during I/O read operation via CMD52. And host may need suspend transcation during write busy stage in SDIO suspend/resume scenario. >From other side, a card may accept CMD52 during data transfer phase. Previous implement would block issuing above command in busy stage. It cause function driver can't implement as proper way and has no opportunity to do some coverage in error case via I/O abort etc. We need bypass some necessary operation during busy check stage. Signed-off-by: Jiajie Hao <jiajie.hao@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24mmc: sdhci-esdhc-imx: reset tuning circuit when power on mmc cardHaibo Chen
USDHC tuning circuit should be reset before every time card enumeration or re-enumeration. SD3.0 card need tuning. For SDR104 card, when system suspend in standby mode, and then resume back, the IO timing is still SDR104(tuned) which may result in card re-enumeration fail in low card speed(400khz) for some cards. And we did meet the issue that in certain probability, SDR104 card meet mmc command CRC/Timeout error when send CMD2 during mmc bus resume. This patch reset the tuning circuit when the ios timing is MMC_TIMING_LEGACY/MMC_TIMING_MMC_HS/MMC_TIMING_SD_HS, which means both mmc_power_up() and mmc_power_off() will reset the tuning circuit. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Acked-by: Dong Aisheng <aisheng.dong@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24clk: apn806: fix spelling mistake: "mising" -> "missing"Colin Ian King
trivial fix to spelling mistake in dev_warn message Signed-off-by: Colin Ian King <colin.king@canonical.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24mmc: sdhci-of-esdhc: add delay between tuning cyclesyangbo lu
It's observed that eSDHC needed delay between tuning cycles for HS200 successful tuning. This patch is to set 1ms delay for that. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24mmc: sdhci: Control the delay between tuning commandsAdrian Hunter
The delay between tuning commands for SD cards is not part of the specification. A driver that needs it probably needs it for eMMC too, whereas most drivers would probably like to set it to 0. Make it a host member (host->tuning_delay) that defaults to the existing behaviour. Drivers can set it to zero to eliminate the delay, or set it to a positive value to always have a delay. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24mmc: sdhci-of-esdhc: add tuning supportyangbo lu
eSDHC uses tuning block for tuning procedure. So the tuning block control register must be configured properly before tuning. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24mmc: sdhci-of-esdhc: add support for signal voltage switchyangbo lu
eSDHC supports signal voltage switch from 3.3v to 1.8v by eSDHC_PROCTL[VOLT_SEL] bit. This bit changes the value of output signal SDHC_VS, and there must be a control circuit out of eSDHC to change the signal voltage according to SDHC_VS output signal. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24mmc: sdhci-of-esdhc: add peripheral clock supportyangbo lu
eSDHC could select peripheral clock or platform clock as clock source by the PCS bit of eSDHC Control Register, and this bit couldn't be reset by software reset for all. In default, the platform clock is used. But we have to use peripheral clock since it has a higher frequency to support eMMC HS200 mode and SD UHS-I mode. This patch is to add peripheral clock support and use it instead of platform clock if it's declared in eSDHC dts node. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24mmc: sdhci-pci: Allow for 3 bytes from Intel DSMAdrian Hunter
The DSM used by some Intel controllers can return a 3 byte package. Allow for that by using memcpy to copy the bytes. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24mmc: cavium: Fix a shift wrapping bugDan Carpenter
"dat" is a u64 and "shift" starts as 54 so this is a shift wrapping bug. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24mmc: cavium: Check pointer before de-referenceJan Glauber
Add a pointer check to prevent this smatch warning: drivers/mmc/host/cavium.c:803 cvm_mmc_request() error: we previously assumed 'cmd->data' could be null (see line 782) This is a theoretical fix because MMC_CMD_ADTC seems to imply that cmd->data is not null. Nevertheless checking cmd->data before using it improves readability. Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24mmc: cavium: Remove redundant pointer checkJan Glauber
Remove redundant mmc->card check reported by smatch: drivers/mmc/host/cavium.c:694 cvm_mmc_dma_request() warn: variable dereferenced before check 'mmc->card' (see line 675) Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24mmc: meson-gx: add support for descriptor chain modeHeiner Kallweit
So far a bounce buffer is used to serialize the scatterlist(s). This overhead can be avoided by switching to descriptor chain mode. As result the performance is drastically improved. On a Odroid-C2 with a 128 GB eMMC module raw reads reach 140 MB/s. Prerequisite for descriptor chain mode is that all scatterlist buffers are 8 byte aligned for 64-bit DMA. That's not always the case, at least the brcmfmac SDIO WiFi driver is known to cause problems. Therefore, for each request, check upfront whether all scatterlist buffers are 8 byte aligned and fall back to bounce buffer mode if that's not the case. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24mmc: meson-gx: add basic tuning for rx clock phaseHeiner Kallweit
This patch adds basic tuning which changes the rx clock phase only until a working setting is found. On a Odroid C2 with 128GB eMMC card and 200 MHz MMC clock only 180° rx clock phase make the system boot w/o CRC errors. With other MMC devices / clock speeds this might be different, therefore don't change the driver config in general. When retuning skip the currently active parameter set. This avoids the current problematic config to be chosen again if it causes CRC errors just occasionally. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24mmc: meson-gx: introduce struct meson_tuning_paramsHeiner Kallweit
Introduce struct meson_tuning_params for storing the clock phase configurations. There's no functional change because tx and rx clock phase were implicitely set to CLK_PHASE_0 before. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24mmc: core: add proper be32 annotationWinkler, Tomas
Annotate big endian values correctly and make sparse happy. In mmc_app_send_scr remove scr function parameter as it was updating card->raw_scr anyway. Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24mmc: sdhci-cadence: add parsing sdhci propertiesPiotr Sroka
Add calling sdhci_get_of_property function to parse sdhci properties. Signed-off-by: Piotr Sroka <piotrs@cadence.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24mmc: host: omap_hsmmc: checking for NULL instead of IS_ERR()Dan Carpenter
devm_pinctrl_get() returns error pointers, it never returns NULL. Fixes: 455e5cd6f736 ("mmc: omap_hsmmc: Pin remux workaround to support SDIO interrupt on AM335x") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24MAINTAINERS: add entry for Marvell Xenon MMC Host Controller driversHu Ziji
Add maintainer entry for Marvell Xenon eMMC/SD/SDIO Host Controller drivers. Signed-off-by: Hu Ziji <huziji@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24mmc: sdhci-xenon: Add SoC PHY PAD voltage controlHu Ziji
Some SoCs have PHY PAD outside Xenon IP. PHY PAD voltage should match signalling voltage in use. Add generic SoC PHY PAD voltage control interface. Implement Aramda-3700 SoC PHY PAD voltage control. Signed-off-by: Hu Ziji <huziji@marvell.com> Tested-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHCHu Ziji
Marvell Xenon eMMC/SD/SDIO Host Controller contains PHY. Multiple types of PHYs are supported. Add support to multiple types of PHYs init and configuration. Add register definitions of PHYs. Xenon PHY cannot fit in kernel common PHY framework. Xenon SDHC PHY register is a part of Xenon SDHC register set. Besides, MMC initialization has to call several PHY functions to complete timing setting. Those PHY setting functions have to access SDHC registers and know current MMC setting, such as bus width, clock frequency and speed mode. As a result, implement Xenon PHY in MMC host directory. Signed-off-by: Hu Ziji <huziji@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24mmc: sdhci-xenon: Add Marvell Xenon SDHC core functionalityHu Ziji
Add Xenon eMMC/SD/SDIO host controller core functionality. Add Xenon specific initialization process. Add Xenon specific mmc_host_ops APIs. Add Xenon specific register definitions. Add CONFIG_MMC_SDHCI_XENON support in drivers/mmc/host/Kconfig. Marvell Xenon SDHC conforms to SD Physical Layer Specification Version 3.01 and is designed according to the guidelines provided in the SD Host Controller Standard Specification Version 3.00. Signed-off-by: Hu Ziji <huziji@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24dt: bindings: Add bindings for Marvell Xenon SD Host ControllerHu Ziji
Marvell Xenon SDHC can support eMMC/SD/SDIO. Add Xenon-specific properties. Also add properties for Xenon PHY setting. Signed-off-by: Hu Ziji <huziji@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24mmc: sdhci: Export sdhci_enable_sdio_irq() from sdhci.cHu Ziji
Export sdhci_enable_sdio_irq() from sdhci.c. Thus vendor SDHC driver can implement its specific SDIO irq control. Signed-off-by: Hu Ziji <huziji@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24mmc: sdhci: Export sdhci_start_signal_voltage_switch() in sdhci.cHu Ziji
Export sdhci_start_signal_voltage_switch() from sdhci.c. Thus vendor sdhci driver can implement its own signal voltage switch routine. Signed-off-by: Hu Ziji <huziji@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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