summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2012-09-29Merge branch 'vt8500/devel' into next/dtOlof Johansson
Picked up one more bugfix by Tony Prisk: * vt8500/devel: arm: vt8500: Fixup for missing gpio.h
2012-09-29arm: vt8500: Fixup for missing gpio.hTony Prisk
mach/include/gpio.h was removed as part of the multiplatform-3.7 update. This patch removes the include from arch-vt8500/vt8500.c Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Olof Johansson <olof@lixom.net>
2012-09-29Merge tag 'omap-devel-board-late-v3-for-v3.7' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup From Tony Lindgren: These board and platform related patches have been posted quite a while ago but have somehow fallen though the cracks as most of the focus has been making things to work with device tree. As the first patch depends on sparse IRQ related removal of irqs.h and related header moves, these are based on omap-cleanup-local-headers-for-v3.7 tag. * tag 'omap-devel-board-late-v3-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP2+: serial: Change MAX_HSUART_PORTS to 6 ARM: OMAP4: twl-common: Support for additional devices on i2c1 bus
2012-09-29Merge tag 'devel-dt-arch-timer-for-v3.7' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt From Tony Lindgren: Few late patches to enable arch timer for omap5 using device tree. * tag 'devel-dt-arch-timer-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP5: Enable arch timer support ARM: OMAP: Add initialisation for the real-time counter.
2012-09-29Merge tag 'omap-devel-late-for-v3.7' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into late/soc These changes take us a step closer to merging the common clock framework for omap but unfortunately these patches were not ready for merging earlier. See also the notes below on the dependencies these patches have, they are based on a merge of sereral branches already merged. From Paul Walmsley <paul@pwsan.com>: OMAP patches intended for the 3.7 merge window: - Runtime PM conversions for the GPMC and RNG IP blocks - Preparation patches for the OMAP common clock framework conversion - clkdev alias additions required by other drivers - Performance Monitoring Unit (PMU) support for OMAP2, 3, and non-4430 OMAP4 - OMAP hwmod code and data improvements - Preparation patches for the IOMMU runtime PM conversion - Preparation patches for OMAP4 full-chip retention support Based on a merge of v3.6-rc6, the omap-cleanup-b-for-3.7 tag (7852ec0536ca39cefffc6301dc77f8ae55592926),the cleanup-fixes-for-v3.7 tag (de6ca33a96a6bf61fcb91d3d399703e19ead9d1e), and the omap-devel-am33xx-for-v3.7 tag (11964f53eb4d9ce59a058be9999d9cfcb1ced878), due to dependencies. * tag 'omap-devel-late-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (281 commits) ARM: OMAP4460/4470: PMU: Enable PMU for OMAP4460/70 ARM: OMAP2+: PMU: Add runtime PM support ARM: OMAP4430: PMU: prepare to create PMU device via HWMOD ARM: OMAP2+: PMU: Convert OMAP2/3 devices to use HWMOD ARM: OMAP3: hwmod data: Add debugss HWMOD data ARM: OMAP2+: clockdomain/hwmod: add workaround for EMU clockdomain idle problems ARM: OMAP: Add a timer attribute for timers that can interrupt the DSP hwrng: OMAP: remove SoC restrictions from driver registration ARM: OMAP: split OMAP1, OMAP2+ RNG device registration hwrng: OMAP: convert to use runtime PM hwrng: OMAP: store per-device data in per-device variables, not file statics ARM: OMAP2xxx: hwmod/CM: add RNG integration data ARM: OMAP2+: gpmc: minimal driver support ARM: OMAP2+: gpmc: Adapt to HWMOD ARM: OMAP2/3: hwmod data: add gpmc ARM: OMAP4: hwmod data: add mmu hwmod for ipu and dsp ARM: OMAP3: hwmod data: add mmu data for iva and isp ARM: OMAP: iommu: fix including iommu.h without IOMMU_API selected ARM: OMAP4: hwmod data: add missing HWMOD_NO_IDLEST flags to some PRCM IP blocks ARM: OMAP4: hwmod data: make *phy_48m* as the main_clk of ocp2scp ...
2012-09-29efi: Fix the ACPI BGRT driver for images located in EFI boot services memoryJosh Triplett
The ACPI BGRT driver accesses the BIOS logo image when it initializes. However, ACPI 5.0 (which introduces the BGRT) recommends putting the logo image in EFI boot services memory, so that the OS can reclaim that memory. Production systems follow this recommendation, breaking the ACPI BGRT driver. Move the bulk of the BGRT code to run during a new EFI late initialization phase, which occurs after switching EFI to virtual mode, and after initializing ACPI, but before freeing boot services memory. Copy the BIOS logo image to kernel memory at that point, and make it accessible to the BGRT driver. Rework the existing ACPI BGRT driver to act as a simple wrapper exposing that image (and the properties from the BGRT) via sysfs. Signed-off-by: Josh Triplett <josh@joshtriplett.org> Link: http://lkml.kernel.org/r/93ce9f823f1c1f3bb88bdd662cce08eee7a17f5d.1348876882.git.josh@joshtriplett.org Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2012-09-29efi: Add a function to look up existing IO memory mappingsJosh Triplett
The EFI initialization creates virtual mappings for EFI boot services memory, so if a driver wants to access EFI boot services memory, it cannot call ioremap itself; doing so will trip the WARN about mapping RAM twice. Thus, a driver accessing EFI boot services memory must do so via the existing mapping already created during EFI intiialization. Since the EFI code already maintains a memory map for that memory, add a function efi_lookup_mapped_addr to look up mappings in that memory map. Signed-off-by: Josh Triplett <josh@joshtriplett.org> Link: http://lkml.kernel.org/r/0eb48ae012797912874919110660ad420b90268b.1348876882.git.josh@joshtriplett.org Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2012-09-29efi: Defer freeing boot services memory until after ACPI initJosh Triplett
Some new ACPI 5.0 tables reference resources stored in boot services memory, so keep that memory around until we have ACPI and can extract data from it. Signed-off-by: Josh Triplett <josh@joshtriplett.org> Link: http://lkml.kernel.org/r/baaa6d44bdc4eb0c58e5d1b4ccd2c729f854ac55.1348876882.git.josh@joshtriplett.org Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2012-09-29Merge branch 'dt2' of git://github.com/hzhuang1/linux into next/dtOlof Johansson
From Haojian Zhuang: * 'dt2' of git://github.com/hzhuang1/linux: ARM: dt: mmp-dma: add binding file
2012-09-29Merge branch 'next/dt-samsung-new' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/dt2 From Kukjin Kim: * 'next/dt-samsung-new' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: dts: Add nodes for dw_mmc controllers for Samsung EXYNOS5250 platforms ARM: EXYNOS: Add AUXDATA support for MSHC controllers ARM: EXYNOS: Add support for MSHC controller clocks ARM: dts: Enable on-board keys as wakeup source for exynos4210-origen ARM: dts: use uart2 for console on smdkv310 and smdk5250 ARM: dts: Add basic dts file for Samsung Trats board ARM: EXYNOS: Add OF compatibility lookups for EXYNOS4 i2c adapters ARM: dts: Specify address and size cells for i2c controllers for EXYNOS4 ARM: dts: Assume status of all optional nodes as disabled for exynos4 ARM: EXYNOS: Use exynos4 prefix instead of exynos4210 on exynos4-dt ARM: dts: Move parts common to EXYNOS4 from exynos4210.dtsi to exynos4.dtsi
2012-09-29Merge branch 'samsung/pinctrl' into next/dt2Olof Johansson
* samsung/pinctrl: pinctrl: exynos: Fix wakeup IRQ domain registration check pinctrl: samsung: Uninline samsung_pinctrl_get_soc_data pinctrl: exynos: Correct the detection of wakeup-eint node pinctrl: exynos: Mark exynos_irq_demux_eint as inline pinctrl: exynos: Handle only unmasked wakeup interrupts pinctrl: exynos: Fix typos in gpio/wkup _irq_mask pinctrl: exynos: Set pin function to EINT in irq_set_type of GPIO EINTa ARM: EXYNOS: Enable pinctrl driver support for EXYNOS4 device tree enabled platform ARM: dts: Add pinctrl node entries for SAMSUNG EXYNOS4210 SoC ARM: EXYNOS: skip wakeup interrupt setup if pinctrl driver is used gpio: exynos4: skip gpiolib registration if pinctrl driver is used pinctrl: add exynos4210 specific extensions for samsung pinctrl driver pinctrl: add samsung pinctrl and gpiolib driver
2012-09-29Merge branch 'samsung/boards' into next/dt2Olof Johansson
* samsung/boards: ARM: EXYNOS: Add generic PWM lookup support for SMDKV310 ARM: EXYNOS: Add generic PWM lookup support for SMDK4X12 ARM: EXYNOS: Use generic pwm driver in Origen board ARM: dts: Add heartbeat gpio-leds support to Origen ARM: dts: Use active low flag for gpio-keys on Origen ARM: S3C64XX: Register audio platform devices for Bells on Cragganmore ARM: S3C64XX: Update configuration for WM5102 module on Cragganmore Add/add conflict in arch/arm/mach-exynos/mach-smdkv310.c. Signed-off-by: Olof Johansson <olof@lixom.net>
2012-09-29Merge tag 'iommu-fixes-v3.6-rc7' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu Pull IOMMU fixes from Joerg Roedel: "Two small patches: * One patch to fix the function declarations for !CONFIG_IOMMU_API. This is causing build errors in linux-next and should be fixed for v3.6. * Another patch to fix an IOMMU group related NULL pointer dereference." * tag 'iommu-fixes-v3.6-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: iommu/amd: Fix wrong assumption in iommu-group specific code iommu: static inline iommu group stub functions
2012-09-29Merge git://git.infradead.org/users/willy/linux-nvmeLinus Torvalds
Pull NVMe driver fixes from Matthew Wilcox: "Now that actual hardware has been released (don't have any yet myself), people are starting to want some of these fixes merged." Willy doesn't have hardware? Guys... * git://git.infradead.org/users/willy/linux-nvme: NVMe: Cancel outstanding IOs on queue deletion NVMe: Free admin queue memory on initialisation failure NVMe: Use ida for nvme device instance NVMe: Fix whitespace damage in nvme_init NVMe: handle allocation failure in nvme_map_user_pages() NVMe: Fix uninitialized iod compiler warning NVMe: Do not set IO queue depth beyond device max NVMe: Set block queue max sectors NVMe: use namespace id for nvme_get_features NVMe: replace nvme_ns with nvme_dev for user admin NVMe: Fix nvme module init when nvme_major is set NVMe: Set request queue logical block size
2012-09-29mtd: nand: detect Samsung K9GBG08U0A, K9GAG08U0F IDBrian Norris
Datasheets for the following Samsung NAND parts (both MLC and SLC) describe extensions to the Samsung 6-byte extended ID decoding table: K9GBG08U0A (MLC, 6-byte ID) K9GAG08U0F (MLC, 6-byte ID) K9FAG08U0M (SLC, 6-byte ID) The table found in K9GAG08U0F, p.44, contains a superset of the information found in other previous datasheets. This patch adds support for all of these chips, with 512B and 640B OOB sizes. It also changes the detection pattern such that this table applies to all Samsung 6-byte ID NAND, not just MLC. This is safe, according to the NAND parameter data I have collected: Note that nand_base.c does not yet support the bad block marker scheme defined for these chips (i.e., scan 1st and last page for BB markers). Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: nand: decode Hynix MLC, 6-byte ID lengthBrian Norris
Hynix has introduced a new ID decoding scheme for their newer MLC, some of which don't support ONFI. The following devices all follow the pattern given in the datasheet for Hynix H27UBG8T2B, p.22: Hynix H27UAG8T2A Hynix H27UBG8T2A Hynix H27UBG8T2B Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: nand: increase max OOB size to 640Brian Norris
Some Hynix and Samsung MLC NAND have 640B OOB size. Sooner or later, we should dynamically allocate the buffers that use these macros. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: nand: add generic READ ID length calculation functionsBrian Norris
When decoding the extended ID bytes of a NAND chip, we have to calculate the ID length according to some heuristic patterns (e.g., Does the ID wrap around? Does it end in trailing zeros?). Currently, these heuristics are built into complicated if/else blocks that can be hard to understand. Now, these checks can be done generically in a function, making them more robust and reusable. In fact, this sort of calculation is needed in future additions to nand_base.c. And with this advancement, we get the added benefit of a more readable "extended ID decode". Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: nand: split simple ID decode into its own functionBrian Norris
When detecting NAND parameters, the code gets a little ugly so that the logic is obscured. Try to remedy that by moving code to separate functions that have well-defined purposes. This patch splits out the simple ID decode functionality, where all the information regarding NAND size/blocksize/pagesize/oobsize/busw is encoded in the first two bytes of the ID string. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: nand: split extended ID decoding into its own functionBrian Norris
When detecting NAND parameters, the code gets a little ugly so that the logic is obscured. Try to remedy that by moving code to separate functions that have well-defined purposes. This patch splits out the extended ID decode functionality, which handles decoding the 3rd-8th ID bytes to determine NAND device parameters. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: nand: split BB marker options decoding into its own functionBrian Norris
When detecting NAND parameters, the code gets a little ugly so that the logic is obscured. Try to remedy that by moving code to separate functions that have well-defined purposes. This patch splits the bad block marker options detection into its own function, away from the other parameters (e.g., chip size, page size, etc.). Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: nand: remove redundant ID readBrian Norris
Instead of reading 2 bytes then later 8 bytes, we can simply read all 8 bytes from the start. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: nand: remove unnecessary variableBrian Norris
We don't actually use the 'ret' variable; we set it, test it, and then it dies. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: docg4: add missing HAS_IOMEM dependencyPeter Huewe
While building an allyesconfig for UML I received this error message(s): drivers/mtd/nand/docg4.c: In function 'probe_docg4': drivers/mtd/nand/docg4.c:1272:2: error: implicit declaration of function 'ioremap' [-Werror=implicit-function-declaration] drivers/mtd/nand/docg4.c:1272:10: warning: assignment makes pointer from integer without a cast [enabled by default] drivers/mtd/nand/docg4.c:1327:2: error: implicit declaration of function 'iounmap' [-Werror=implicit-function-declaration] which is caused by the missing implementations on UML. This patch adds this missing HAS_IOMEM dependency and prevents the driver from being build on platforms with no HAS_IOMEM Signed-off-by: Peter Huewe <peterhuewe@gmx.de> Acked-by: Mike Dunn <mikedunn@newsguy.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: gpmi: initialize the timing registers only one timeHuang Shijie
The current code initializes the timing registers at very time we call the gpmi_begin(). This really wastes the cpu cycles. Add a new flag to let the gpmi driver initializes the timing registers only one time. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: gpmi: add EDO feature for imx6qHuang Shijie
When the frequency on the nand chip pins is above 33MHz, the nand EDO(extended Data Out) timing could be applied. The GPMI implements a Feedback read strobe to sample the read data in the EDO timing mode. This patch adds the EDO feature for the gpmi-nand driver. For some onfi nand chips, the mode 4 is the fastest; while for other onfi nand chips, the mode 5 is the fastest. This patch only adds the support for the fastest asynchronous timing mode. So this patch only supports the mode 4 and mode 5. I tested several Micron's ONFI nand chips with EDO enabled, take Micron MT29F32G08MAA for example (in mode 5, 100MHz): 1) The test result BEFORE we add the EDO feature: ================================================= mtd_speedtest: MTD device: 2 mtd_speedtest: MTD device size 209715200, eraseblock size 524288, page size 4096, count of eraseblocks 400, pages per eraseblock 128, OOB size 218 ....................................... mtd_speedtest: testing eraseblock read speed mtd_speedtest: eraseblock read speed is 3632 KiB/s ....................................... mtd_speedtest: testing page read speed mtd_speedtest: page read speed is 3554 KiB/s ....................................... mtd_speedtest: testing 2 page read speed mtd_speedtest: 2 page read speed is 3592 KiB/s ....................................... ================================================= 2) The test result AFTER we add the EDO feature: ================================================= mtd_speedtest: MTD device: 2 mtd_speedtest: MTD device size 209715200, eraseblock size 524288, page size 4096, count of eraseblocks 400, pages per eraseblock 128, OOB size 218 ....................................... mtd_speedtest: testing eraseblock read speed mtd_speedtest: eraseblock read speed is 19555 KiB/s ....................................... mtd_speedtest: testing page read speed mtd_speedtest: page read speed is 17319 KiB/s ....................................... mtd_speedtest: testing 2 page read speed mtd_speedtest: 2 page read speed is 18339 KiB/s ....................................... ================================================= 3) The read data performance is much improved by more then 5 times. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: gpmi: do not set the default values for the extra clocksHuang Shijie
The default frequencies of the extra clocks are 200MHz. The current code sets the extra clocks to 44.5MHz. When i add the EDO feature to gpmi, i have to revert the extra clocks to 200MHz. So it is better that we do not set the default values for the extra clocks. The driver runs well even when we do not set the default values for extra clocks. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: gpmi: simplify the DLL setting codeHuang Shijie
The setting DLL code is a little mess. Just simplify the code and the comments. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: gpmi: add a new field for HW_GPMI_CTRL1Huang Shijie
add the WRN_DLY_SEL field for HW_GPMI_CTRL1. This field is used as delay for gpmi write strobe. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: gpmi: do not get the clock frequency in gpmi_begin()Huang Shijie
The current code will gets the clock frequency which is used by gpmi_nfc_compute_hardware_timing(). It makes the code a little mess. So move the `get clock frequency` code to the gpmi_nfc_compute_hardware_timing() itself. This makes the code tidy and clean. This patch also uses the macro NSEC_PER_SEC to replace the `1000000000`. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: gpmi: add a new field for HW_GPMI_TIMING1Huang Shijie
The gpmi_nfc_compute_hardware_timing{} should contains all the fields setting for gpmi timing registers. It already contains the fields for HW_GPMI_TIMING0 and HW_GPMI_CTRL1. So it is better to add a new field setting for HW_GPMI_TIMING1 in this data structure. This makes the code more clear in logic. This patch also changes some comments to make the code more readable. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: add helpers to get the supportted ONFI timing modeHuang Shijie
add onfi_get_async_timing_mode() to get the supportted asynchronous timing mode. add onfi_get_sync_timing_mode() to get the supportted synchronous timing mode. Also add the neccessary macros : the timing modes. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: add helpers to set/get features for ONFI nandHuang Shijie
Add the set-features(0xef)/get-features(0xee) helpers for ONFI nand. Also add the necessary macros. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: fsl_ifc_nand: fix sparse warningsKim Phillips
drivers/mtd/nand/fsl_ifc_nand.c:196:34: warning: cast removes address space of expression [sparse] drivers/mtd/nand/fsl_ifc_nand.c:196:34: warning: incorrect type in initializer (different address spaces) [sparse] drivers/mtd/nand/fsl_ifc_nand.c:196:34: expected unsigned int [noderef] [usertype] <asn:2>*mainarea [sparse] drivers/mtd/nand/fsl_ifc_nand.c:196:34: got unsigned int [usertype] *<noident> [sparse] ... Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: nandsim: bugfix: fail if overridesize is too bigRichard Genoud
If override size is too big, the module was actually loaded instead of failing, because retval was not set. This lead to memory corruption with the use of the freed structs nandsim and nand_chip. Cc: stable@vger.kernel.org Signed-off-by: Richard Genoud <richard.genoud@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: docg4: ecc.read_page() returns 0 on uncorrectable errorsMike Dunn
Currently the docg4's ecc.read_page() method returns -EBADMSG when uncorrectable bitflips occur. This is wrong; 0 should be returned in this case. An error code should only be returned by this method in the case of a hardware error (probably -EIO). Signed-off-by: Mike Dunn <mikedunn@newsguy.com> Acked-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: nand: use NAND_BBT_SCAN_MAXBLOCKSRichard Genoud
In nand_bbt.c, a hardcoded value was used instead of the define meant for that, so we use the define. There's no functional change. Signed-off-by: Richard Genoud <richard.genoud@gmail.com> Acked-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: remove bcmring NAND driverChristian Daudt
This driver is being removed as part of the cleanup of the bcmring SoC from mainline as it is no longer maintained. Signed-off-by: Christian Daudt <csd@broadcom.com> Reviewed-by: Jiandong Zheng <jdzheng@broadcom.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: nand: expand description of read_page method in comment headerMike Dunn
In the absence of any formal documentation of the nand interface, I thought this patch to the header file might be helpful. Signed-off-by: Mike Dunn <mikedunn@newsguy.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: nand: clk: preparation for switch to common clock frameworkm-karicheri2@ti.com
As a first step towards migrating davinci platforms to use common clock framework, replace all instances of clk_enable() with clk_prepare_enable() and clk_disable() with clk_disable_unprepare(). Until the platform is switched to use the CONFIG_HAVE_CLK_PREPARE Kconfig variable, this just adds a might_sleep() call and would work without any issues. This will make it easy later to switch to common clk based implementation of clk driver from DaVinci specific driver. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Reviewed-by: Mike Turquette <mturquette@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: mtd_nandecctest: add double bit error detection testsAkinobu Mita
This adds the double bit error detection test cases listed below: * Prepare data block with double bit error and ECC data without corruption, and verify that the uncorrectable error is detected by __nand_correct_data(). * Prepare data block with single bit error and ECC data with single bit error, and verify that the uncorrectable error is detected. * Prepare data block without corruption and ECC data with double bit error, and verify that the uncorrectable error is detected. Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: mtd_nandecctest: add single bit error correction testAkinobu Mita
This adds the single bit error correction test case listed below: Prepare data block without corruption and ECC data with single bit error, and verify that the data block is preserved by __nand_correct_data(). Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: mtd_nandecctest: add no corruption testAkinobu Mita
This adds no corruptin test case listed below: Prepare data block and ECC data with no corruption, and verify that the data block is preserved by __nand_correct_data() Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: mtd_nandecctest: rewrite the test routineAkinobu Mita
This rewrites the entire test routine in order to make it easy to add more tests by later changes and minimize duplication of each tests as much as possible. Now that each test is described by the members of struct nand_ecc_test: - name: descriptive testname - prepare: function to prepare data block and ecc with artifical corruption - verify: function to verify the result of correcting data block Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: mtd_nandecctest: support injecting bit error for ecc codeAkinobu Mita
Currently inject_single_bit_error() is used to inject single bit error into randomly selected bit position of the 256 or 512 bytes data block. Later change will add tests which inject bit errors into the ecc code. Unfortunately, inject_single_bit_error() doesn't work for the ecc code which is not a multiple of sizeof(unsigned long). Because bit fliping at random position is done by __change_bit(). For example, flipping bit position 0 by __change_bit(0, addr) modifies 3rd byte (32bit) or 7th byte (64bit) on big-endian systems. Using little-endian version of bitops can fix this issue. But little-endian version of __change_bit is not yet available. So this defines __change_bit_le() locally in a similar fashion to asm-generic/bitops/le.h and use it. Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: tests: test for multi-bit error correctionIwo Mergler
This tests ECC biterror recovery on a single NAND page. Mostly intended to test ECC hardware and low-level NAND driver. There are two test modes: 0 - artificially inserting bit errors until the ECC fails This is the default method and fairly quick. It should be independent of the quality of the FLASH. 1 - re-writing the same pattern repeatedly until the ECC fails. This method relies on the physics of NAND FLASH to eventually generate '0' bits if '1' has been written sufficient times. Depending on the NAND, the first bit errors will appear after 1000 or more writes and then will usually snowball, reaching the limits of the ECC quickly. The test stops after 10000 cycles, should your FLASH be exceptionally good and not generate bit errors before that. Try a different page offset in that case. Please note that neither of these tests will significantly 'use up' any FLASH endurance. Only a maximum of two erase operations will be performed. Signed-off-by: Iwo Mergler <Iwo.Mergler@netcommwireless.com.au> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: cmdlinepart: make the partitions rule more strictShmulik Ladkani
Huang Shijie <shijie8@gmail.com> explains: Assume we have a 1GiB(8Gib) NAND chip, and we set the partitions in the command line like this: #gpmi-nand:100m(boot),100m(kernel),1g(rootfs) In this case, the partition truncating occurs. The current code will get the following result: ---------------------------------- root@freescale ~$ cat /proc/mtd dev: size erasesize name mtd0: 06400000 00040000 "boot" mtd1: 06400000 00040000 "kernel" ---------------------------------- It is obvious that we lost the truncated partition `rootfs` which should be 824MiB in this case. Also, forbid 0-sized partitions. Signed-off-by: Shmulik Ladkani <shmulik.ladkani@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: nand/gpio: Convert to module_platform_driver()Sachin Kamat
module_platform_driver simplifies the code by eliminating module_init and module_exit calls. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: mxc_nand: Adapt the clock name to the new clock frameworkFabio Estevam
With the new i.mx clock framework the mxc_nand clock is registered as: clk_register_clkdev(clk[nfc_gate], NULL, "mxc_nand");0") So we do not need to pass "nfc" string and can use NULL instead. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2012-09-29mtd: mxc_nand: Convert to module_platform_driver()Fabio Estevam
Using module_platform_driver() makes the code smaller and cleaner. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
generated by cgit (git 2.34.1) at 2025-09-23 12:31:41 +0000