summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2017-09-26drm/amdgpu:use formal register to trigger hdp invalidateMonk Liu
Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amdgpu:hdp flush should be put it initializedMonk Liu
Signed-off-by: Monk Liu <Monk.Liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amdgpu:insert TMZ_BEGINMonk Liu
FRAME_CONTROL(begin) is needed for vega10 due to ucode logic change, it can fix some CTS random fail under gfx preemption enabled mode. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amdgpu/sriov:don't load psp fw during gpu resetMonk Liu
At least for SRIOV we found reload PSP fw during gpu reset cause PSP hang. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amdgpu/sriov:move in_reset to adev and renameMonk Liu
currently in_reset is only used in sriov gpu reset, and it will be used for other non-gfx hw component later, like PSP, so move it from gfx to adev and rename to in_sriov_reset make more sense. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amdgpu:no kiq in IHMonk Liu
Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amdgpu/sriov:fix missing error handlingMonk Liu
Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amdgpu: Add GPU reset functionality for Vega10Ken Wang
V2 Signed-off-by: Ken Wang <Ken.Wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/ttm: Remove TTM dma tracepoint since it's not required anymoreTom St Denis
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/amdgpu: remove usage of ttm traceTom St Denis
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/amdgpu: add support for iova_to_phys to replace TTM trace (v5)Tom St Denis
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (v2): Add domain to iova debugfs (v3): Add true read/write methods to access system memory of pages mapped to the device (v4): Move get_domain call out of loop and return on error (v5): Just use kmap/kunmap
2017-09-26drm/amd/amdgpu: Fold TTM debugfs entries into array (v2)Tom St Denis
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (v2): add domains and avoid strcmp
2017-09-26drm/amdgpu: fix checkpatch.pl warning to amdgpu_drv.cRex Zhu
fix checkpatch.pl WARNING: Prefer 'unsigned int' to bare use of 'unsigned' Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amdgpu: remove the clearance of vce 4.0 interrupt maskLeo Liu
Requested by SRIOV, the clearance of the bit moved into firmware Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amdgpu/sdma3: set wptr shadow atomicallyXiangliang.Yu
Port it from sdma4 for wptr polling usage. Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amdgpu/sdma3: Enable sdma wptr polling for SRIOVXiangliang.Yu
When hypervisor triggering FLR for one of VFs, need to enable sdma wptr polling to avoid missing wptr update if enabling doorbell. Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/ttm: cleanup ttm_page_alloc_dma.cChristian König
Remove unused defines and variables. Also stop computing the gfp_flags when they aren't used. No intended functional change. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amdgpu: Track pending retry faults in IH and VM (v2)Felix Kuehling
IH tracks pending retry faults in a hash table for fast lookup in interrupt context. Each VM has a short FIFO of pending VM faults for processing in a bottom half. The IH prescreening stage adds retry faults and filters out repeated retry interrupts to minimize the impact of interrupt storms. It's the VM's responsibility remove pending faults once they are handled. For now this is only done when the VM is destroyed. v2: - Made the hash table smaller and the FIFO longer. I never want the FIFO to fill up, because that would make prescreen take longer. 128 pending page faults should be enough to keep migrations busy. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christian.koenig@amd.com> (v1) Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd: Closed hash table with low overhead (v2)Felix Kuehling
This adds a statically sized closed hash table implementation with low memory and CPU overhead. The API is inspired by kfifo. Storing, retrieving and deleting data does not involve any dynamic memory management, which makes it ideal for use in interrupt context. Static memory usage per entry comprises a 32 or 64 bit hash key, two bits for occupancy tracking and the value size stored in the table. No list heads or pointers are needed. Therefore this data structure should be quite cache-friendly, too. It uses linear probing and lazy deletion. During lookups free space is reclaimed and entries relocated to speed up future lookups. v2: squash in do_div and _BITOPS_LONG_SHIFT fixes Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amdgpu: Add prescreening stage in IH processing (v2)Felix Kuehling
To filter out high-frequency interrupts that can be safely ignored. v2: squash in trivial typo fix for si (Alex) Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amdkfd: Use PASID manager from KGDFelix Kuehling
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amdkfd: Separate doorbell allocation from PASIDFelix Kuehling
PASID management is moving into KGD. Limiting the PASID range to the number of doorbell pages is no longer practical. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/radeon: Add PASID manager for KFDFelix Kuehling
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amdgpu: Add PASID managementFelix Kuehling
Allows assigning a PASID to a VM for identifying VMs involved in page faults. The global PASID manager is also exported in the KFD interface so that AMDGPU and KFD can share the PASID space. PASIDs of different sizes can be requested. On APUs, the PASID size is deterined by the capabilities of the IOMMU. So KFD must be able to allocate PASIDs in a smaller range. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amdgpu: Fix error handling in amdgpu_vm_initFelix Kuehling
Make sure vm->root.bo is not left reserved if amdgpu_bo_kmap fails. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/powerplay: Simplify smu7_voting_clients()Rex Zhu
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amdgpu: add powerplay support for CI asicsRex Zhu
currently, for CI asics, use dpm by default, amdgpu.dpm=-1. when set amdgpu.dpm=1, enable powplay. when set amdgpu.dpm=0, disable both dpm and powerplay. when powerplay is stable on CI asics, ci_dpm will be removed. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/powerplay: Add support for CI asics to hwmgrRex Zhu
Add support for CI asics (Bonaire, Hawaii) to the powerplay hwmgr Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/powerplay: Add support functions for CI to ppatomctrl.cRex Zhu
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/powerplay: refine dmesg info under powerplayRex Zhu
Use pr_debug to prevent spamming unimportant dmesg. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/powerplay: fix set target TDP error on tonga/icelandRex Zhu
ConfigurableTDP do not exist from Fiji. so only use in previous ASIC. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amd/powerplay: add CI asics support to smumgr (v3)Rex Zhu
This ports support for CI asics (Bonaire, Hawaii) to the powerplay smumgr v2: warning fix (Alex) v3: squash in fix for thermal (Tom) Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/i915: Compact device info access by a small re-orderingTvrtko Ursulin
More effort to align members on 4-byte boundary helps with code size a tiny bit: text data bss dec hex filename -1460454 60014 3656 1524124 17419c drivers/gpu/drm/i915/i915.ko +1460254 60014 3656 1523924 1740d4 drivers/gpu/drm/i915/i915.ko Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170920092701.17963-3-tvrtko.ursulin@linux.intel.com
2017-09-26drm/i915: Add IS_PLATFORM macroTvrtko Ursulin
This will allow some code re-organization in a following patch. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170920092701.17963-2-tvrtko.ursulin@linux.intel.com
2017-09-26drm/i915/selftests: Try to recover from a wedged GPU during reset testsChris Wilson
If we see the seqno stop progressing, we abandon the test for fear that the GPU died following the reset. However, during test teardown we still wait for the GPU to idle before continuing, but we have already confirmed that the GPU is dead. Furthermore, since we are inside a reset test, we have disabled the hangchecker, and so there is no safety net and we wait indefinitely. Detect the stuck GPU and declare it wedged as a state of emergency so we can escape. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jari Tahvanainen <jari.tahvanainen@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170915130929.18892-1-chris@chris-wilson.co.uk Tested-by: Jari Tahvanainen <jari.tahvanainen@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
2017-09-26drm/i915/huc: Reorganize HuC authenticationSagar Arun Kamble
Prepared intel_auth_huc to separate HuC specific functionality from GuC send action. Created new header intel_huc.h to group HuC specific declarations. v2: Changed argument preparation for AUTHENTICATE_HUC. s/intel_auth_huc/intel_huc_auth. Deferred creation of intel_huc.h to later patch. v3: Rebase as intel_guc.h is removed. Added param description to intel_huc_auth. (Michal) v4: Rebase as intel_guc.h is added again. :) v5: Rebase w.r.t removal of GuC code restructuring. v6-v7: Rebase. v8: Tagged subject as drm/i915/huc. (Michal Wajdeczko) Added kernel-doc description to intel_huc_auth and intel_guc_auth_huc. s/dev_priv/i915 and removed unnecessary variable offset. (Joonas) v9: Rebase. Had conflict with i915_modparams change. Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Michał Winiarski <michal.winiarski@intel.com> Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1506410236-17926-1-git-send-email-sagar.a.kamble@intel.com
2017-09-26drm/i915: Fix default values of some modparamsMichal Wajdeczko
Members should be initialized with values of matching types. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170925105008.46060-3-michal.wajdeczko@intel.com
2017-09-26drm/i915: Extend I915_PARAMS_FOR_EACH with default member valueMichal Wajdeczko
By combining default value into helper macro we can initialize modparams struct in the same automatic way as it was declared. This will initialize members in the same order as declared and additionally will disallow declaring new member without proper default value for it. v2: make MEMBER macro more robust (Joonas) Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170925105008.46060-2-michal.wajdeczko@intel.com
2017-09-26drm/i915: Make I915_PARAMS_FOR_EACH macro more flexibleMichal Wajdeczko
We should not add trailing ; after each member to allow other than statements-style uses of this helper macro. While here s/func/param for clarity. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170925105008.46060-1-michal.wajdeczko@intel.com
2017-09-26drm/i915: Enable scanline read based on frame timestampsUma Shankar
For certain platforms on certain encoders, timings are driven from port instead of pipe. Thus, we can't rely on pipe scanline registers to get the timing information. Some cases scanline register read will not be functional. This is causing vblank evasion logic to fail since it relies on scanline, causing atomic update failure warnings. This patch uses pipe framestamp and current timestamp registers to calculate scanline. This is an indirect way to get the scanline. It helps resolve atomic update failure for gen9 dsi platforms. v2: Addressed Ville and Daniel's review comments. Updated the register MACROs, handled race condition for register reads, extracted timings from the hwmode. Removed the dependency on crtc->config to get the encoder type. v3: Made get scanline function generic v4: Addressed Ville's review comments. Added a flag to decide timestamp based scanline reporting. Changed 64bit variables to u32 v5: Adressed Ville's review comments. Put the scanline compute function at the place of caller. Removed hwmode flags from uapi and used a local i915 data structure instead. v6: Used vblank hwmode to get the timings. v7: Fixed sparse warnings, indentation and minor review comments. v8: Limited this only for Gen9 DSI. Credits-to: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1506347761-4201-1-git-send-email-vidya.srinivas@intel.com
2017-09-25drm/i915/execlists: Microoptimise execlists_cancel_port_request()Chris Wilson
Just rearrange the code slightly to trim the number of iterations required. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20170925124929.16974-1-chris@chris-wilson.co.uk Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
2017-09-25drm/i915: Don't rmw PIPESTAT enable bitsVille Syrjälä
i830 seems to occasionally forget the PIPESTAT enable bits when we read the register. These aren't the only registers on i830 that have problems with RMW, as reading the double buffered plane registers returns the latched value rather than the last written value. So something similar is perhaps going on with PIPESTAT. This corruption results on vblank interrupts occasionally turning off on their own, which leads to vblank timeouts and generally a stuck display subsystem. So let's not RMW the pipestat enable bits, and instead use the cached copy we have around. Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170914151731.5034-1-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
2017-09-25drm/i915: Speed up DMC firmware loadingDavid Weinehall
Currently we're doing: 1. acquire lock 2. write word to hardware 3. release lock 4. repeat from 1 to load the DMC firmware. Due to the cost of acquiring/releasing a lock, and the size of the DMC firmware, this slows down DMC loading a lot. This patch simply acquires the lock, writes the entire firmware, then releases the lock. Testing shows resume speedups in the order of 10ms on platforms with DMC firmware (GEN9+). v2: Per feedback from Chris & Ville there's no need to do the whole forcewake dance, so lose that bit (Chris, Ville) v3: Actually send the new version of the patch... v4: Don't acquire the uncore lock. Disable preempt. (Chris) Signed-off-by: David Weinehall <david.weinehall@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170905131050.11655-1-david.weinehall@linux.intel.com Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2017-09-25drm/i915/dp: Remove useless debug about TPS3 supportDhinakaran Pandiyan
We already print training pattern used during link training and also print if the source or sink does not support TPS3 for HBR2 link rates, see intel_dp_training_pattern(). Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170918222141.4674-5-dhinakaran.pandiyan@intel.com
2017-09-25drm/i915/dp: Fix buffer size for sink_irq_esi readPandiyan, Dhinakaran
The buffer size defined is 16 bytes whereas only 14 bytes are read. Add a macro to avoid this discrepancy. Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Reviewed-by: James Ausmus <james.ausmus@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170918222141.4674-3-dhinakaran.pandiyan@intel.com
2017-09-25drm/i915/mst: Print active mst links after updatePandiyan, Dhinakaran
Both mst_disable_dp and mst_post_disable_dp print number of active links before the variable has been updated. Move the print statement in mst_disable_dp after the decrement so that the printed values indicate the disabing of a mst connector. Also, add some text to clarify what we are printing. Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Reviewed-by: James Ausmus <james.ausmus@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170918222141.4674-2-dhinakaran.pandiyan@intel.com
2017-09-25drm/i915/mst: Debug log connector name in destroy_connector()Pandiyan, Dhinakaran
Print connector name in destroy_connect() and this doesn't add any extra lines to dmesg. The debug macro has been moved before the unregister call so that we don't lose the connector name and id. Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Reviewed-by: James Ausmus <james.ausmus@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170918222141.4674-1-dhinakaran.pandiyan@intel.com
2017-09-25drm/i915/lrc: Skip no-op per-bb buffer on gen9Chris Wilson
Since we inherited the context image setup from gen8 which needed a per-bb workaround (for GPGPU), we are submitting an empty per-bb buffer on gen9. Now that we can skip adding the buffer to the context image, remove the dangling per-bb. This slightly improves execution latency, most notably on an idle engine. References: https://bugs.freedesktop.org/show_bug.cgi?id=87725 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170921135444.27330-2-chris@chris-wilson.co.uk Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
2017-09-25drm/i915/lrc: Only enable per-context and per-bb buffers if setChris Wilson
The per-context and per-batch workaround buffers are optional, yet we tell the GPU to execute them even if they contain no instructions. Doing so incurs the dispatch latency, which we can avoid if we don't ask the GPU to execute the no-op buffers. Allow ourselves to skip setup of empty buffer, and then to only enable non-empty buffers in the context image. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170921135444.27330-1-chris@chris-wilson.co.uk Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
2017-09-25drm/i915: Make execlist port count variableMika Kuoppala
As we emulate execlists on top of the GuC workqueue, it is not restricted to just 2 ports and we can increase that number arbitrarily to trade-off queue depth (i.e. scheduling latency) against pipeline bubbles. v2: rebase. better commit msg (Chris) v3: rebase Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20170922124307.10914-5-mika.kuoppala@intel.com
generated by cgit (git 2.34.1) at 2025-09-11 07:25:55 +0000