summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2020-09-15drm/msm/dp: add debugfs support to DP driverAbhinav Kumar
To prepare the MSM DP driver for running video pattern compliance tests introduce debugfs module for it. Changes in v2: rebase on top of latest patchset of dependency Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-15drm/msm/dp: wait for audio notification before disabling clocksAbhinav Kumar
In the current implementation, there is a very small window for the audio side to safely signal the hdmi_code_shutdown() before the clocks are disabled. Add some synchronization between the DP display and DP audio module to safely disable the clocks to avoid unclocked access from audio side. In addition, audio side can open the sound card even if DP monitor is not connected. Avoid programming hardware registers in this case and bail out early. Changes in v4: - removed some leftover prints Changes in v5: - fix crash when user tries to play audio in suspended state Changes in v6: - rebased on top of latest patchset of dependency Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-15drm/msm/dp: signal the hotplug disconnect in the event handlerAbhinav Kumar
Signal the hotplug disconnect event to the audio side in the event handler so that they are notified earlier and have more time to process the disconnect event. Changes in v2: none Changes in v3: none Changes in v4: rebase on top of latest patchset of dependency Changes in v5: rebase on top of latest patchset of dependency Changes in v6: none Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-15drm/msm/dp: add hook_plugged_cb hdmi-codec op for MSM DP driverAbhinav Kumar
Add the hook_plugged_cb op for the MSM DP driver to signal connect and disconnect events to the hdmi-codec driver which in-turn shall notify the audio subsystem to start a new or teardown an existing session. Changes in v2: none Changes in v3: none Changes in v4: rebase on top of latest patchset of dependency Changes in v5: rebase on top of latest patchset of dependency Changes in v6: none Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-15drm/msm/dp: add audio support for Display Port on MSMAbhinav Kumar
Introduce audio support for Display Port on MSM chipsets. This change integrates DP audio sub-module with the main Display Port platform driver. In addition, this change leverages hdmi_codec_ops to expose the operations to the audio driver. Changes in v2: fix up a compilation issue on drm-next branch Changes in v3: none Changes in v4: none Changes in v5: none Changes in v6: rebase on top of latest patchset of dependency Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-15drm/msm/dp: store dp_display in the driver dataAbhinav Kumar
Store the dp_display in the platform driver data instead of the dp_display_private. This is required to allow other sub-modules to reuse the platform driver data. Changes in v3: none Changes in v4: none Changes in v5: none Changes in v6: rebase on top of latest patchset of dependency Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-15drm/msm/dp: Add DP compliance tests on Snapdragon ChipsetsKuogee Hsieh
add event thread to execute events serially from event queue. Also timeout mode is supported which allow an event be deferred to be executed at later time. Both link and phy compliant tests had been done successfully. Changes in v2: -- Fix potential deadlock by removing redundant connect_mutex -- Check and enable link clock during modeset -- Drop unused code and fix function prototypes. -- set sink power to normal operation state (D0) before DPCD read Changes in v3: -- push idle pattern at main link before timing generator off -- add timeout handles for both connect and disconnect Changes in v4: -- add ST_SUSPEND_PENDING to handles suspend/modeset test operations -- clear dp phy aux interrupt status when ERR_DPPHY_AUX error -- send segment addr during edid read -- clear bpp depth before MISC register write Changes in v5: -- add ST_SUSPENDED to fix crash at resume Changes in v6: -- at msm_dp_display_enable() do not return until resume_done to avoid kms commit timeout Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-15drm/msm/dp: Add Display Port HPD featureTanmay Shah
Configure HPD registers in DP controller and enable HPD interrupt. Add interrupt to handle HPD connect and disconnect events. Changes in v8: None Signed-off-by: Tanmay Shah <tanmay@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-15drm/msm/dpu: add display port support in DPUJeykumar Sankaran
Add display port support in DPU by creating hooks for DP encoder enumeration and encoder mode initialization. changes in v2: - rebase on [2] (Sean Paul) - remove unwanted error checks and switch cases (Jordan Crouse) [1] https://lwn.net/Articles/768265/ [2] https://lkml.org/lkml/2018/11/17/87 changes in V3: -- Moved this change as part of the DP driver changes. -- Addressed compilation issues on the latest code base. Changes in v6: -- Fix checkpatch.pl warning Changes in v7: Remove depends-on tag from commit message. Changes in v8: None Changes in v9: None Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org> Signed-off-by: Vara Reddy <varar@codeaurora.org> Signed-off-by: Tanmay Shah <tanmay@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-15drm/msm/dp: add support for DP PLL driverChandan Uddaraju
Add the needed DP PLL specific files to support display port interface on msm targets. The DP driver calls the DP PLL driver registration. The DP driver sets the link and pixel clock sources. Changes in v2: -- Update copyright markings on all relevant files. -- Use DRM_DEBUG_DP for debug msgs. Changes in v4: -- Update the DP link clock provider names Changes in V5: -- Addressed comments from Stephen Boyd, Rob clark. Changes in V6: -- Remove PLL as separate driver and include PLL as DP module -- Remove redundant clock parsing from PLL module and make DP as clock provider -- Map USB3 DPCOM and PHY IO using hardcoded register address and move mapping form parser to PLL module -- Access DP PHY modules from same base address using offsets instead of deriving base address of individual module from device tree. -- Remove dp_pll_10nm_util.c and include its functionality in dp_pll_10nm.c -- Introduce new data structures private to PLL module Changes in v7: -- Remove DRM_MSM_DP_PLL config from Makefile and Kconfig -- Remove set_parent from determin_rate API -- Remove phy_pll_vco_div_clk from parent list -- Remove flag CLK_DIVIDER_ONE_BASED -- Remove redundant cell-index property parsing Changes in v8: -- Unregister hardware clocks during driver cleanup Changes in v9: -- Remove redundant Kconfig option DRM_MSM_DP_10NM_PLL Changes in v10: -- Limit 10nm PLL function scope Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org> Signed-off-by: Vara Reddy <varar@codeaurora.org> Signed-off-by: Tanmay Shah <tanmay@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-15drm/msm/dp: add displayPort driver supportChandan Uddaraju
Add the needed displayPort files to enable DP driver on msm target. "dp_display" module is the main module that calls into other sub-modules. "dp_drm" file represents the interface between DRM framework and DP driver. Changes in v12: -- Add support of pm ops in display port driver -- Clear bpp depth bits before writing to MISC register -- Fix edid read Previous Change log: https://lkml.kernel.org/lkml/20200818051137.21478-3-tanmay@codeaurora.org/ Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org> Signed-off-by: Vara Reddy <varar@codeaurora.org> Signed-off-by: Tanmay Shah <tanmay@codeaurora.org> Co-developed-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> Co-developed-by: Kuogee Hsieh <khsieh@codeaurora.org> Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org> Co-developed-by: Guenter Roeck <groeck@chromium.org> Signed-off-by: Guenter Roeck <groeck@chromium.org> Co-developed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-15drm: add constant N value in helper fileChandan Uddaraju
The constant N value (0x8000) is used by i915 DP driver. Define this value in dp helper header file to use in multiple Display Port drivers. Change i915 driver accordingly. Change in v6: Change commit message Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org> Signed-off-by: Vara Reddy <varar@codeaurora.org> Signed-off-by: Tanmay Shah <tanmay@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-15drm/msm: Get rid of the REG_ADRENO offsetsJordan Crouse
As newer GPU families are added it makes less sense to maintain a "generic" version functions for older families. Move adreno_submit() and get_rptr() into the target specific code for a2xx, a3xx and a4xx. Add a parameter to adreno_flush to pass the target specific WPTR register instead of relying on the generic register. All of this gets rid of the last of the REG_ADRENO offsets so remove all all the register definitions and infrastructure. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-15drm/msm: a6xx: Use WHERE_AM_I for eligible targetsJordan Crouse
Support the WHERE_AM_I opcode for the A618, A630 and A640 GPUs if the microcode supports it. The WHERE_AM_I opcode allows the RPTR shadow to be updated in priviliged memory which protects the shadow from being read or written from user submissions. A650 already supports extended APRIV have built in hardware support for to access privilged memory from the CP and can go back to using the hardware RPTR shadow feature. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-15drm/msm: Allow a5xx to mark the RPTR shadow as privilegedJordan Crouse
Newer microcode versions have support for the CP_WHERE_AM_I opcode which allows the RPTR shadow memory to be marked as privileged to protect it from corruption. Move the RPTR shadow into its own buffer and protect it it if the current microcode version supports the new feature. We can also re-enable preemption for those targets that support CP_WHERE_AM_I. Start out by preemptively assuming that we can enable preemption and disable it in a5xx_hw_init if the microcode version comes back as too old. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-09-15drm/i915: Nuke pointless variableVille Syrjälä
No point in assigning the function return value to a local variable if we're just going to use it the one time. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200630215601.28557-13-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2020-09-15drm/i915: Introduce intel_hpd_hotplug_irqs()Ville Syrjälä
Introduce intel_hpd_hotplug_irqs() as a partner to intel_hpd_enabled_irqs(). There's no need to care about the encoders which we're not exposing, so we can avoid hardcoding the masks in various places. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200630215601.28557-12-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2020-09-15drm/i915: Introduce HPD_PORT_TC<n>Ville Syrjälä
Make a clean split between hpd pins for DDI vs. TC. This matches how the actual hardware is split. And with this we move the DDI/PHY->HPD pin mapping into the encoder init instead of having to remap yet again in the interrupt code. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200630215601.28557-11-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2020-09-15drm/i915: Move hpd_pin setup to encoder initVille Syrjälä
Currently DP/HDMI/DDI encoders init their hpd_pin from the connector init. Let's move it to the encoder init so that we don't need to add platform specific junk to the connector init (which is shared by all g4x+ platforms). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200630215601.28557-10-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2020-09-15drm/i915: Split icp_hpd_detection_setup() into ddi vs. tc partsVille Syrjälä
No reason to stuff both DDI and TC port handling into the same function. Split it into two. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200630215601.28557-9-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2020-09-15drm/i915: Configure GEN11_{TBT,TC}_HOTPLUG_CTL for ports TC5/6Ville Syrjälä
gen11_hpd_detection_setup() is missing ports TC5/6. Add them. TODO: Might be nice to only enable the hpd detection logic for ports we actually have. Should be rolled out for all platforms if/when done... Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200630215601.28557-8-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2020-09-15drm/i915: Nuke the redundant TC/TBT HPD bit definesVille Syrjälä
We have nice parametrized GEN11_{TC,TBT}_HOTPLUG() so nuke the overlapping defines. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200630215601.28557-7-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2020-09-15drm/i915: Add VBT AUX CH H and IVille Syrjälä
As with everything else VBT can now specify AUX CH H or I. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200630215601.28557-6-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2020-09-15drm/i915: Add VBT DVO ports H and IVille Syrjälä
VBT has ports H and I since version 217. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200630215601.28557-5-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2020-09-15drm/i915: Add AUX_CH_{H,I} power domain handlingVille Syrjälä
AUX CH H/I need their power domains too. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200630215601.28557-4-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2020-09-15drm/i915: Add PORT_{H,I} to intel_port_to_power_domain()Ville Syrjälä
We need to go up to PORT_I (aka. TC6) these days. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200630215601.28557-3-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2020-09-15drm/i915: Add more AUX CHs to the enumVille Syrjälä
We need to go up to AUX_CH_I (aka. AUX CH USBC6) these days. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200630215601.28557-2-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2020-09-15drm/ttm: remove available_cachingChristian König
Instead of letting TTM make an educated guess based on some mask all drivers should just specify what caching they want for their CPU mappings. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/390207/
2020-09-15drm/nouveau: explicitly specify caching to useChristian König
Instead of letting TTM masking the caching bits specify directly what the driver needs. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/390206
2020-09-15drm/ttm: remove default cachingChristian König
As far as I can tell this was never used either and we just always fallback to the order cached > wc > uncached anyway. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/390142/
2020-09-15drm/bridge: ps8640: Rework power state handlingEnric Balletbo i Serra
The get_edid() callback can be triggered anytime by an ioctl, i.e drm_mode_getconnector (ioctl) -> drm_helper_probe_single_connector_modes -> drm_bridge_connector_get_modes -> ps8640_bridge_get_edid Actually if the bridge pre_enable() function was not called before get_edid(), the driver will not be able to get the EDID properly and display will not work until a second get_edid() call is issued and if pre_enable() is called before. The side effect of this, for example, is that you see anything when `Frecon` starts, neither the splash screen, until the graphical session manager starts. To fix this we need to make sure that all we need is enabled before reading the EDID. This means the following: 1. If get_edid() is called before having the device powered we need to power on the device. In such case, the driver will power off again the device. 2. If get_edid() is called after having the device powered, all should just work. We added a powered flag in order to avoid recurrent calls to ps8640_bridge_poweron() and unneeded delays. 3. This seems to be specific for this device, but we need to make sure the panel is powered on before do a power on cycle on this device. Otherwise the device fails to retrieve the EDID. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Tested-by: Bilal Wasim <bwasim.lkml@gmail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200827085911.944899-2-enric.balletbo@collabora.com
2020-09-15drm/i915: Reduce INTEL_DISPLAY_ENABLED to just treat outputs as disconnectedVille Syrjälä
Since the display hardware is all there even when INTEL_DISPLAY_ENABLED return false we have to be capable of shutting it down cleanly so as to not anger the hw. To that end let's reduce the effect of !INTEL_DISPLAY_ENABLE to just treating all outputs as disconnected. Should prevent anyone from automagically enabling any of them, while still allowing us to cleanly shut them down. v2: Put the check into the right place for CRT Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200910164256.25983-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2020-09-15drm/i915: Reduce INTEL_DISPLAY_ENABLED to just removing the outputsVille Syrjälä
Having a mode where the display hardware is present but we try to pretend it isn't just leads to massive headaches when trying to reason what the fallout might be from skipping some random bits of programming. Let's just neuter INTEL_DISPLAY_ENABLED so that we treat the hardware as fully present, except we just don't register any outputs. That's still rather sketchy if the outputs are already enabled when the driver is loaded. I think the simplest solution would be to probe everything as normal and just return disconnected" from all .detect() hooks. That would avoid anything automagically enabling those outputs, but the driver could then shut things down using the normal codepaths. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200909213824.12390-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2020-09-15drm/virtio: add virtio_gpu_cmd_unref_resource error handlingGerd Hoffmann
Usually we wait for the host to complete the unref request, then cleanup the guest-side state of the object in the completion callback. When submitting the unref command failed the completion callback will not be called though, so cleanup right away. Fixes a WARN on stale mm entries on driver shutdown. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20200908070723.6394-4-kraxel@redhat.com
2020-09-15drm/virtio: return virtio_gpu_queue errorsGerd Hoffmann
In case queuing virtio commands fails (can happen when the device got unplugged) pass up the error. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20200908070723.6394-3-kraxel@redhat.com
2020-09-15drm/virtio: use drmm_mode_config_initGerd Hoffmann
Use managed init call to simplify cleanup. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20200908070723.6394-2-kraxel@redhat.com
2020-09-15gpu/drm: ingenic: Add option to mmap GEM buffers cachedPaul Cercueil
Ingenic SoCs are most notably used in cheap chinese handheld gaming consoles. There, the games and applications generally render in software directly into GEM buffers. Traditionally, GEM buffers are mapped write-combine. Writes to the buffer are accelerated, and reads are slow. Application doing lots of alpha-blending paint inside shadow buffers, which is then memcpy'd into the final GEM buffer. On recent Ingenic SoCs however, it is much faster to have a fully cached GEM buffer, in which applications paint directly, and whose data is invalidated before scanout, than having a write-combine GEM buffer, even when alpha blending is not used. Add an optional 'cached_gem_buffers' parameter to the ingenic-drm driver to allow GEM buffers to be mapped fully-cached, in order to speed up software rendering. v2: Use standard noncoherent DMA APIs v3: Use damage clips instead of invalidating full frames v4: Avoid dma_pgprot() which is not exported. Using vm_get_page_prot() is enough in this case. v5: - Avoid calling drm_gem_cma_prime_mmap(). It has the side effect that an extra object reference is obtained, which causes our dumb buffers to never be freed. It should have been drm_gem_cma_mmap_obj(). However, our custom mmap function only differs with one flag, so we can cleanly handle both modes in ingenic_drm_gem_mmap(). - Call drm_gem_vm_close() if drm_mmap_attrs() failed, just like in drm_gem_cma_mmap_obj(). Signed-off-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200912195639.176001-1-paul@crapouillou.net
2020-09-14drm/i915: Drop the drm_atomic_helper_calc_timestamping_constants() callVille Syrjälä
We update the timestamping constants per-crtc explicitly in intel_crtc_update_active_timings(). Furtermore the helper will use uapi.adjusted_mode whereas we want hw.adjusted_mode. Thus let's drop the helper call an rely on what we already have in intel_crtc_update_active_timings(). We can now also drop the hw.adjusted_mode -> uapi.adjusted_mode copy hack that was added to keep the helper from deriving the timestamping constants from the wrong thing. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200907120026.6360-3-ville.syrjala@linux.intel.com Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2020-09-14drm/atomic-helper: Remove the timestamping constant update from ↵Ville Syrjälä
drm_atomic_helper_update_legacy_modeset_state() The timestamping constants have nothing to do with any legacy state so should not be updated from drm_atomic_helper_update_legacy_modeset_state(). Let's make everyone call drm_atomic_helper_calc_timestamping_constants() directly instead of relying on drm_atomic_helper_update_legacy_modeset_state() to call it. @@ expression S; @@ - drm_atomic_helper_calc_timestamping_constants(S); @@ expression D, S; @@ drm_atomic_helper_update_legacy_modeset_state(D, S); + drm_atomic_helper_calc_timestamping_constants(S); v2: Update drm_crtc_vblank_helper_get_vblank_timestamp{,_internal}() docs (Daniel) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200907120026.6360-2-ville.syrjala@linux.intel.com Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2020-09-14drm/atomic-helper: Extract drm_atomic_helper_calc_timestamping_constants()Ville Syrjälä
Put the vblank timestamping constants update loop into its own function. It has no business living inside drm_atomic_helper_update_legacy_modeset_state() so we'll be wanting to move it out entirely. As a first step we'll still call it from drm_atomic_helper_update_legacy_modeset_state(). v2: Drop comment about 'legacy state' in the new function Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200907120026.6360-1-ville.syrjala@linux.intel.com Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2020-09-14drm/i915: Update DRIVER_DATE to 20200914Rodrigo Vivi
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2020-09-14drm/i915: Update DRIVER_DATE to 20200914Rodrigo Vivi
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2020-09-14Merge tag 'gvt-next-2020-09-10' of https://github.com/intel/gvt-linux into ↵Rodrigo Vivi
drm-intel-next-queued gvt-next-2020-09-10 - Cleanup command access flag (Yan) - New workaround cmd access fix (Colin) - MIA reset state fix (Colin) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> From: Zhenyu Wang <zhenyuw@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200910053720.GK28614@zhen-hp.sh.intel.com
2020-09-14Merge drm/drm-next into drm-misc-nextMaxime Ripard
Paul Cercueil needs some patches in -rc5 to apply new patches for ingenic properly. Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-09-14Merge v5.9-rc5 into drm-nextDaniel Vetter
Paul needs 1a21e5b930e8 ("drm/ingenic: Fix leak of device_node pointer") and 3b5b005ef7d9 ("drm/ingenic: Fix driver not probing when IPU port is missing") from -fixes to be able to merge further ingenic patches into -next. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2020-09-14drm/mediatek: Disable tmds on mt2701chunhui dai
Without that patch if you use specific resolutions like 1280x1024, I can see distortion in the output. It seems as if the frequency for updating the pixel of the image is out of sync. For initialization tmds needs to be active, but can be disabled after init to fix blurry display Signed-off-by: chunhui dai <chunhui.dai@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Tested-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2020-09-14drm/i915: Use fb->format->is_yuv for the g4x+ sprite RGB vs. YUV checkVille Syrjälä
g4x+ sprites have an extra cdclk limitation listed for RGB formats. For some random reason I chose to use cpp>=4 as the check for that. While that does actually work let's deobfuscate it by checking for !is_yuv instead. I suspect is_yuv didn't exist way back when I originally write the code. Also drop the duplicate comment. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200206201204.31704-2-ville.syrjala@linux.intel.com Acked-by: Jani Nikula <jani.nikula@intel.com>
2020-09-14drm/i915: Fix g4x+ sprite dotclock limit for upscalingVille Syrjälä
Even if we're not doing downscaling we should account for some of the extra dotclock limitations for g4x+ sprites. In particular we must never exceed the 90% rule, and with RGB that limits actually drops to 80%. So instead of bailing out when upscaling let's clamp the scaling factor appropriately and go through the rest of calculation normally. By luck we already did the full calculations for the 1:1 case. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200206201204.31704-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2020-09-14drm/i915: Nuke CACHE_MODE_0 save/restoreVille Syrjälä
The CACHE_MODE_0 save/restore was added without explanation in commit 1f84e550a870 ("drm/i915 more registers for S3 (DSPCLK_GATE_D, CACHE_MODE_0, MI_ARB_STATE)"). If there are any bits we care about those should be set explicitly during some appropriate init function. Let's assume it's all good and just nuke this magic save/restore. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200908140210.31048-4-ville.syrjala@linux.intel.com Acked-by: Jani Nikula <jani.nikula@intel.com>
2020-09-14drm/i915: Nuke MI_ARB_STATE save/restoreVille Syrjälä
Originally added in commit 1f84e550a870 ("drm/i915 more registers for S3 (DSPCLK_GATE_D, CACHE_MODE_0, MI_ARB_STATE)") to fix some underruns. I suspect that was due to the trickle feed settings getting clobbered during suspend. We've been disabling trickle feed explicitly since commit 20f949670f51 ("drm/i915: Disable trickle feed via MI_ARB_STATE for the gen4") so this magic save/restore should no longer be needed. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200908140210.31048-3-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
generated by cgit (git 2.34.1) at 2025-09-12 15:50:51 +0000