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2020-07-28sched: Remove duplicated tick_nohz_full_enabled() checkMiaohe Lin
In sched_update_tick_dependency() there's two calls that check whether nohz_full is enabled: tick_nohz_full_cpu() does it implicitly, while there's also an explicit call to tick_nohz_full_enabled(). Remove the duplicated, open coded check. [ mingo: Amended the changelog. ] Signed-off-by: Miaohe Lin <linmiaohe@huawei.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://lore.kernel.org/r/1595935075-14223-1-git-send-email-linmiaohe@huawei.com
2020-07-28kprobes: Remove unnecessary module_mutex locking from kprobe_optimizer()Masami Hiramatsu
Since we already lock both kprobe_mutex and text_mutex in the optimizer, text will not be changed and the module unloading will be stopped inside kprobes_module_callback(). The mutex_lock() has originally been introduced to avoid conflict with text modification, at that point we didn't hold text_mutex. But after: f1c6ece23729 ("kprobes: Fix potential deadlock in kprobe_optimizer()") We started holding the text_mutex and don't need the modules mutex anyway. So remove the module_mutex locking. [ mingo: Amended the changelog. ] Suggested-by: Ingo Molnar <mingo@kernel.org> Signed-off-by: Masami Hiramatsu <mhiramat@kernel.org> Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com> Link: https://lore.kernel.org/r/20200728163400.e00b09c594763349f99ce6cb@kernel.org
2020-07-28Merge tag 'v5.8-rc7' into perf/core, to pick up fixesIngo Molnar
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2020-07-28ARM: mstar: Add reboot supportDaniel Palmer
MStar v7 SoCs support reset by writing a magic value to a register in the "pmsleep" area. This adds a node for using the syscon reboot driver to trigger a reset. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28ARM: mstar: Add "pmsleep" node to base dtsiDaniel Palmer
This patch adds a node for the pmsleep area so that other drivers can access registers contained within it. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28ARM: mstar: Add PMUDaniel Palmer
Adds the ARM PMU to the base MStar v7 dtsi. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28ARM: mstar: Adjust IMI size for infinity3Daniel Palmer
infinity3 has 128KB of SRAM at the IMI region. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28ARM: mstar: Adjust IMI size for mercury5Daniel Palmer
mercury5 family chips have 128KB of SRAM in the IMI region. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28ARM: mstar: Adjust IMI size of infinityDaniel Palmer
infinity has 88KB of SRAM at the IMI region. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28ARM: mstar: Add IMI SRAM regionDaniel Palmer
All MStar v7 SoCs have an internal SRAM region that is between 64KB (infinity2m) and 128KB(infinity3, mercury5). The region is always at the same base address and is used for the second stage loader (MStar IPL or u-boot SPL) and will be used for the DDR self-refresh entry code within the kernel eventually. This patch adds a 128KB region to the SoC and the minimum 64KB SRAM region to the base dtsi. Families with more SRAM will override the size in their family level dtsi. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28dt-bindings: arm: mstar: Move existing MStar binding descriptionsDaniel Palmer
Now there is an mstar directory move the existing MStar specific descriptions into that directory. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28dt-bindings: arm: mstar: Add binding details for mstar, pmsleepDaniel Palmer
This adds a YAML description of the pmsleep node used by MStar/SigmaStar Armv7 SoCs. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28xhci: dbgtty: Make some functions staticWei Yongjun
The sparse tool complains as follows: drivers/usb/host/xhci-dbgtty.c:401:5: warning: symbol 'xhci_dbc_tty_register_device' was not declared. Should it be static? drivers/usb/host/xhci-dbgtty.c:452:6: warning: symbol 'xhci_dbc_tty_unregister_device' was not declared. Should it be static? After commit 6ae6470bfa33 ("xhci: dbc: Add a operations structure to access driver functions"), those functions are not used outside of xhci-dbgtty.c, so this commit marks them static. Fixes: 6ae6470bfa33 ("xhci: dbc: Add a operations structure to access driver functions") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Link: https://lore.kernel.org/r/20200727171149.3011-1-weiyongjun1@huawei.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-07-28xhci: dbc: Make function xhci_dbc_ring_alloc() staticWei Yongjun
The sparse tool complains as follows: drivers/usb/host/xhci-dbgcap.c:422:18: warning: symbol 'xhci_dbc_ring_alloc' was not declared. Should it be static? This function is not used outside ofxhci-dbgcap.c, so this commit marks it static. Fixes: ac286428c69f ("xhci: dbc: don't use generic xhci ring allocation functions for dbc.") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Link: https://lore.kernel.org/r/20200727171207.3101-1-weiyongjun1@huawei.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-07-28platform/x86: thinkpad_acpi: add documentation for battery charge controlBarnabás Pőcze
Add a section to the Thinkpad ACPI extras driver documentation detailing the provided features that may be used to modify battery charge related state. As of yet, only charge_control_{start,end}_threshold attributes are supported and documented. Signed-off-by: Barnabás Pőcze <pobrn@protonmail.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-07-28parisc: Replace HTTP links with HTTPS onesAlexander A. Klimov
Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de> Signed-off-by: Helge Deller <deller@gmx.de>
2020-07-28parisc: elf.h: delete a duplicated wordRandy Dunlap
Drop the repeated word "the". Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: "James E.J. Bottomley" <James.Bottomley@HansenPartnership.com> Cc: Helge Deller <deller@gmx.de> Cc: linux-parisc@vger.kernel.org Signed-off-by: Helge Deller <deller@gmx.de>
2020-07-28parisc: Report bad pages as HardwareCorruptedHelge Deller
The /proc/meminfo file reports physically broken memory pages in the HardwareCorrupted field. When the parisc kernel boots report physically bad pages which were recorded in the page deallocation table (PDT) as HardwareCorrupted too. Signed-off-by: Helge Deller <deller@gmx.de>
2020-07-28ARM: mstar: Fix dts filename for 70mai midrive d08Daniel Palmer
Fixes the filename for the 70mai midrive d08 dts. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28ARM: mstar: Add dts for 70mai midrive d08Daniel Palmer
Adds initial support for the 70mai midrive d08 dash camera. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28ARM: mstar: Add dts for msc313(e) based BreadBee boardsDaniel Palmer
BreadBee is an opensource development board based on the MStar msc313(e) SoC. Hardware details, schematics and so on can be found at: https://github.com/breadbee/breadbee Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28ARM: mstar: Add mercury5 series dtsisDaniel Palmer
This adds a family level dtsi for the mercury5 and then a chip level dtsi for the ssc8336n chip. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28ARM: mstar: Add infinity/infinity3 family dtsisDaniel Palmer
This adds two family level dtsis for the infinity and infinity3 and then adds a chip level dtsi each for a chip in those families. infinity3.dtsi includes infinity.dtsi as these SoCs share most of their memory map and we would have a lot of duplication otherwise. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28ARM: mstar: Add Armv7 base dtsiDaniel Palmer
Adds initial dtsi for the base MStar/Sigmastar Armv7 SoCs. These SoCs have very similar memory maps and this will avoid duplicating nodes across multiple dtsis. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28ARM: mstar: Add binding details for mstar,l3bridgeDaniel Palmer
This adds a YAML description of the l3bridge node needed by the platform code for the MStar/SigmaStar Armv7 SoCs. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28ARM: mstar: Add machine for MStar/Sigmastar Armv7 SoCsDaniel Palmer
Initial support for the MStar/Sigmastar Armv7 based IP camera and dashcam SoCs. These chips are interesting in that they contain a Cortex-A7, peripherals and system memory in a single tiny QFN package that can be hand soldered allowing almost anyone to embed Linux in their projects. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28dt-bindings: arm: Add mstar YAML schemaDaniel Palmer
Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28dt-bindings: vendor-prefixes: Add thingy.jp prefixDaniel Palmer
Add prefix for thingy.jp Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28dt-bindings: vendor-prefixes: Add 70mai vendor prefixDaniel Palmer
Add prefix for 70mai Co., Ltd Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28dt-bindings: vendor-prefixes: Add sstar vendor prefixDaniel Palmer
Add prefix for Xiamen Xingchen Technology Co., Ltd Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28dt-bindings: vendor-prefixes: Add mstar vendor prefixDaniel Palmer
Add prefix for MStar Semiconductor, Inc. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28arm64: dts: sparx5: Add i2c devices, i2c muxesLars Povlsen
This patch adds i2c devices and muxes to the Sparx5 reference boards. Link: https://lore.kernel.org/r/20200615133242.24911-11-lars.povlsen@microchip.com Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28arm64: dts: sparx5: Add Sparx5 SoC DPLL clockLars Povlsen
This adds a DPLL clock to the Sparx5 SoC. It is used to generate clock to misc peripherals, specifically the SDHCI/eMMC controller. Link: https://lore.kernel.org/r/20200615133242.24911-10-lars.povlsen@microchip.com Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28lockdep: Move list.h inclusion into lockdep.hHerbert Xu
Currently lockdep_types.h includes list.h without actually using any of its macros or functions. All it needs are the type definitions which were moved into types.h long ago. This potentially causes inclusion loops because both are included by many core header files. This patch moves the list.h inclusion into lockdep.h. Note that we could probably remove it completely but that could potentially result in compile failures should any end users not include list.h directly and also be unlucky enough to not get list.h via some other header file. Reported-by: Petr Mladek <pmladek@suse.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Tested-by: Petr Mladek <pmladek@suse.com> Link: https://lkml.kernel.org/r/20200716063649.GA23065@gondor.apana.org.au
2020-07-28ALSA: hda/hdmi: Fix keep_power assignment for non-component devicesTakashi Iwai
It's been reported that, when neither nouveau nor Nvidia graphics driver is used, the screen starts flickering. And, after comparing between the working case (stable 4.4.x) and the broken case, it turned out that the problem comes from the audio component binding. The Nvidia and AMD audio binding code clears the bus->keep_power flag whenever snd_hdac_acomp_init() succeeds. But this doesn't mean that the component is actually bound, but it merely indicates that it's ready for binding. So, when both nouveau and Nvidia are blacklisted or not ready, the driver keeps running without the audio component but also with bus->keep_power = false. This made the driver runtime PM kicked in and powering down when unused, which results in flickering in the graphics side, as it seems. For fixing the bug, this patch moves the bus->keep_power flag change into generic_acomp_notifier_set() that is the function called from the master_bind callback of component ops; i.e. it's guaranteed that the binding succeeded. BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=208609 Fixes: 5a858e79c911 ("ALSA: hda - Disable audio component for legacy Nvidia HDMI codecs") Cc: <stable@vger.kernel.org> Link: https://lore.kernel.org/r/20200728082033.23933-1-tiwai@suse.de Signed-off-by: Takashi Iwai <tiwai@suse.de>
2020-07-28KVM: arm64: Don't inherit exec permission across page-table levelsWill Deacon
If a stage-2 page-table contains an executable, read-only mapping at the pte level (e.g. due to dirty logging being enabled), a subsequent write fault to the same page which tries to install a larger block mapping (e.g. due to dirty logging having been disabled) will erroneously inherit the exec permission and consequently skip I-cache invalidation for the rest of the block. Ensure that exec permission is only inherited by write faults when the new mapping is of the same size as the existing one. A subsequent instruction abort will result in I-cache invalidation for the entire block mapping. Signed-off-by: Will Deacon <will@kernel.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Tested-by: Quentin Perret <qperret@google.com> Reviewed-by: Quentin Perret <qperret@google.com> Cc: Marc Zyngier <maz@kernel.org> Cc: <stable@vger.kernel.org> Link: https://lore.kernel.org/r/20200723101714.15873-1-will@kernel.org
2020-07-28KVM: arm64: Prevent vcpu_has_ptrauth from generating OOL functionsMarc Zyngier
So far, vcpu_has_ptrauth() is implemented in terms of system_supports_*_auth() calls, which are declared "inline". In some specific conditions (clang and SCS), the "inline" very much turns into an "out of line", which leads to a fireworks when this predicate is evaluated on a non-VHE system (right at the beginning of __hyp_handle_ptrauth). Instead, make sure vcpu_has_ptrauth gets expanded inline by directly using the cpus_have_final_cap() helpers, which are __always_inline, generate much better code, and are the only thing that make sense when running at EL2 on a nVHE system. Fixes: 29eb5a3c57f7 ("KVM: arm64: Handle PtrAuth traps early") Reported-by: Nathan Chancellor <natechancellor@gmail.com> Reported-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Tested-by: Nathan Chancellor <natechancellor@gmail.com> Reviewed-by: Nathan Chancellor <natechancellor@gmail.com> Link: https://lore.kernel.org/r/20200722162231.3689767-1-maz@kernel.org
2020-07-28ARM: dts: berlin: Align L2 cache-controller nodename with dtschemaKrzysztof Kozlowski
Fix dtschema validator warnings like: l2-cache-controller@ac0000: $nodename:0: 'l2-cache-controller@ac0000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$' Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Link: https://lore.kernel.org/r/20200626080642.4244-1-krzk@kernel.org' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28Merge tag 'aspeed-5.9-devicetree' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed into arm/dt ASPEED device tree updates for 5.9 There is one new machine; AMD's EthanolX reference platform with an AST2600 BMC. Misc updates for Rainier, Tacoma, Wedge and Mihawk machines. * tag 'aspeed-5.9-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed: (26 commits) ARM: dts: Aspeed: tacoma: Enable EHCI controller ARM: dts: aspeed: rainier: Enable EHCI controller ARM: dts: aspeed: rainier: Switch OCCs to P10 ARM: dts: aspeed: rainier: Add FSI I2C masters ARM: dts: aspeed: rainier: Add CFAM SPI controllers ARM: dts: aspeed: rainier: Add I2C buses for NVMe use ARM: dts: aspeed: Initial device tree for AMD EthanolX ARM: dts: rainier: Describe GPIO mux on I2C3 ARM: dts: aspeed: wedge40: Enable pwm_tacho device ARM: dts: aspeed: wedge40: Enable ADC device ARM: dts: aspeed: wedge40: Disable unused i2c controllers ARM: dts: aspeed: cmm: Fixup I2C tree ARM: dts: aspeed: tacoma: Add CFAM reset GPIO ARM: dts: aspeed: rainier: Add CFAM reset GPIO ARM: dts: aspeed: tacoma: Fix gpio-key definitions ARM: dts: rainier: Configure ball Y23 as GPIOP7 for MCLR_VPP ARM: dts: aspeed: rainier: Add second cfam on the hub ARM: dts: aspeed: rainier: Add line-name checkstop ARM: dts: aspeed: tacoma: Remove checkstop gpio-key ARM: dts: aspeed: tacoma: Enable XDMA engine ... Link: https://lore.kernel.org/r/CACPK8Xf_Np7LtcDFhywi6Uk1EgUpb0pVVa+Lr9YEwBRjbjOKCQ@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-27arm64: dts: qcom: Add Microsoft Lumia 950 (Talkman) device treeKonrad Dybcio
Add device tree support for the Microsoft Lumia 950 smartphone. It is based on msm8992 and supports booting Linux via a custom EDK2 port. Currently it supports: * Screen console via EFIFB * Booting via EFI_STUB * SDHCI * I2C * PSCI core bringup Please note that there is an implementation of EL2 startup on this board, but it requires the user to resign from PSCI and use spin-table instead. This revision sticks with PSCI. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-14-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: Add Xiaomi Libra (Mi 4C) device treeKonrad Dybcio
This commit adds support for the Xiaomi Libra (Mi 4C) smartphone. It's based on the Qualcomm msm8992 SoC. It currently supports: * Screen console from bootloader * SDHCI * Regulator configuration * Serial console * I2C Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-13-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: msm8992: Add RPMCC nodeKonrad Dybcio
This lets us use clocks provided by RPM. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-12-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: msm8992: Add PSCI support.Konrad Dybcio
This SoC's firmware does not fully support the PSCI spec, but it's good enough to bring the cores up. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-11-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: msm8992: Add PMU nodeKonrad Dybcio
Add the PMU so we can get proper perf event support on this SoC. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-10-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: msm8992: Add BLSP2_UART2 and I2C nodesKonrad Dybcio
Add support for I2C to enable support for peripherals such as touchscreens or sensors. Also add BLSP_UART2 interface. Please note that the naming scheme follows downstream and as abominable as it is, that's what we get. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-9-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: msm8992: Add SPMI PMIC arbiter deviceKonrad Dybcio
Add SPMI PMIC arbiter device to communicate with PMICs attached to SPMI bus. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-8-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: msm8992: Add a SCM nodeKonrad Dybcio
Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-7-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: msm8992: Add a proper CPU mapKonrad Dybcio
This commit adds cpu nodes for all 6 cores present on this SoC and the cpu-map. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-6-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: bullhead: Move UART pinctrl to SoCKonrad Dybcio
This pinout is common for every 8992-based device and should therefore reside in the SoC device tree. Also convert addresses into phandles. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-5-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-07-27arm64: dts: qcom: bullhead: Add qcom,msm-idKonrad Dybcio
Add the property required for the bootloader to select the correct device tree blob. It has been removed from the SoC device tree as it should be set on a per-device basis. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-4-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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