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2025-05-13dt-bindings: interrupt-controller: Convert faraday,ftintc010 to DT schemaRob Herring (Arm)
Convert the Faraday FTINTC010 interrupt controller binding to schema format. It's a straight-forward conversion of the typical interrupt controller. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20250505144654.1288979-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-05-13dt-bindings: interrupt-controller: Convert arm,versatile-fpga-irq to DT schemaRob Herring (Arm)
Convert the Arm Versatile FPGA interrupt controller binding to schema format. It's a straight-forward conversion of the typical interrupt controller. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20250505144558.1286889-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-05-13dt-bindings: interrupt-controller: Convert marvell,orion-bridge-intc to DT ↵Rob Herring (Arm)
schema Convert the Marvell Orion bridge interrupt controller binding to schema format. marvell,orion-intc is already covered by mrvl,intc.yaml schema, so it can be dropped. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20250505144743.1290672-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-05-13dt-bindings: interrupt-controller: Convert brcm,bcm2835-armctrl-ic to DT schemaRob Herring (Arm)
Convert the Broadcom BCM2835 ARMCTRL interrupt controller binding to schema format. It's a straight-forward conversion of the typical interrupt controller. Link: https://lore.kernel.org/r/20250505144618.1287539-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-05-13dt-bindings: interrupt-controller: Convert cnxt,cx92755-ic to DT schemaRob Herring (Arm)
Convert the Conexant Digicolor interrupt controller binding to schema format. It's a straight-forward conversion of the typical interrupt controller. Acked-by: Baruch Siach <baruch@tkos.co.il> Link: https://lore.kernel.org/r/20250505144644.1288617-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-05-13dt-bindings: Move altr,msi-controller to interrupt-controller directoryRob Herring (Arm)
While altr,msi-controller is used with PCI, it is not a PCI host bridge and is just an MSI provider. Move it with other MSI providers in the 'interrupt-controller' directory. Acked-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250507154253.1593870-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-05-13cxl: docs - add self-referencing cross-linksGregory Price
Add some crosslinks between pages in the CXL docs - mostly to the ACPI tables. Suggested-by: Bagas Sanjaya <bagasdotme@gmail.com> Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-18-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13cxl: docs/allocation/hugepagesGregory Price
Add docs on how CXL capacity interacts with CMA and HugeTLB allocation interfaces. Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-17-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13cxl: docs/allocation/reclaimGregory Price
Document a bit about how reclaim interacts with various CXL configurations. Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-16-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13cxl: docs/allocation/page-allocatorGregory Price
Document some interesting interactions that occur when exposing CXL memory capacity to page allocator. Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-15-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13cxl: docs/allocation/daxGregory Price
Small example of accessing CXL memory capacity via DAX device Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-14-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13cxl: docs/linux/memory-hotplugGregory Price
Add documentation on how the CXL driver surfaces memory through the DAX driver and memory-hotplug. Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-13-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13cxl: docs/linux/dax-driver documentationGregory Price
Add documentation on how the CXL driver interacts with the DAX driver. Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-12-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13cxl: docs/linux/cxl-driver - add example configurationsGregory Price
Add 4 example configurations: - single device - cross-host-bridge interleave - intra-host-bridge-interleave - multi-level interleave Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-11-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13cxl: docs/linux - add cxl-driver theory of operationGregory Price
Add docs for the CXL driver that explains the base devices, decoder types, region types, mailbox interfaces, and decoder programming. Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-10-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13cxl: docs/linux - early boot configurationGregory Price
Document __init time configurations that affect CXL driver probe process and memory region configuration. Signed-off-by: Gregory Price <gourry@gourry.net> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://patch.msgid.link/20250512162134.3596150-9-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13cxl: docs/linux - overviewGregory Price
Add type-3 device configuration overview that explains the probe process for a type-3 device from early-boot through memory-hotplug. Signed-off-by: Gregory Price <gourry@gourry.net> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://patch.msgid.link/20250512162134.3596150-8-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13cxl: docs/platform/example-configs documentationGregory Price
Add example ACPI Table configurations for different sample platforms. Signed-off-by: Gregory Price <gourry@gourry.net> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://patch.msgid.link/20250512162134.3596150-7-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13cxl: docs/platform/acpi reference documentationGregory Price
Add basic ACPI table information needed to understand the CXL driver probe process. Signed-off-by: Gregory Price <gourry@gourry.net> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://patch.msgid.link/20250512162134.3596150-6-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13cxl: docs/platform/bios-and-efi documentationGregory Price
Add some docs on CXL configurations done in bios/efi that affect linux configuration - information vendors may care to consider. Signed-off-by: Gregory Price <gourry@gourry.net> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://patch.msgid.link/20250512162134.3596150-5-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13cxl: docs/devices - add cxl device and protocol referenceGregory Price
Add a simple device primer sufficient to understand the theory of operation documentation. Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-4-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13cxl: docs - access-coordinates doc fixupsGregory Price
Place the hierarchy diagram in access-coordinates.rst in a code block. Fix a few grammar issues. Suggested-by: Randy Dunlap <rdunlap@infradead.org> Suggested-by: Bagas Sanjaya <bagasdotme@gmail.com> Signed-off-by: Gregory Price <gourry@gourry.net> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://patch.msgid.link/20250512162134.3596150-3-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13cxl: update documentation structure in prep for new docsGregory Price
Restructure the cxl folder to make adding docs per-page cleaner. Signed-off-by: Gregory Price <gourry@gourry.net> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://patch.msgid.link/20250512162134.3596150-2-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13Documentation: scheduler: Changed lowercase acronyms to uppercaseJake Rice
Everywhere else in this doc, the dispatch queue acronym (DSQ) is uppercase. There were a couple places where the acronym was written in lowercase. I changed them to uppercase to make it homogeneous. Signed-off-by: Jake Rice <jake@jakerice.dev> Signed-off-by: Tejun Heo <tj@kernel.org>
2025-05-13dt-bindings: display: msm: correct example in SM8350 MDSS schemaDmitry Baryshkov
Fix the interconnects in the example to follow the schema changes. Fixes: 60b8d3a2365a ("dt-bindings: display: msm: sm8350-mdss: Describe the CPU-CFG icc path") Reported-by: Rob Herring <robh@kernel.org> Closes: http://lore.kernel.org/r/CAL_JsqKr8Xd8uxFzE0YJTyD+V6N++VV8SX-GB5Xt0_BKkeoGUQ@mail.gmail.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/651775/ Link: https://lore.kernel.org/r/20250505-sm8350-fix-example-v1-1-36d5d9ccba66@oss.qualcomm.com
2025-05-13docs: bpf: Fix bullet point formatting warningKhaled Elnaggar
Fix indentation for a bullet list item in bpf_iterators.rst. According to reStructuredText rules, bullet list item bodies must be consistently indented relative to the bullet. The indentation of the first line after the bullet determines the alignment for the rest of the item body. Reported by smatch: /linux/Documentation/bpf/bpf_iterators.rst:55: WARNING: Bullet list ends without a blank line; unexpected unindent. [docutils] Fixes: 7220eabff8cb ("bpf, docs: document open-coded BPF iterators") Signed-off-by: Khaled Elnaggar <khaledelnaggarlinux@gmail.com> Signed-off-by: Andrii Nakryiko <andrii@kernel.org> Link: https://lore.kernel.org/bpf/20250513015901.475207-1-khaledelnaggarlinux@gmail.com
2025-05-13f2fs: fix 32-bits hexademical number in fault injection docChao Yu
FAULT_KMALLOC 0x000000001 There is one redundant '0' in 32-bits hexademical number of fault type, remove it. Signed-off-by: Chao Yu <chao@kernel.org> Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
2025-05-13dt-bindings: remoteproc: qcom,sm8150-pas: Add missing SC8180X compatibleKrzysztof Kozlowski
Commit 4b4ab93ddc5f ("dt-bindings: remoteproc: Consolidate SC8180X and SM8150 PAS files") moved SC8180X bindings from separate file into this one, but it forgot to add actual compatibles in top-level properties section making the entire binding un-selectable (no-op) for SC8180X PAS. Fixes: 4b4ab93ddc5f ("dt-bindings: remoteproc: Consolidate SC8180X and SM8150 PAS files") Cc: stable@vger.kernel.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250428075243.44256-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-13dt-bindings: remoteproc: qcom,sm8350-pas: Add SC8280XPKonrad Dybcio
From the software POV, it matches the SM8350's implementation. Describe it as such, with a fallback. Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> # Lenovo X13s Link: https://lore.kernel.org/r/20250503-topic-8280_slpi-v1-1-9400a35574f7@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-13dt-bindings: cache: Convert marvell,tauros2-cache to DT schemaRob Herring (Arm)
Convert the Marvell Tauros2 Cache binding to DT schema. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-05-13dt-bindings: cache: Convert marvell,{feroceon,kirkwood}-cache to DT schemaRob Herring (Arm)
Convert the Marvell Feroceon/Kirkwood Cache binding to DT schema format. Use "marvell,kirkwood-cache" for the filename instead as that's only compatible used in a .dts upstream. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-05-13Documentation/gpu: Disambiguate SPI termBagas Sanjaya
Documentation/userspace-api/media/glossary.rst:170: WARNING: duplicate term description of SPI, other instance in gpu/amdgpu/amdgpu-glossary That's because SPI of amdgpu (Shader Processor Input) shares the same global glossary term as SPI of media subsystem (which is Serial Peripheral Interface Bus). Disambiguate the former from the latter to fix the warning. Note that adding context qualifiers in the term is strictly necessary in order to make Sphinx happy. Fixes: dd3d035a7838 ("Documentation/gpu: Add new entries to amdgpu glossary") Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Closes: https://lore.kernel.org/linux-next/20250509185845.60bf5e7b@canb.auug.org.au/ Signed-off-by: Bagas Sanjaya <bagasdotme@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-05-13Merge tag 'ib-mfd-gpio-nvmem-v6.16' of ↵Bartosz Golaszewski
git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into gpio/for-next Immutable branch between MFD, GPIO and NVMEM due for the v6.16 merge window
2025-05-13gpu: nova-core: define registers layout using helper macroAlexandre Courbot
Add the register!() macro, which defines a given register's layout and provide bit-field accessors with a way to convert them to a given type. This macro will allow us to make clear definitions of the registers and manipulate their fields safely. The long-term goal is to eventually move it to the kernel crate so it can be used by other drivers as well, but it was agreed to first land it into nova-core and make it mature there. To illustrate its usage, use it to define the layout for the Boot0 (renamed to NV_PMC_BOOT_0 to match OpenRM's naming scheme) and take advantage of its accessors. Suggested-by: Danilo Krummrich <dakr@kernel.org> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Link: https://lore.kernel.org/r/20250507-nova-frts-v3-5-fcb02749754d@nvidia.com [ Fix typo in commit message. - Danilo ] Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2025-05-13dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs8300Lijuan Gao
Correct the gpio-ranges in the QCS8300 TLMM pin controller example to include the UFS_RESET pin, which is expected to be wired to the reset pin of the primary UFS memory. This allows the UFS driver to toggle it. Fixes: 5778535972e2 ("dt-bindings: pinctrl: describe qcs8300-tlmm") Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com> Link: https://lore.kernel.org/20250506-correct_gpio_ranges-v3-2-49a7d292befa@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-05-13dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs615Lijuan Gao
Correct the gpio-ranges in the QCS615 TLMM pin controller example to include the UFS_RESET pin, which is expected to be wired to the reset pin of the primary UFS memory. This allows the UFS driver to toggle it. Fixes: 55c487ea6084 ("dt-bindings: pinctrl: document the QCS615 Top Level Mode Multiplexer") Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com> Link: https://lore.kernel.org/20250506-correct_gpio_ranges-v3-1-49a7d292befa@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-05-13cpufreq: intel_pstate: Document hybrid processor supportRafael J. Wysocki
Describe the support for hybrid processors in intel_pstate, including the CAS and EAS support, in the admin-guide documentation. Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/1935040.CQOukoFCf9@rjwysocki.net
2025-05-13PM: EM: Documentation: Fix typos in example driver codeAtul Kumar Pant
Fix the API name to free the allocated table in the example driver code that modifies the EM. Also fix the passing of correct table when updating the cost. Signed-off-by: Atul Kumar Pant <atulpant.linux@gmail.com> Link: https://patch.msgid.link/20250511071141.13237-1-atulpant.linux@gmail.com Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2025-05-13dt-bindings: mfd: stm32-lptimer: Add support for stm32mp25Fabrice Gasnier
Add a new stm32mp25 compatible to stm32-lptimer dt-bindings, to support STM32MP25 SoC. Some features has been updated or added to the low-power timer: - new capture compare channels - up to two PWM channels - PWM input capture - peripheral interconnect in stm32mp25 has been updated (new triggers). - registers/bits has been added or revisited (IER access). So introduce a new compatible to handle this diversity. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org> Link: https://lore.kernel.org/r/20250429125133.1574167-2-fabrice.gasnier@foss.st.com Signed-off-by: Lee Jones <lee@kernel.org>
2025-05-13dt-bindings: arm: sunxi: Add Liontron H-A133L board nameAndre Przywara
The Liontron H-A133L is an industrial development board using the Allwinner A133 SoC. Add its compatible name to the list of valid board names. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250505164729.18175-3-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-05-13dt-bindings: vendor-prefixes: Add Liontron nameAndre Przywara
Liontron is a company based in Shenzen, China, making industrial development boards and embedded computers, mostly using Rockchip and Allwinner SoCs. Add their name to the list of vendors. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250505164729.18175-2-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-05-13net: enable driver support for netmem TXMina Almasry
Drivers need to make sure not to pass netmem dma-addrs to the dma-mapping API in order to support netmem TX. Add helpers and netmem_dma_*() helpers that enables special handling of netmem dma-addrs that drivers can use. Document in netmem.rst what drivers need to do to support netmem TX. Signed-off-by: Mina Almasry <almasrymina@google.com> Acked-by: Stanislav Fomichev <sdf@fomichev.me> Link: https://patch.msgid.link/20250508004830.4100853-7-almasrymina@google.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2025-05-13net: add devmem TCP TX documentationMina Almasry
Add documentation outlining the usage and details of the devmem TCP TX API. Signed-off-by: Mina Almasry <almasrymina@google.com> Acked-by: Stanislav Fomichev <sdf@fomichev.me> Link: https://patch.msgid.link/20250508004830.4100853-6-almasrymina@google.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2025-05-13net: devmem: TCP tx netlink apiStanislav Fomichev
Add bind-tx netlink call to attach dmabuf for TX; queue is not required, only ifindex and dmabuf fd for attachment. Signed-off-by: Stanislav Fomichev <sdf@fomichev.me> Signed-off-by: Mina Almasry <almasrymina@google.com> Link: https://patch.msgid.link/20250508004830.4100853-4-almasrymina@google.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2025-05-13Merge commit 'its-for-linus-20250509-merge' into x86/core, to resolve conflictsIngo Molnar
Conflicts: Documentation/admin-guide/hw-vuln/index.rst arch/x86/include/asm/cpufeatures.h arch/x86/kernel/alternative.c arch/x86/kernel/cpu/bugs.c arch/x86/kernel/cpu/common.c drivers/base/cpu.c include/linux/cpu.h Signed-off-by: Ingo Molnar <mingo@kernel.org>
2025-05-13Merge branch 'x86/platform' into x86/core, to merge dependent commitsIngo Molnar
Prepare to resolve conflicts with an upstream series of fixes that conflict with pending x86 changes: 6f5bf947bab0 Merge tag 'its-for-linus-20250509' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Signed-off-by: Ingo Molnar <mingo@kernel.org>
2025-05-13Merge branch 'x86/microcode' into x86/core, to merge dependent commitsIngo Molnar
Prepare to resolve conflicts with an upstream series of fixes that conflict with pending x86 changes: 6f5bf947bab0 Merge tag 'its-for-linus-20250509' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Signed-off-by: Ingo Molnar <mingo@kernel.org>
2025-05-13dt-bindings: soc: samsung: exynos-pmu: gs101: add google,pmu-intr-gen phandlePeter Griffin
gs101 requires access to the pmu interrupt generation register region which is exposed as a syscon. Update the exynos-pmu bindings documentation to reflect this. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20250506-contrib-pg-cpu-hotplug-suspend2ram-fixes-v1-v4-2-9f64a2657316@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-05-13dt-bindings: soc: google: Add gs101-pmu-intr-gen binding documentationPeter Griffin
Add bindings documentation for the Power Management Unit (PMU) interrupt generator. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20250506-contrib-pg-cpu-hotplug-suspend2ram-fixes-v1-v4-1-9f64a2657316@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-05-13Documentation: fix typo in root= kernel parameter descriptionPetr Vaněk
Fixes a typo in the root= parameter description, changing "this a a" to "this is a". Fixes: c0c1a7dcb6f5 ("init: move the nfs/cifs/ram special cases out of name_to_dev_t") Signed-off-by: Petr Vaněk <arkamar@atlas.cz> Link: https://lore.kernel.org/20250512110827.32530-1-arkamar@atlas.cz Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Christian Brauner <brauner@kernel.org>
generated by cgit (git 2.34.1) at 2025-07-24 16:53:30 +0000