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* pm-cpufreq: (57 commits)
cpufreq: MAINTAINERS: Add co-maintainer
cpufreq: pxa2xx: initialize variables
ARM: S5pv210: compiling issue, ARM_S5PV210_CPUFREQ needs CONFIG_CPU_FREQ_TABLE=y
cpufreq: cpu0: Put cpu parent node after using it
cpufreq: ARM big LITTLE: Adapt to latest cpufreq updates
cpufreq: ARM big LITTLE: put DT nodes after using them
cpufreq: Don't call __cpufreq_governor() for drivers without target()
cpufreq: exynos5440: Protect OPP search calls with RCU lock
cpufreq: dbx500: Round to closest available freq
cpufreq: Call __cpufreq_governor() with correct policy->cpus mask
cpufreq / intel_pstate: Optimize intel_pstate_set_policy
cpufreq: OMAP: instantiate omap-cpufreq as a platform_driver
arm: exynos: Enable OPP library support for exynos5440
cpufreq: exynos: Remove error return even if no soc is found
cpufreq: exynos: Add cpufreq driver for exynos5440
cpufreq: AMD "frequency sensitivity feedback" powersave bias for ondemand governor
cpufreq: ondemand: allow custom powersave_bias_target handler to be registered
cpufreq: convert cpufreq_driver to using RCU
cpufreq: powerpc/platforms/cell: move cpufreq driver to drivers/cpufreq
cpufreq: sparc: move cpufreq driver to drivers/cpufreq
...
Conflicts:
MAINTAINERS (with commit a8e39c3 from pm-cpuidle)
drivers/cpufreq/cpufreq_governor.h (with commit beb0ff3)
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* pm-cpuidle: (51 commits)
cpuidle: add maintainer entry
ARM: s3c64xx: cpuidle: use init/exit common routine
SH: cpuidle: use init/exit common routine
cpuidle: fix comment format
ARM: imx: cpuidle: use init/exit common routine
ARM: davinci: cpuidle: use init/exit common routine
ARM: kirkwood: cpuidle: use init/exit common routine
ARM: calxeda: cpuidle: use init/exit common routine
ARM: tegra: cpuidle: use init/exit common routine for tegra3
ARM: tegra: cpuidle: use init/exit common routine for tegra2
ARM: OMAP4: cpuidle: use init/exit common routine
ARM: shmobile: cpuidle: use init/exit common routine
ARM: tegra: cpuidle: use init/exit common routine
ARM: OMAP3: cpuidle: use init/exit common routine
ARM: at91: cpuidle: use init/exit common routine
ARM: ux500: cpuidle: use init/exit common routine
cpuidle: make a single register function for all
ARM: ux500: cpuidle: replace for_each_online_cpu by for_each_possible_cpu
cpuidle: remove en_core_tk_irqen flag
ARM: OMAP3: remove cpuidle_wrap_enter
...
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The code intializes the cpuidle driver at different places.
The cpuidle driver for :
* imx5 : is in the pm-imx5.c, the init function is in cpuidle.c
* imx6 : is in cpuidle-imx6q.c, the init function is in cpuidle.c
and cpuidle-imx6q.c
Instead of having the cpuidle code spread across different files,
let's create a driver for each SoC and use the common register function.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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The en_core_tk_irqen flag is set in all the cpuidle driver which
means it is not necessary to specify this flag.
Remove the flag and the code related to it.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Kevin Hilman <khilman@linaro.org> # for mach-omap2/*
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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Remove the majority of cache flushing calls from the individual platform
files. This is now handled by the core code.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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into next/soc2
From Shawn Guo:
The imx soc changes for 3.10:
* Enable anatop, well bisa and RBC for suspend to optimize the power
consumption a little bit
* Clock changes for TVE, LDB, PATA, SRTC support
* Add System Reset Controller (SRC) support for imx5 and imx6
* Add initial imx6dl support based on imx6q code
* Kconfig for cpufreq-cpu0, defconfig updates and few other changes
* tag 'imx-soc-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6: (275 commits)
ARM i.MX53: set CLK_SET_RATE_PARENT flag on the tve_ext_sel clock
ARM i.MX53: tve_di clock is not part of the CCM, but of TVE
ARM i.MX53: make tve_ext_sel propagate rate change to PLL
ARM i.MX53: Remove unused tve_gate clkdev entry
ARM i.MX5: Remove tve_sel clock from i.MX53 clock tree
ARM: i.MX5: Add PATA and SRTC clocks
ARM: imx: do not bring up unavailable cores
ARM: imx: add initial imx6dl support
ARM: imx1: mm: add call to mxc_device_init
ARM: imx_v4_v5_defconfig: Add CONFIG_GPIO_SYSFS
ARM: imx_v6_v7_defconfig: Select CONFIG_PERF_EVENTS
ARM: i.MX53 Add the cko1, cko2 clock outputs.
staging: drm/imx: Use SRC to reset IPU
ARM i.MX6q: Add GPU, VPU, IPU, and OpenVG resets to System Reset Controller (SRC)
ARM: imx: do not use regmap_read for ANADIG_DIGPROG
ARM i.MX6q: set the LDB serial clock parent to the video PLL
ARM i.MX6q: Add audio/video PLL post dividers for i.MX6q rev 1.1
ARM i.MX6q: fix ldb di divider and selector clocks
ARM i.MX53: fix ldb di divider and selector clocks
ARM i.MX: Add imx_clk_divider_flags and imx_clk_mux_flags
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Trivial change/change conflict in arch/arm/mach-imx/mach-imx6q.c resolved.
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Use imx_clk_mux_flags to set the appropriate flags for the TVE
selector clock. This is needed so tve_clk rate changes can propagate
up to pll4_sw.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Remove the tve_di clock from the CCM clock tree. It will be provided
by the Television Encoder driver, as this clock is an output signal
of the TVE module.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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This is needed so the Television Encoder driver can set the rate
on tve_clk and have it propagated up to pll4_sw.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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On i.MX53, there is only tve_ext_sel.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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This adds the clock gates and the binding documentation
for PATA and SRTC.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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The i.MX6 Quad can be fused as i.MX6 Dual chip, and similarly i.MX6
DualLite can be fused as i.MX6 Solo. The actual number of available
cores can be found out from SCU.
Since we do not reflect the fusing thing in device tree, the function
arm_dt_init_cpu_maps() will always call set_cpu_possible(true) for 4
cores on i.MX6 Quad/Dual and 2 cores for i.MX6 DualLite/Solo. This
causes failures when kernel tries to bring those unavailable cores
online. For example, the following failure message will be seen when
booting an i.MX6 Solo chip.
CPU1: failed to come online
Though kernel will still boot fine, the message is somehow annoying.
Let's get rid of it by calling set_cpu_possible(false) on those
unavailable cores.
While at it, the set_cpu_possible(true) for available cores is removed,
since it's already been done in arm_dt_init_cpu_maps().
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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The i.MX6 DualLite/Solo is another i.MX6 family SoC, which is highly
compatible with i.MX6 Quad/Dual. And that's why we choose to support
it using imx6q code with cpu_is_imx6dl() check when necessary.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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mxc_device_init() is mandatory for mxc_aips and mxc_ahb bus registration, needed
as parents, at least, for gpio and dma.
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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These two clocks connect to external pins and can be muxed to
various internal clocks.
They are typically used either for debugging or to provide
clocks to external chips (eg audio codecs).
Currently only the selectable clocks that already exist in the clock tree
have been added.
Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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(SRC)
The SRC has auto-deasserting reset bits that control reset lines to
the GPU, VPU, IPU, and OpenVG IP modules. This patch adds a reset
controller that can be controlled by those devices using the
reset controller API.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Function imx_anatop_get_digprog() that reads register ANADIG_DIGPROG is
called to identify silicon version. Users might query silicon version
earlier than regmap subsystem is ready. For example, imx6q clock driver
query revision in mx6q_clocks_init(), where regmap is not initialized
yet.
Change imx_anatop_get_digprog() to map anatop block and read
ANADIG_DIGPROG in the native way, so that the function can work at very
early stage.
While at it, let's move imx_print_silicon_rev() back to
imx6q_timer_init() to have the message show up a little earlier.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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On i.MX6q revision 1.1 and later, set the video PLL as parent for
the LDB clock branch. On revision 1.0, the video PLL is useless
due to missing dividers, so keep the default parent (mmdc_ch1_axi).
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Query silicon revision to determine clock tree and add post
dividers for newer revisions.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Use imx_clk_mux_flags and imx_clk_divider_flags to set the appropriate
flags for the LDB display interface divider and selector clocks.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Use imx_clk_mux_flags and imx_clk_divider_flags to set the appropriate
flags for the LDB display interface divider and selector clocks.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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The default is for dividers to set CLK_SET_PARENT_RATE and for muxes to
not set that flag. In the LDB clock tree, we need the opposite, so add
functions to create divider and mux clocks with configurable flags.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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So it can be used in clk-imx6q.c for revision dependent clock tree setup.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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There are some config options not selected by imx27 and imx5 that are
necessary to use the cpufreq-cpu0 driver.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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This patch adds the missing GPU2D and GPU3D mux and gate clocks,
and the graphics arbiter gate clock.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Fix the following sparse warnings:
arch/arm/mach-imx/anatop.c:56:6: warning: symbol 'imx_anatop_pre_suspend' was not declared. Should it be static?
arch/arm/mach-imx/anatop.c:62:6: warning: symbol 'imx_anatop_post_resume' was not declared. Should it be static?
arch/arm/mach-imx/anatop.c:68:6: warning: symbol 'imx_anatop_usb_chrg_detect_disable' was not declared. Should it be static?
arch/arm/mach-imx/anatop.c:78:5: warning: symbol 'imx_anatop_get_digprog' was not declared. Should it be static?
arch/arm/mach-imx/anatop.c:86:13: warning: symbol 'imx_anatop_init' was not declared. Should it be static?
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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RBC is to control whether some ANATOP sub modules
can enter lpm mode when SOC is into STOP mode, if
RBC is enabled and PMIC_VSTBY_REQ is set, ANATOP
will have below behaviors:
1. Digital LDOs(CORE, SOC and PU) are bypassed;
2. Analog LDOs(1P1, 2P5, 3P0) are disabled;
As the 2P5 is necessary for DRAM IO pre-drive in
STOP mode, so we need to enable weak 2P5 in STOP
mode when 2P5 LDO is disabled.
For RBC settings, there are some rules as below
due to hardware design:
1. All interrupts must be masked during operating
RBC registers;
2. At least 2 CKIL(32K) cycles is needed after the
RBC setting is changed.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Enable periphery charge pump for well biasing
at suspend to reduce periphery leakage.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Anatop module have sereval configurations for user
to reduce the power consumption in suspend, provide
suspend/resume interface for further use and enable
fet_odrive to reduce CORE LDO leakage during suspend.
As we have a common anatop file, remove all the operations
of anatop module in other files, use anatop interfaces to
do that.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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The imx cleanup for 3.10:
* Clean up a couple of unneeded function declarations
* Remove imx specific cpufreq driver as generic cpufreq-cpu0 works well
as the replacement
* Remove platform ahci support
* Clean up unused ARCH/MACH Kconfig symbols
* Remove a couple of unused files
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Bringin in clk subsystem dependencies needed by sunxi.
* depends/clk-for-3.10: (26 commits)
clk: sunxi: drop an unnecesary kmalloc
clk: sunxi: drop CLK_IGNORE_UNUSED
clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates
clk: divider: Introduce CLK_DIVIDER_ALLOW_ZERO flag
clk: mvebu: Use common of_clk_init() function
clk: fix clk_mux::flags kerneldoc
clk: allow reentrant calls into the clk framework
clk: abstract locking out into helper functions
clk: zynq: Add missing zynq clk header
clk: sunxi: rename compatible strings
arm: sunxi: Add useful information about sunxi clocks
clk: arm: sunxi: Add a new clock driver for sunxi SOCs
clk: ux500: Fix prcmu clocks registration
ARM: imx: adapt clk_busy_mux to new clk_mux struct
clk: Add composite clock type
clk: add table lookup to mux
clk: Fix incorrect return type in clk.c
clk: prima2: fix return value check in sirfsoc_of_clk_init()
clk:SPEAr1340: Correct parent clock configuration
documentation: clk: fix couple of misspelling
...
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git://git.linaro.org/people/shawnguo/linux-2.6 into next/cleanup
From Shawn Guo:
The imx cleanup for 3.10:
* Clean up a couple of unneeded function declarations
* Remove imx specific cpufreq driver as generic cpufreq-cpu0 works well
as the replacement
* Remove platform ahci support
* Clean up unused ARCH/MACH Kconfig symbols
* Remove a couple of unused files
* tag 'imx-cleanup-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6:
ARM: i.MX: remove unused ARCH_* configs
ARM i.MX53: remove platform ahci support
ARM: imx: remove mx6q.h
ARM: imx: remove Makefile.boot
ARM: imx: clk-imx27: Do not register peripheral clock for SSI
ARM: imx: avic: Move avic_saved_mask_reg under CONFIG_PM
ARM: imx: Remove cpufreq driver
ARM: imx: remove pl310_get_save_ptr() declaration
ARM: imx: remove duplicated function declaration
Signed-off-by: Olof Johansson <olof@lixom.net>
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The TWD and SCU configs are selected by default as long as
MSM_SCORPIONMP is false and/or MCT is false. Implementing the
logic this way certainly saves lines in the Kconfig but it
precludes those machines which select MSM_SCORPIONMP or MCT from
participating in the single zImage effort because when those
machines are combined with other SMP capable machines the TWD and
SCU are no longer selected by default.
Push the select out to the machine entries so that we can compile
these machines together and still select the appropriate configs.
Cc: Barry Song <baohua.song@csr.com>
Acked-by: David Brown <davidb@codeaurora.org>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Pawel Moll <pawel.moll@arm.com>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Acked-by: Simon Horman <horms@verge.net.au>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Tony Lindgren <tony@atomide.com>
Acked-by: Viresh Kumar <viresh.linux@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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The SRC in i.MX51 and i.MX53 is similar to the one in i.MX6q minus
the IPU2 reset line and multi core CPU reset/enable bits.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Add cpufreq-cpu0 platform device for imx5 DT init and register the clock
for imx5.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Adds cpufreq-cpu0 platform device for imx27 DT init and adds a clock
registration for cpufreq-cpu0 device.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Similarly as it was done for mx6q, use a DT lookup in order to make maintainance
task for the clock devices easier.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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This is a dependency for the mxs/cleanup branch.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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This removes the unused Kconfig options ARCH_MX5, ARCH_MX51,
ARCH_MX53 and MACH_MX21.
Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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The i.MX53 ahci platform support is unused in mainline. To demotivate
people using it just remove it from the tree.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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According to the recent i.MX6 Quad technical reference manual, mode 0x4 (100b)
of the CCM_CS2DCR register (address 0x020C402C) bits [11-9] and [14-12] select
the PLL3 clock, and not the PLL3 PFD1 540M clock. In our code, the PLL3 root
clock is named 'pll3_usb_otg', select this instead of the 540M clock.
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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While booting from device tree, imx6q used to provide twd clock lookup
by calling clk_register_clkdev() in clock driver. However, the commit
bd60345 (ARM: use device tree to get smp_twd clock) forces DT boot to
look up the clock from device tree. It causes the failure below when
twd driver tries to get the clock, and hence kernel has to calibrate the
local timer frequency.
smp_twd: clock not found -2
...
Calibrating local timer... 396.13MHz.
Fix the regression by providing twd clock lookup from device tree, and
remove the unused twd clk_register_clkdev() call from clock driver.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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The admux clock seems to be the audmux clock as tests show. audmux does
not work without this clock enabled. Currently imx35 does not register a
clock device for audmux. This patch adds this registration. imx-audmux
driver already handles a clock device, so no changes are necessary
there.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Cc: stable@vger.kernel.org
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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This patch enables iomuxc_gate clock. It is necessary to be able to
reconfigure iomux pads. Without this clock enabled, the
clk_disable_unused function will disable this clock and the iomux pads
are not configurable anymore. This happens at every boot. After a reboot
(watchdog system reset) the clock is not enabled again, so all iomux pad
reconfigurations in boot code are without effect.
The iomux pads should be always configurable, so this patch always
enables it.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Cc: stable@vger.kernel.org
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Twelve Kconfig symbols, all related to WM8350, WM8351, and WM8352, are
unused. Commit 19d57ed5a308472a02e773f33c03ad4cb2ec6a9 ("mfd: Remove
custom wm8350 cache implementation") removed all their (actual) users.
Remove these symbols too.
Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
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Both zynq and shmobile have conflicts against the gic cleanup
series, resolved here.
Conflicts:
arch/arm/mach-shmobile/smp-emev2.c
arch/arm/mach-shmobile/smp-r8a7779.c
arch/arm/mach-shmobile/smp-sh73a0.c
arch/arm/mach-zynq/platsmp.c
drivers/gpio/gpio-pl061.c
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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From Michal Simek <michal.simek@xilinx.com>:
This branch is based on zynq/clksrc/cleanup parts because
there are some dependencies on moving timer to generic location.
I could based it on standard Linux tagged version but you will get
several conflicts you will have to resolve.
If you are OK to resolving these problems, please let me know
I will create another branch with core-smp changes which are not based
on zynq/clksrc/cleanup branch.
* 'zynq/core-smp' of git://git.xilinx.com/linux-xlnx:
arm: zynq: Add hotplug support
arm: zynq: Add smp support
arm: zynq: Add smp_twd timer
arm: zynq: Get rid of xilinx function prefix
arm: zynq: Add support for system reset
arm: zynq: Move slcr initialization to separate file
arm: zynq: Load scu baseaddress at run time
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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* pm-cpuidle-next:
cpuidle: imx6: remove timer broadcast initialization
cpuidle: OMAP4: remove timer broadcast initialization
cpuidle: ux500: remove timer broadcast initialization
cpuidle: initialize the broadcast timer framework
timer: move enum definition out of ifdef section
cpuidle: kirkwood: fix coccicheck warnings
cpuidle / kirkwood: remove redundant Kconfig option
cpuidle / ux500 : use CPUIDLE_FLAG_TIMER_STOP flag
cpuidle / imx6 : use CPUIDLE_FLAG_TIMER_STOP flag
cpuidle / omap4 : use CPUIDLE_FLAG_TIMER_STOP flag
cpuidle : handle clockevent notify from the cpuidle framework
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