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IPQ5424 has tsens v2.3.3 peripheral. This patch adds the tsens
node with nvmem cells for calibration data.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Link: https://lore.kernel.org/r/20250210120436.821684-6-quic_mmanikan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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This patch adds thermal zone nodes for sensors present in
IPQ5332.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Link: https://lore.kernel.org/r/20250210120436.821684-5-quic_mmanikan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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IPQ5332 has tsens v2.3.3 peripheral. This patch adds the tsens
node with nvmem cells for calibration data.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Link: https://lore.kernel.org/r/20250210120436.821684-4-quic_mmanikan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add LDOA2 regulator from MP5496 to support SDCC voltage scaling.
Suggested-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250210070122.208842-6-amadeus@jmu.edu.cn
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Change the labels of mp5496 regulator from ipq6018 to mp5496.
Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://lore.kernel.org/r/20250210070122.208842-5-amadeus@jmu.edu.cn
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Some IPQ60xx SoCs don't come with the mp5496 pmic chip. The mp5496
pmic was never part of the IPQ60xx SoC, it's optional, so we moved
it out of the soc dtsi.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20250210070122.208842-4-amadeus@jmu.edu.cn
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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The early version of IPQ6000 (SoC id: IPQ6018, SBL version:
BOOT.XF.0.3-00077-IPQ60xxLZB-2) and IPQ6005 SoCs can reach
a max frequency of 1.5GHz, so add this CPU frequency.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20250210070122.208842-3-amadeus@jmu.edu.cn
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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The final version of IPQ6000 (SoC id: IPQ6000, SBL version:
BOOT.XF.0.3-00086-IPQ60xxLZB-1) has a max design frequency
of 1.2GHz, so add this CPU frequency.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250210070122.208842-2-amadeus@jmu.edu.cn
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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The sa8775p-ride platform uses the QCA6698 Bluetooth chip. While the
QCA6698 shares the same IP core as the WCN6855, it has different RF
components and RAM sizes, requiring new firmware files. Use the
firmware-name property to specify the NVM and rampatch firmware to load.
Signed-off-by: Cheng Jiang <quic_chejiang@quicinc.com>
Reviewed-by: Zijun Hu <quic_zijuhu@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250110063914.28001-2-quic_chejiang@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Make this USB controller consistent with the others on this platform.
Fixes: 4af46b7bd66f ("arm64: dts: qcom: x1e80100: Add USB nodes")
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250109205232.92336-1-kettenis@openbsd.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Enable SLPI, sensors DSP, on the Qualcomm Robotics RB5 platform. The
firmware for the DSP is a part of linux-firmware repository.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250222-rb3-rb5-slpi-v1-2-6739be1684b6@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Enable SLPI, sensors DSP, on the Qualcomm Robotics RB3 platform. The
firmware for the DSP is a part of linux-firmware repository.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250222-rb3-rb5-slpi-v1-1-6739be1684b6@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Enabling spi6 caused boot loop on my device(Huawei Matebook E Go),
&spi6 {
pinctrl-0 = <&spi6_default>;
pinctrl-names = "default";
status = "okay";
};
After looking into this, I found the clocks for spi0 to spi7 are
wrong, we can derive the correct clocks from the regular pattern
between spi8 to spi15, spi16 to spi23. Or we can verify it according
to the hex file of BSRC_QSPI.bin(From windows driver qcspi8280.cab)
000035d0: 0700 4445 5649 4345 0001 000a 005c 5f53 ..DEVICE.....\_S
000035e0: 422e 5350 4937 0003 0076 0001 000a 0043 B.SPI7...v.....C
000035f0: 4f4d 504f 4e45 4e54 0000 0008 0000 0000 OMPONENT........
00003600: 0000 0000 0003 0017 0001 0007 0046 5354 .............FST
00003610: 4154 4500 0000 0800 0000 0000 0000 0000 ATE.............
00003620: 0300 3d00 0100 1400 4449 5343 4f56 4552 ..=.....DISCOVER
00003630: 4142 4c45 5f50 5354 4154 4500 0100 0600 ABLE_PSTATE.....
00003640: 434c 4f43 4b00 0100 1700 6763 635f 7175 CLOCK.....gcc_qu
00003650: 7076 335f 7772 6170 305f 7336 5f63 6c6b pv3_wrap0_s6_clk
Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20250223110152.47192-1-mitltlatltl@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Enable PMIC and PMIC peripherals for qcs8300-ride board. The qcs8
300-ride uses 2 pmics(pmm8620au:0,pmm8650au:1) on the board, which
are variants of pmm8654au used on sa8775p/qcs9100 -ride(4x pmics).
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Tingguo Cheng <quic_tingguoc@quicinc.com>
Link: https://lore.kernel.org/r/20250108-adds-spmi-pmic-peripherals-for-qcs8300-v3-2-ee94642279ff@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add the SPMI bus arbiter(Version:5.2.0) node for QCS8300 SoC
which connected with PMICs on QCS8300 boards.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Tingguo Cheng <quic_tingguoc@quicinc.com>
Link: https://lore.kernel.org/r/20250108-adds-spmi-pmic-peripherals-for-qcs8300-v3-1-ee94642279ff@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add node to support uart3.
Signed-off-by: Wojciech Slenska <wojciech.slenska@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241112124651.215537-1-wojciech.slenska@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add the PMU node for WCN6750 present on the qcs6490-rb3gen2
board and assign its power outputs to the Bluetooth module.
In WCN6750 module sw_ctrl and wifi-enable pins are handled
in the wifi controller firmware. Therefore, it is not required
to have those pins' entries in the PMU node.
Signed-off-by: Janaki Ramaiah Thota <quic_janathot@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250221171014.120946-2-quic_janathot@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add the OPP tables for each CPU clusters (cpu0-1, cpu2-3-4, cpu5-6 & cpu7)
to permit scaling the Last Level Cache Controller (LLCC), DDR and L3 cache
frequency by aggregating bandwidth requests of all CPU core with referenc
to the current OPP they are configured in by the LMH/EPSS hardware.
The effect is a proper caches & DDR frequency scaling when CPU cores
changes frequency.
The OPP tables were built using the downstream memlat ddr, llcc & l3
tables for each cluster types with the actual EPSS cpufreq LUT tables
from running HDK and QRD devices.
The cpu2 and cpu5 tables are similar but must be kept separate to
take in account that they define OPP for shared CPUs of two different
clusters that can scale separately, thus vote different bandwidths.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250211-topic-sm8650-ddr-bw-scaling-v2-3-a0c950540e68@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add the interconnect entry for each cpu, with 3 different paths:
- CPU to Last Level Cache Controller (LLCC)
- Last Level Cache Controller (LLCC) to DDR
- L3 Cache from CPU to DDR interface
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250211-topic-sm8650-ddr-bw-scaling-v2-2-a0c950540e68@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add the OSC L3 Cache controller node.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250211-topic-sm8650-ddr-bw-scaling-v2-1-a0c950540e68@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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The X Elite implements Server Base System Architecture (SBSA) specification
compliant generic watchdog.
Describe it.
Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20250212-x1e80100-add-watchdog-v2-1-a73897f0dad5@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add support for vadc and adc-tm channels which are used for
monitoring thermistors present on the platform.
- Add the necessary includes for qcom,spmi-adc7-pm7325 and
qcom,spmi-adc7-pmk8350.
- Add thermal zones for quiet-thermal, sdm-skin-thermal, and
xo-thermal, and define their polling delays and thermal sensors.
- Configure the pm7325_temp_alarm node to use the pmk8350_vadc
channel for thermal monitoring.
- Configure the pmk8350_adc_tm node to enable its thermal sensors
and define their registers and settings.
- Configure the pmk8350_vadc node to define its channels and settings
Signed-off-by: Rakesh Kota <quic_kotarake@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250212113342.873086-1-quic_kotarake@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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There are 4 Qualcomm PMIC Die Temp Alarm Sensor Devices under windows os,
in separate dt files, pm8350c and pmr735a have already support temp alarm,
add the rest 2 devices for sc8280xp-pmic.
Temperature trip points are from dsdt(Temp. in tenths of degrees Kelvin).
example:
Name (TPSV, 0x0E60) // 0x0E60 - 2730 = 950
Method (_PSV, 0, NotSerialized) // _PSV: Passive Temperature
{
Return (\_SB.TZ15.TPSV)
}
Name (TCRT, 0x0F28) // 0X0F28 - 2730 = 1150
Method (_CRT, 0, NotSerialized) // _CRT: Critical Temperature
{
Return (\_SB.TZ15.TCRT)
}
Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
Link: https://lore.kernel.org/r/20250111083209.262269-2-mitltlatltl@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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According to the binding for qcom,spmi-pmic-arb, the cell 1 should be
slave id, the slave id of pmc8280_2 is 3.
Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250111083209.262269-1-mitltlatltl@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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There is no use wasting power on keeping the links between the CPU and
something else online when the CPUs are online. Change the interconnect
tag for such paths, so that RPMh is requested to automatically
clock-gate those when possible.
Keeping these paths online is also a potential power collapse blocker,
however this commit alone doesn't magically fix all the remaining
TODOs related to suspend.
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250111-topic-x1e_fixups-v1-2-77dc39237c12@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Pull SoC devicetree updates from Arnd Bergmann:
"We see the addition of eleven new SoCs, including a total of sixx
arm64 chips from Qualcomm alone. Overall, the Qualcomm platforms once
again make up the majority of all changes, after a couple of quieter
releases.
The new SoCs in this branch are:
- Microchip sama7d65 is a new 32-bit embedded chip with a single
Cortex-A7 and the current high end of the old Atmel SoC line.
- Samsung Exynos 9810 is a mobile phone chip used in some older
phones like the Samsung Galaxy S9
- Renesas R-Car V4H ES3.0 (R8A779G3) is an updated version of the V4H
(R8A779G0) low-power automotive SoC
- Renesas RZ/G3E (R0A09G047) is a family of embedded chips using
Cortex-A55 cores
- Qualcomm Snapdragon 8 Elite (SM8750) is a new phone chip based on
Qualcomm's Oryon CPU cores.
- Qualcomm Snapdragon AR2 (SAR2130P) is a SoC for augmented reality
glasses.
- Qualcomm IQ6 (QCS610) and IQ8 (QCS8300) are two industrial IOT
platforms.
- Snapdragon 425 (MSM8917) is a mobile phone SoC from 2016
- Qualcomm IPQ5424 is a Wi-Fi 7 networking chip
All of the above are part of already supported SoC families that only
need new devicetree files. Two additional SoCs in new families are
part of a separate branch.
There are 48 new machines in total, including six arm32 ones based on
aspeed. broadcom, microchip and st SoCs all using Cortex-A7 cores, and
a single risc-v board, the Banana Pi R3.
The remaining ones use arm64 chips from Broadcom, Samsung, NXP,
Mediatek, Qualcomm, Renesas and Rockchips and cover development
boards, phones, laptops, industrial machines routers.
A lot of ongoing work is for cleaning up build time warnings and other
issues, in addition to the new machines and added features"
* tag 'soc-dt-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (619 commits)
arm64: tegra: Fix Tegra234 PCIe interrupt-map
arm64: dts: qcom: x1e80100-romulus: Update firmware nodes
arm64: dts: rockchip: add DTs for Firefly ITX-3588J and its Core-3588J SoM
dt-bindings: arm: rockchip: Add Firefly ITX-3588J board
arm64: dts: rockchip: Add Orange Pi 5 Max board
dt-bindings: arm: rockchip: Add Xunlong Orange Pi 5 Max
arm64: dts: rockchip: refactor common rk3588-orangepi-5.dtsi
arm64: dts: rockchip: add WLAN to rk3588-evb1 controller
arm64: dts: rockchip: increase gmac rx_delay on rk3399-puma
arm64: dts: rockchip: Delete redundant RK3328 GMAC stability fixes
arm64: tegra: Disable Tegra234 sce-fabric node
arm64: tegra: Fix typo in Tegra234 dce-fabric compatible
arm64: tegra: Fix DMA ID for SPI2
arm64: dts: qcom: msm8916-samsung-serranove: Add display panel
arm64: dts: qcom: sm8650: Add 'global' interrupt to the PCIe RC nodes
arm64: dts: qcom: sm8550: Add 'global' interrupt to the PCIe RC nodes
arm64: dts: qcom: Remove unused and undocumented properties
arm64: dts: qcom: sdm450-lenovo-tbx605f: add DSI panel nodes
arm64: dts: qcom: pmi8950: add LAB-IBB nodes
arm64: dts: qcom: ipq5424: enable the download mode support
...
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Other x1e machines use _dtbs.elf for these firmwares, which matches the
filenames shipped by Windows.
Fixes: 09d77be56093 ("arm64: dts: qcom: Add support for X1-based Surface Laptop 7 devices")
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250108124500.44011-1-joel@jms.id.au
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add the Samsung S6E88A0-AMS427AP24 panel to the device tree for the
Samsung Galaxy S4 Mini Value Edition. By default the panel displays
everything horizontally flipped, so add "flip-horizontal" to the panel
node to correct that.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Co-developed-by: Jakob Hauser <jahau@rocketmail.com>
Signed-off-by: Jakob Hauser <jahau@rocketmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241114220718.12248-1-jahau@rocketmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt
to the host CPUs. This interrupt can be used by the device driver to
identify events such as PCIe link specific events, safety events, etc...
Hence, add it to the PCIe RC node along with the existing MSI interrupts.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20241126-topic-sm8x50-pcie-global-irq-v1-3-4049cfccd073@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt
to the host CPUs. This interrupt can be used by the device driver to
identify events such as PCIe link specific events, safety events, etc...
Hence, add it to the PCIe RC node along with the existing MSI interrupts.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20241126-topic-sm8x50-pcie-global-irq-v1-2-4049cfccd073@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Remove properties which are both unused in the kernel and undocumented.
Most likely they are leftovers from downstream.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241115193435.3618831-1-robh@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add the necessary nodes to enable the DSI panel on the
Lenovo Smart Tab M10 tablet.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241115-topic-sdm450-upstream-lab-ibb-v1-2-8a8e74befbfe@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add the PMI8950 LAB-IBB regulator nodes, with the
PMI8998 compatible as fallback.
The LAB-IBB regulators are used as panels supplies
on existing phones or tablets.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241115-topic-sdm450-upstream-lab-ibb-v1-1-8a8e74befbfe@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Enable support for download mode to collect RAM dumps in case
of system crash, facilitating post mortem analysis.
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241204141416.1352545-3-quic_mmanikan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add an scm node to interact with the secure world.
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241204133627.1341760-3-quic_mmanikan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Qualcomm IP catalog says that all CAMSS interrupts is edge rising,
fix it in the CAMSS device tree node for sm8250 SoC.
Fixes: 30325603b910 ("arm64: dts: qcom: sm8250: camss: Add CAMSS block definition")
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20241127122950.885982-7-vladimir.zapolskiy@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Qualcomm IP catalog says that all CAMSS interrupts is edge rising,
fix it in the CAMSS device tree node for sdm845 SoC.
Fixes: d48a6698a6b7 ("arm64: dts: qcom: sdm845: Add CAMSS ISP node")
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20241127122950.885982-6-vladimir.zapolskiy@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Qualcomm IP catalog says that all CAMSS interrupts are edge rising,
fix it in the CAMSS device tree node for sc8280xp SoC.
Fixes: 5994dd60753e ("arm64: dts: qcom: sc8280xp: camss: Add CAMSS block definition")
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20241127122950.885982-5-vladimir.zapolskiy@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Enable primary USB controller on QCS8300 Ride platform. The primary USB
controller is made "peripheral", as this is intended to be connected to
a host for debugging use cases.
For using the controller in host mode, changing the dr_mode and adding
appropriate pinctrl nodes to provide vbus would be sufficient.
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241114055152.1562116-3-quic_kriskura@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add support for USB controllers on QCS8300. The second
controller is only High Speed capable.
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241114055152.1562116-2-quic_kriskura@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add support for GPU, Video, Camera and Display clock controllers on
Qualcomm QCS8300 platform.
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Link: https://lore.kernel.org/r/20241114-qcs8300-mm-cc-dt-patch-v1-1-7a974508c736@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add coresight components on Qualcomm SM8450 Soc. The components include
TMC ETF/ETR, ETE, STM, TPDM, CTI.
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
Link: https://lore.kernel.org/r/20250107090031.3319-3-quic_jinlmao@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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For both the controller instances, size of the 'addr_space' region should
be 0x1fe00000 as per the hardware memory layout.
Otherwise, endpoint drivers cannot request even reasonable BAR size of 1MB.
Cc: stable@vger.kernel.org # 6.11
Fixes: c5f5de8434ec ("arm64: dts: qcom: sa8775p: Add ep pcie1 controller node")
Fixes: 1924f5518224 ("arm64: dts: qcom: sa8775p: Add ep pcie0 controller node")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20241231130224.38206-2-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Enable UFS on the Qualcomm QCS615 Ride platform.
Signed-off-by: Sayali Lokhande <quic_sayalil@quicinc.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Co-developed-by: Xin Liu <quic_liuxin@quicinc.com>
Signed-off-by: Xin Liu <quic_liuxin@quicinc.com>
Link: https://lore.kernel.org/r/20241216095439.531357-4-quic_liuxin@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add the UFS Host Controller node and its PHY for QCS615 SoC.
Signed-off-by: Sayali Lokhande <quic_sayalil@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Co-developed-by: Xin Liu <quic_liuxin@quicinc.com>
Signed-off-by: Xin Liu <quic_liuxin@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241216095439.531357-3-quic_liuxin@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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The IPQ5424 SoC has both USB2.0 and USB3.0 controllers. The USB3.0
can connect to either of USB2.0 or USB3.0 phy and operate in the
respective mode.
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241118052839.382431-7-quic_varada@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add a DT node for Last level cache (aka. system cache) controller
which provides control over the last level cache present on
IPQ5424 SoCs.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20241121051935.1055222-4-quic_varada@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add coresight components: Funnel, ETE and ETF for SM8650.
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com>
Link: https://lore.kernel.org/r/20250107-sm8650-cs-dt-v4-1-2113b18754ea@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Back when the CRD support was brought up, the usb_2 controller didn't
have anything connected to it in order to test it properly, so it was
never enabled.
On the Lenovo ThinkPad T14s, the usb_2 controller has the fingerprint
controller connected to it. So enabling it, proved that the interrupts
lines were wrong from the start.
Fix both the pwr_event and the DWC ctrl_irq lines, according to
documentation.
Fixes: 4af46b7bd66f ("arm64: dts: qcom: x1e80100: Add USB nodes")
Cc: stable@vger.kernel.org # 6.9
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20250107-x1e80100-fix-usb2-controller-irqs-v1-1-4689aa9852a7@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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On Lenovo ThinkPad T14s, the fingerprint reader placed in the power
button is connected via the usb_2 controller. The controller has only
a USB 2.0 PHY which is then connected via a NXP PTN3222 eUSB2 repeater,
which in turn is connected to the Goodix fingerprint reader.
So enable all the usb_2 controller and PHY nodes, set dual-role mode to
host and describe the eUSB2 repeater in order to get the fingerprint
reader discovered.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20250107-x1e80100-t14-enable-fingerprint-sensor-v1-1-8fd911d39ad1@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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