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2025-06-19arm64: dts: rockchip: add SDIO controller on RK3576Alexey Charkov
RK3576 has one more SD/MMC controller than are currently listed in its .dtsi, with the missing one intended as an SDIO controller. Add the missing node (tested with the onboard WiFi module on ArmSoM Sige5 v1.2) Signed-off-by: Alexey Charkov <alchark@gmail.com> Link: https://lore.kernel.org/r/20250614-sige5-updates-v2-2-3bb31b02623c@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-19arm64: dts: rockchip: Enable gpu on rk3576-evb1-v10Andy Yan
Enable gpu for rk3576 evb. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Link: https://lore.kernel.org/r/20250618063609.690332-1-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-19arm64: dts: rockchip: Update the PinePhone Pro panel descriptionOlivier Benjamin
Fix a few issues in the panel section of the PinePhone Pro DTS: - add the second part of the Himax HX8394 LCD panel controller compatible - as proposed by Diederik de Haas, reuse the mipi_out and ports definitions from rk3399-base.dtsi instead of redefining them - add a pinctrl for the LCD_RST signal for LCD1, derived from LCD1_RST, which is on GPIO4_D1, as documented on pages 11 and 16 of the PinePhone Pro schematic Signed-off-by: Olivier Benjamin <olivier.benjamin@bootlin.com> Reviewed-by: Diederik de Haas <didi.debian@cknow.org> Link: https://lore.kernel.org/r/20250619-dtb_fixes-v3-1-9cb02ddd8ce4@bootlin.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-10arm64: dts: rockchip: convert rk3562 to their dt-binding constantsHeiko Stuebner
Now that the binding head has been merged, convert the power-domain ids back to these constants for easier handling. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250510161531.2086706-1-heiko@sntech.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-10arm64: dts: rockchip: Add Luckfox Omni3576 Board supportJohn Clark
Add device tree for the Luckfox Omni3576 Carrier Board with Core3576 Module, powered by the Rockchip RK3576 SoC with four Cortex-A72 cores, four Cortex-A53 cores, and a Mali-G52 MC3 GPU. This initial implementation enables essential functionality for booting Linux and basic connectivity. Supported and tested features: - UART for serial console - SD card for storage - PCIe with NVMe SSD (detected, mounted, and fully functional) - USB 2.0 host ports - RK806 PMIC for power management - RTC with timekeeping and wake-up - GPIO-controlled LED with heartbeat trigger - eMMC (enabled, not populated on tested board) The device tree provides a foundation for further peripheral support, such as WiFi, MIPI-DSI, HDMI, and Ethernet, in future updates. Tested on Linux 6.15-rc4 Based on the Luckfox SDK, which derives from Rockchip’s SDK examples, with relevant changes to align with upstream Linux. Signed-off-by: John Clark <inindev@gmail.com> Link: https://lore.kernel.org/r/20250516002713.145026-4-inindev@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-10arm64: dts: rockchip: Remove workaround that prevented Turing RK1 GPU power ↵Sam Edwards
regulator control The RK3588 GPU power domain cannot be activated unless the external power regulator is already on. When GPU support was added to this DT, we had no way to represent this requirement, so `regulator-always-on` was added to the `vdd_gpu_s0` regulator in order to ensure stability. A later patch series (see "Fixes:" commit) resolved this shortcoming, but that commit left the workaround -- and rendered the comment above it no longer correct. Remove the workaround to allow the GPU power regulator to power off, now that the DT includes the necessary information to power it back on correctly. Fixes: f94500eb7328b ("arm64: dts: rockchip: Add GPU power domain regulator dependency for RK3588") Signed-off-by: Sam Edwards <CFSworks@gmail.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20250608184855.130206-1-CFSworks@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-10arm64: dts: rockchip: add overlay for RockPro64 screenPeter Robinson
The Pine64 touch panel is a panel consisting of the Feiyang fy07024di26a30d panel with a Goodix gt911 touch screen. Add a device tree overlay to allow the display to be easily used on the device. This was previously included in the main device tree but left disabled by default which still required rebuilding the DT to use the device, now overlays can go upstream the overlay is the best way to handle the add on devices. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> [added the missing v2 to dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64-v2-screen.dtb ^^ rk3399-rockpro64-v2-screen-dtbs := rk3399-rockpro64-v2.dtb \ rk3399-rockpro64-screen.dtbo dropped address-cells/size-cells from panel node to fix warning about rk3399-rockpro64-screen.dtso:69.22-84.4: Warning (avoid_unnecessary_addr_size) /fragment@2/__overlay__/panel@0: unnecessary #address-cells/#size-cells without "ranges", "dma-ranges" or child "reg" property] Link: https://lore.kernel.org/r/20250518215944.178582-2-pbrobinson@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-09arm64: dts: rockchip: drop touch panel display from rockpro64Peter Robinson
The touch panel display is an optional add on for the RockPro64 so this should be an DT overlay, drop the panel options in preparation to add this as an overlay. This effectively reverts commit b65155c786c4 so as to add an overlay for it. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Link: https://lore.kernel.org/r/20250518215944.178582-1-pbrobinson@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-09arm64: dts: rockchip: Use standard PHY reset properties for RK3576 ArmSoM Sige5John Clark
Replace deprecated snps,reset-gpio, snps,reset-active-low, and snps,reset-delays-us in gmac0 and gmac1 nodes with standard reset-gpios, reset-assert-us, and reset-deassert-us in rgmii_phy0 and rgmii_phy1 nodes. Add pinctrl properties to PHY nodes and define gmac0_rst and gmac1_rst in pinctrl node. Reorder phy-handle for consistency. Signed-off-by: John Clark <inindev@gmail.com> Link: https://lore.kernel.org/r/20250520003332.163124-2-inindev@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-09arm64: dts: rockchip: add ROCK 5T device treeNicolas Frattaroli
The RADXA ROCK 5T is a single board computer quite similar to the ROCK 5B+, except it has one more PCIe-to-Ethernet controller (at the expense of a USB3 port) and a barrel jack for power input instead. Some pins are shuffled around as well. Add a device tree for it. Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20250520-add-rock5t-v2-4-1f1971850a20@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-09arm64: dts: rockchip: move common ROCK 5B/+ nodes into own treeNicolas Frattaroli
A few device tree nodes are shared between ROCK 5B and ROCK 5B+ that are not shared with ROCK 5T. Move them into their own device tree include. Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20250520-add-rock5t-v2-3-1f1971850a20@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-09arm64: dts: rockchip: rename rk3588-rock-5b.dtsiNicolas Frattaroli
As subsequent patches will add ROCK 5T support, rename the .dtsi file to reflect that it's shared between ROCK 5B, ROCK 5B+ and ROCK 5T. This is done separately from moving the 5B and 5B+ only nodes to a common tree so that the history stays bisectable and the diff easily reviewable. Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20250520-add-rock5t-v2-2-1f1971850a20@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-09arm64: dts: rockchip: Add spi nodes for RK3528Chukun Pan
There are 2 SPI controllers on the RK3528 SoC, describe it. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Link: https://lore.kernel.org/r/20250520100102.1226725-3-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-09arm64: dts: rockchip: add DTs for Sakura Pi RK3308BHsun Lai
The Sakura Pi RK3308B is a SBC based on the Rockchip RK3308 SoC. Link: https://github.com/Sakura-Pi Link: https://docs.sakurapi.org/article/sakurapi-rk3308b/introduce The device contains the following hardware that is tested/working: - 4 or 8GB eMMC - SDMMC card slot - Realtek SDIO WiFi 5/BT - 256 or 512MB of RAM - USB 2.0 port - OTG port Signed-off-by: Hsun Lai <i@chainsx.cn> Link: https://lore.kernel.org/r/20250521131108.5710-4-i@chainsx.cn Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-09arm64: dts: rockchip: Add cd-gpios for sdcard detect on Cool Pi 4BAndy Yan
cd-gpios is used for sdcard detects for sdmmc. Fixes: 3f5d336d64d6 ("arm64: dts: rockchip: Add support for rk3588s based board Cool Pi 4B") Signed-off-by: Andy Yan <andyshrk@163.com> Link: https://lore.kernel.org/r/20250524064223.5741-2-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-09arm64: dts: rockchip: Add cd-gpios for sdcard detect on Cool Pi CM5Andy Yan
cd-gpios is used for sdcard detects for sdmmc. Fixes: 791c154c3982 ("arm64: dts: rockchip: Add support for rk3588 based board Cool Pi CM5 EVB") Signed-off-by: Andy Yan <andyshrk@163.com> Link: https://lore.kernel.org/r/20250524064223.5741-1-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-09arm64: dts: rockchip: Fix cover detection on PineNoteDiederik de Haas
The SW_MACHINE_COVER switch event was added to input event codes to detect the removal of the back cover of the N900. But on the PineNote its purpose is to detect when the front cover gets closed, just like when a laptop lid is closed. Therefore SW_LID is the appropriate linux code and not SW_MACHINE_COVER. Reported-by: hrdl <git@hrdl.eu> Helped-by: phantomas <phantomas@phantomas.xyz> Link: https://lore.kernel.org/r/270f27c9-afd6-171d-7dce-fe1d71dd8f9a@wizzup.org/ Signed-off-by: Diederik de Haas <didi.debian@cknow.org> Link: https://lore.kernel.org/r/20250526161506.139028-1-didi.debian@cknow.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-09arm64: dts: rockchip: Adjust the HDMI DDC IO driver strength for rk3588Andy Yan
For the RK3588 HDMI controller, the falling edge of DDC SDA and SCL almost coincide and cannot be adjusted by HDMI registrer, resulting in poor compatibility of DDC communication. An improvement of the compatibility of DDC can be done by increasing the driver strength of SCL and decreasing the driver strength of SDA to increase the slope of the falling edge. It should be noted that the maximum driving strength of hdmim0_tx1_scl is only 3, which is different from that of the other IOs. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Tested-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20250522020537.1884771-1-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-09arm64: dts: rockchip: fix rk3576 pcie1 linux,pci-domainShawn Lin
pcie0 already used 0 as its pci-domain, so pcie1 will fail to allocate the same pci-domain if both of them are used. rk-pcie 2a210000.pcie: PCIe Link up, LTSSM is 0x130011 rk-pcie 2a210000.pcie: PCIe Gen.2 x1 link up rk-pcie 2a210000.pcie: Scanning root bridge failed rk-pcie 2a210000.pcie: failed to initialize host Fixes: d4b9fc2af45d ("arm64: dts: rockchip: Add rk3576 pcie nodes") Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Link: https://lore.kernel.org/r/1748918140-212263-1-git-send-email-shawn.lin@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-09arm64: dts: rockchip: Document unused device on i2c1Chris Morgan
Update the i2c1 bus noting that the unknown/unused device at 0x3c is an iSmartWare SW2001 "encryption IC". Based on the documentation I was able to find, this IC appears to be used to authenticate a device for certain programs to ensure they only run on authorized devices as a form of digital rights management. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Link: https://lore.kernel.org/r/20250604024119.381337-1-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-09arm64: dts: rockchip: support Ethernet Switch adapter for RK3588 JaguarQuentin Schulz
This adds support for the Ethernet Switch adapter connected to the mezzanine connector on RK3588 Jaguar. This adapter has a KSZ9896 Ethernet Switch with 4 1GbE Ethernet connectors, two user controllable LEDs, and an M12 12-pin connector which exposes the following signals: - RS232/RS485 (max 250Kbps/500Kbps, RX pin1, TX pin2) - two digital inputs (pin4 routed to GPIO3_C5 on SoC, pin5 to GPIO4_B4) - two digital outputs (pin7 routed to GPIO3_D3 on SoC, pin8 to GPIO3_D1) - two analog inputs (pin10 to channel1 of ADS1015, pin11 to channel2) Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> [Andrew's review for gmac1 and switch@5f parts] Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20250604-jaguar-mezz-eth-switch-v3-1-c68123240f9e@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-06-09arm64: dts: rockchip: Add DSI panel support for gameforce-aceChris Morgan
Enable the DSI controller, DSI DCPHY, and Huiling hl055fhav028c 1080x1920 panel for the Gameforce Ace. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Link: https://lore.kernel.org/r/20250603193930.323607-5-macroalpha82@gmail.com [moved lcd_rst pin into a lcd pinctrl group with lcd_bl_en] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-31Merge tag 'soc-dt-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull SoC devicetree updates from Arnd Bergmann: "There are 11 newly supported SoCs, but these are all either new variants of existing designs, or straight reuses of the existing chip in a new package: - RK3562 is a new chip based on the old Cortex-A53 core, apparently a low-cost version of the Cortex-A55 based RK3568/RK3566. - NXP i.MX94 is a minor variation of i.MX93/i.MX95 with a different set of on-chip peripherals. - Renesas RZ/V2N (R9A09G056) is a new member of the larger RZ/V2 family - Amlogic S6/S7/S7D - Samsung Exynos7870 is an older chip similar to Exynos7885 - WonderMedia wm8950 is a minor variation on the wm8850 chip - Amlogic s805y is almost idential to s805x - Allwinner A523 is similar to A527 and T527 - Qualcomm MSM8926 is a variant of MSM8226 - Qualcomm Snapdragon X1P42100 is related to R1E80100 There are also 65 boards, including reference designs for the chips above, this includes - 12 new boards based on TI K3 series chips, most of them from Toradex - 10 devices using Rockchips RK35xx and PX30 chips - 2 phones and 2 laptops based on Qualcomm Snapdragon designs - 10 NXP i.MX8/i.MX9 boards, mostly for embedded/industrial uses - 3 Samsung Galaxy phones based on Exynos7870 - 5 Allwinner based boards using a variety of ARMv8 chips - 9 32-bit machines, each based on a different SoC family Aside from the new hardware, there is the usual set of cleanups and newly added hardware support on existing machines, for a total of 965 devicetree changesets" * tag 'soc-dt-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (956 commits) MAINTAINERS, mailmap: update Sven Peter's email address arm64: dts: renesas: rzg3e-smarc-som: Reduce I2C2 clock frequency arm64: dts: nuvoton: Add pinctrl ARM: dts: samsung: sp5v210-aries: Align wifi node name with bindings arm64: dts: blaize-blzp1600: Enable GPIO support dt-bindings: clock: socfpga: convert to yaml arm64: dts: rockchip: move rk3562 pinctrl node outside the soc node arm64: dts: rockchip: fix rk3562 pcie unit addresses arm64: dts: rockchip: move rk3528 pinctrl node outside the soc node arm64: dts: rockchip: remove a double-empty line from rk3576 core dtsi arm64: dts: rockchip: move rk3576 pinctrl node outside the soc node arm64: dts: rockchip: fix rk3576 pcie unit addresses arm64: dts: rockchip: Drop assigned-clock* from cpu nodes on rk3588 arm64: dts: rockchip: Add missing SFC power-domains to rk3576 Revert "arm64: dts: mediatek: mt8390-genio-common: Add firmware-name for scp0" arm64: dts: mediatek: mt8188: Address binding warnings for MDP3 nodes arm64: dts: mt6359: Rename RTC node to match binding expectations arm64: dts: mt8365-evk: Add goodix touchscreen support arm64: dts: mediatek: mt8188: Add missing #reset-cells property arm64: dts: airoha: en7581: Add PCIe nodes to EN7581 SoC evaluation board ...
2025-05-20arm64: dts: rockchip: move rk3562 pinctrl node outside the soc nodeHeiko Stuebner
The non-mmio pinctrl node is not supposed to be inside the soc simple-bus as dtc points out: ../arch/arm64/boot/dts/rockchip/rk3562.dtsi:1115.20-1181.5: Warning (simple_bus_reg): /soc/pinctrl: missing or empty reg/ranges property Move the pinctrl node outside and adapt the indentation. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250518220449.2722673-7-heiko@sntech.de
2025-05-20arm64: dts: rockchip: fix rk3562 pcie unit addressesHeiko Stuebner
The rk3562 pcie node currently uses the apb register as its unit address which is the second reg area defined in the binding. As can be seen by the dtc warnings like ../arch/arm64/boot/dts/rockchip/rk3562.dtsi:624.26-675.5: Warning (simple_bus_reg): /soc/pcie@ff500000: simple-bus unit address format error, expected "fe000000" using the first reg area as the unit address seems to be preferred. This is the dbi area per the binding, so adapt the unit address accordingly and move the nodes to their new position. With the move also move the reg + reg-names below the compatible, as is the preferred position. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250518220449.2722673-6-heiko@sntech.de
2025-05-20arm64: dts: rockchip: move rk3528 pinctrl node outside the soc nodeHeiko Stuebner
The non-mmio pinctrl node is not supposed to be inside the soc simple-bus as dtc points out: ../arch/arm64/boot/dts/rockchip/rk3528.dtsi:870.20-936.5: Warning (simple_bus_reg): /soc/pinctrl: missing or empty reg/ranges property Move the pinctrl node outside and adapt the indentation. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250518220449.2722673-5-heiko@sntech.de
2025-05-20arm64: dts: rockchip: remove a double-empty line from rk3576 core dtsiHeiko Stuebner
Two empty lines between nodes, is one too many. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250518220449.2722673-4-heiko@sntech.de
2025-05-20arm64: dts: rockchip: move rk3576 pinctrl node outside the soc nodeHeiko Stuebner
The non-mmio pinctrl node is not supposed to be inside the soc simple-bus as dtc points out: ../arch/arm64/boot/dts/rockchip/rk3576.dtsi:2351.20-2417.5: Warning (simple_bus_reg): /soc/pinctrl: missing or empty reg/ranges property Move the pinctrl node outside and adapt the indentation. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202505150745.PQT9TLYX-lkp@intel.com/ Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250518220449.2722673-3-heiko@sntech.de
2025-05-20arm64: dts: rockchip: fix rk3576 pcie unit addressesHeiko Stuebner
The rk3576 pcie nodes currently use the apb register as their unit address which is the second reg area defined in the binding. As can be seen by the dtc warnings like ../arch/arm64/boot/dts/rockchip/rk3576.dtsi:1346.24-1398.5: Warning (simple_bus_reg): /soc/pcie@2a200000: simple-bus unit address format error, expected "22000000" ../arch/arm64/boot/dts/rockchip/rk3576.dtsi:1400.24-1452.5: Warning (simple_bus_reg): /soc/pcie@2a210000: simple-bus unit address format error, expected "22400000" using the first reg area as the unit address seems to be preferred. This is the dbi area per the binding, so adapt the unit address accordingly and move the nodes to their new position. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202505150745.PQT9TLYX-lkp@intel.com/ Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250518220449.2722673-2-heiko@sntech.de
2025-05-20arm64: dts: rockchip: Drop assigned-clock* from cpu nodes on rk3588Diederik de Haas
The assigned-clocks and assigned-clock-rates properties were moved from the scmi_clk node onto cpu nodes in commit 87810bda8a84 ("arm64: dts: rockchip: Fix SCMI assigned clocks on rk3588s") During review of v1 of that patch set, the following comment was made: why aren't you using OPP tables to define CPU frequencies. Assigned-clocks looks like a temporary hack because you haven't done proper OPP tables. Some time later, proper OPP tables for rk3588 were added in commit 276856db91b4 ("arm64: dts: rockchip: Add OPP data for CPU cores on RK3588") So this 'temporary hack' is no longer needed. Dropping it fixes the following dtb validation issues: cpu@0: Unevaluated properties are not allowed ('assigned-clock-rates', 'assigned-clocks' were unexpected) cpu@400: Unevaluated properties are not allowed ('assigned-clock-rates', 'assigned-clocks' were unexpected) cpu@600: Unevaluated properties are not allowed ('assigned-clock-rates', 'assigned-clocks' were unexpected) Link: https://lore.kernel.org/linux-rockchip/CAL_JsqL_EogoKOQ1xwU75=rJSC4o7yV3Jej4vadtacX2Pt3-hw@mail.gmail.com/ Signed-off-by: Diederik de Haas <didi.debian@cknow.org> Link: https://lore.kernel.org/r/20250519101909.62754-1-didi.debian@cknow.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-20arm64: dts: rockchip: Add missing SFC power-domains to rk3576Sebastian Reichel
Add the power-domains for the RK3576 SFC nodes according to the TRM part 1. This fixes potential SErrors when accessing the SFC registers without other peripherals (e.g. eMMC) doing a prior power-domain enable. For example this is easy to trigger on the Rock 4D, which enables the SFC0 interface, but does not enable the eMMC interface at the moment. Cc: stable@vger.kernel.org Fixes: 36299757129c8 ("arm64: dts: rockchip: Add SFC nodes for rk3576") Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20250520-rk3576-fix-fspi-pmdomain-v1-1-f07c6e62dadd@kernel.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-15arm64: dts: rockchip: Improve LED config for NanoPi R5SDiederik de Haas
The NanoPi R5S has 4 GPIO LEDs, a RED one for SYStem power and 3 green LEDs meant to indicate that a cable is connected to either of the 2.5GbE LAN ports or the 1GbE WAN port. In the NanoPi R5S schematic (2204; page 19) as well as on the PCB and on the case, SYS is used and not POWER. So replace 'power' with 'sys'. But keep the 'power_led' label/phandle even though the kernel doesn't use it, but it may be used outside of it. The SYStem LED already had "heartbeat" as its default-trigger. Set the default-trigger to "netdev" for the NICs so they will show when LAN1/LAN2/WAN is connected and set their default-state to "off". Also assign labels as close as possible to the labels on the case, while still being descriptive enough in their own right. Signed-off-by: Diederik de Haas <didi.debian@cknow.org> Link: https://lore.kernel.org/r/20250513170056.96259-1-didi.debian@cknow.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-15arm64: dts: rockchip: add px30-pp1516 base dtsi and board variantsHeiko Stuebner
PP1516 are Touchscreen devices built around the PX30 SoC and companion devices to PX30-Cobra, again with multiple display options. The devices feature an EMMC, OTG port and a 720x1280 display with a touchscreen and camera Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250514150745.2437804-7-heiko@sntech.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-15arm64: dts: rockchip: add px30-cobra base dtsi and board variantsHeiko Stuebner
Cobra are Touchscreen devices built around the PX30 SoC using a variety of display options. The devices feature an EMMC, network port, usb host + OTG ports and a 720x1280 display with a touchscreen. Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250514150745.2437804-5-heiko@sntech.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-15arm64: dts: rockchip: move reset to dedicated eth-phy node on ringneckHeiko Stuebner
Using snps,reset-* properties to handle the ethernet-phy resets is deprecated and instead a real phy node should be used. Move the Ringneck phy-reset properties to such a node Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de> Tested-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250514150745.2437804-3-heiko@sntech.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-15arm64: dts: rockchip: add basic mdio node to px30Heiko Stuebner
Using snps,reset-* properties for handling the phy-reset is deprecated and instead a real phy node should be defined that then contains the reset-gpios handling. To facilitate this, add the core mdio node under the px30's gmac, similar to how the other Rockchip socs already do this. Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de> Link: https://lore.kernel.org/r/20250514150745.2437804-2-heiko@sntech.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-15arm64: dts: rockchip: disable unrouted USB controllers and PHY on RK3399 ↵Quentin Schulz
Puma with Haikou The u2phy0_host port is the part of the USB PHY0 (namely the HOST0_DP/DM lanes) which routes directly to the USB2.0 HOST controller[1]. The other lanes of the PHY are routed to the USB3.0 OTG controller (dwc3), which we do use. The HOST0_DP/DM lanes aren't routed on RK3399 Puma so let's simply disable the USB2.0 controllers. USB3 OTG has been known to be unstable on RK3399 Puma Haikou for a while, one of the recurring issues being that only USB2 is detected and not USB3 in host mode. Reading the justification above and seeing that we are keeping u2phy0_host in the Haikou carrierboard DTS probably may have bothered you since it should be changed to u2phy0_otg. The issue is that if it's switched to that, USB OTG on Haikou is entirely broken. I have checked the routing in the Gerber file, the lanes are going to the expected ball pins (that is, NOT HOST0_DP/DM). u2phy0_host is for sure the wrong part of the PHY to use, but it's the only one that works at the moment for that board so keep it until we figure out what exactly is broken. No intended functional change. [1] https://rockchip.fr/Rockchip%20RK3399%20TRM%20V1.3%20Part2.pdf Chapter 2 USB2.0 PHY Fixes: 2c66fc34e945 ("arm64: dts: rockchip: add RK3399-Q7 (Puma) SoM") Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com> Link: https://lore.kernel.org/r/20250425-onboard_usb_dev-v2-5-4a76a474a010@thaumatec.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-15arm64: dts: rockchip: disable unrouted USB controllers and PHY on RK3399 PumaQuentin Schulz
The u2phy1_host port is the part of the USB PHY1 (namely the HOST1_DP/DM lanes) which routes directly to the USB2.0 HOST controller[1]. The other lanes of the PHY are routed to the USB3.0 OTG controller (dwc3), which we do use. The HOST1_DP/DM lanes aren't routed on RK3399 Puma so let's simply disable the USB2.0 controllers and associated part in USB2.0 PHY. No intended functional change. [1] https://rockchip.fr/Rockchip%20RK3399%20TRM%20V1.3%20Part2.pdf Chapter 2 USB2.0 PHY Fixes: 2c66fc34e945 ("arm64: dts: rockchip: add RK3399-Q7 (Puma) SoM") Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com> Link: https://lore.kernel.org/r/20250425-onboard_usb_dev-v2-4-4a76a474a010@thaumatec.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-15arm64: dts: rockchip: fix internal USB hub instability on RK3399 PumaLukasz Czechowski
Currently, the onboard Cypress CYUSB3304 USB hub is not defined in the device tree, and hub reset pin is provided as vcc5v0_host regulator to usb phy. This causes instability issues, as a result of improper reset duration. The fixed regulator device requests the GPIO during probe in its inactive state (except if regulator-boot-on property is set, in which case it is requested in the active state). Considering gpio is GPIO_ACTIVE_LOW for Puma, it means it’s driving it high. Then the regulator gets enabled (because regulator-always-on property), which drives it to its active state, meaning driving it low. The Cypress CYUSB3304 USB hub actually requires the reset to be asserted for at least 5 ms, which we cannot guarantee right now since there's no delay in the current config, meaning the hub may sometimes work or not. We could add delay as offered by fixed-regulator but let's rather fix this by using the proper way to model onboard USB hubs. Define hub_2_0 and hub_3_0 nodes, as the onboard Cypress hub consist of two 'logical' hubs, for USB2.0 and USB3.0. Use the 'reset-gpios' property of hub to assign reset pin instead of using regulator. Rename the vcc5v0_host regulator to cy3304_reset to be more meaningful. Pin is configured to output-high by default, which sets the hub in reset state during pin controller initialization. This allows to avoid double enumeration of devices in case the bootloader has setup the USB hub before the kernel. The vdd-supply and vdd2-supply properties in hub nodes are added to provide correct dt-bindings, although power supplies are always enabled based on HW design. Fixes: 2c66fc34e945 ("arm64: dts: rockchip: add RK3399-Q7 (Puma) SoM") Cc: stable@vger.kernel.org # 6.6 Cc: stable@vger.kernel.org # Backport of the patch in this series fixing product ID in onboard_dev_id_table in drivers/usb/misc/onboard_usb_dev.c driver Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com> Link: https://lore.kernel.org/r/20250425-onboard_usb_dev-v2-3-4a76a474a010@thaumatec.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-15arm64: dts: rockchip: move rk3528 i2c+uart aliases to board filesHeiko Stuebner
Even though they will be the same for all boards, i2c and uart aliases are supposed to live in the individual board files, to not create aliases for disabled nodes. So move the newly added aliases for rk3528 over to the Radxa E20C board, which is the only rk3528 board right now. Fixes: d3a05f490d04 ("arm64: dts: rockchip: Add I2C controllers for RK3528") Suggested-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Yao Zi <ziyao@disroot.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250510220106.2108414-1-heiko@sntech.de
2025-05-11arm64: dts: rockchip: drop wrong spdif clock from edp1 on rk3588Heiko Stuebner
As described, the analogix-dp controller on rk3588 only supports 2 clocks and the edp0 node handles that correctly. The edp1 node on the other hand seems to have a dangling 3rd clock called spdif, that probably only exists in the vendor-tree. As that is not handled at all, remove it for now so that we adhere to the binding. Fixes: a481bb0b1ad9 ("arm64: dts: rockchip: Add eDP1 dt node for rk3588") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250509152329.2004073-1-heiko@sntech.de
2025-05-11arm64: dts: rockchip: Add RK3562 evb2 devicetreeFinley Xiao
DRAM: DDR4 Storage: eMMC PMIC: RK809 Audio: Headphone and speaker Interface: - USB3.0 HOST - USB2.0 HOST - PCIe x4 slot(pcie2x1 available) - SD card slot - GMAC - debug UART0 NOTE: the USB3.0 and the PCIe reuse the comboPHY, so the USB3.0 work in USB2 only mode. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Link: https://lore.kernel.org/r/20250509102308.761424-6-kever.yang@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-11arm64: dts: rockchip: add core dtsi for RK3562 SoCFinley Xiao
RK3562 is a SoC from Rockchip, which embedded with quad ARM Cortex-A53. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Link: https://lore.kernel.org/r/20250509102308.761424-5-kever.yang@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-10arm64: dts: rockchip: Enable Ethernet controller on Radxa E20CJonas Karlman
The Radxa E20C has two GbE ports, LAN and WAN. The LAN port is provided using a GMAC controller and a YT8531C PHY and the WAN port is provided by an RTL8111H PCIe Ethernet controller. Enable support for the LAN port on Radxa E20C. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Tested-by: Yao Zi <ziyao@disroot.org> Link: https://lore.kernel.org/r/20250509202402.260038-3-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-10arm64: dts: rockchip: Add GMAC nodes for RK3528Jonas Karlman
Rockchip RK3528 has two Ethernet controllers based on Synopsys DWC Ethernet QoS IP. Add device tree nodes for the two Ethernet controllers in RK3528. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Tested-by: Yao Zi <ziyao@disroot.org> Link: https://lore.kernel.org/r/20250509202402.260038-2-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-09arm64: dts: rockchip: add Rock 5B+Sebastian Reichel
Add ROCK 5B+, which is an improved version of the ROCK 5B with the following changes: * Memory LPDDR4X -> LPDDR5 * HDMI input connector size * eMMC socket -> onboard * M.2 E-Key is replaced by onboard RTL8852BE WLAN/BT * M.2 M-Key 1x4 lanes is replaced by 2x2 lanes * Added M.2 B-Key for USB connected WWAN modules (untested) * Add second camera port (not yet supported in upstream Linux) * Add dedicated USB-C port for device power (no impact in DT; the existing port has not been changed and the new port is handled by CH224D standalone chip) Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20250508-rock5bp-for-upstream-v2-4-677033cc1ac2@kernel.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-09arm64: dts: rockchip: move rock 5b to include fileSebastian Reichel
Radxa released some more boards, which are based on the original Rock 5B. Move its board description into an include file to avoid unnecessary duplication. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20250508-rock5bp-for-upstream-v2-1-677033cc1ac2@kernel.org Link: https://lore.kernel.org/r/20250508-rock5bp-for-upstream-v2-2-677033cc1ac2@kernel.org [The original submission was split into two elements, renaming the file and then moving some nodes around. This was done to make review easier due to the diff being smaller. This commit is a squash of both of them to facilitate bisectability and was also intended by the original author] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-09arm64: dts: rockchip: Add rk3399-evb-ind boardChaoyi Chen
General feature for rk3399 industry evaluation board: - Rockchip RK3399 - 4GB LPDDR4 - emmc5.1 - SDIO3.0 compatible TF card - 1x HDMI2.0a TX - 1x HDMI1.4b RX with TC358749XBG HDMI to MIPI CSI2 bridge chip - 1x type-c DisplayPort - 3x USB3.0 Host - 1x USB2.0 Host - 1x Ethernet / USB3.0 to Ethernet Tested with HDMI/GPU/USB2.0/USB3.0/TF card/emmc. Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> Link: https://lore.kernel.org/r/20250506034347.57-3-kernel@airkyi.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-09arm64: dts: rockchip: Enable HDMI audio on Sige5Nicolas Frattaroli
With the hdmi_sound node added to the base RK3576 SoC tree, we can now enable it on the Sige5 SBC. Do this, and also enable the corresponding SAI6 audio controller node. Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20250506-rk3576-sai-v4-4-a8b5f5733ceb@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-05-09arm64: dts: rockchip: Add analog audio on RK3576 Sige5Nicolas Frattaroli
The ArmSoM Sige5 board features an Everest ES8388 codec to provide analog stereo audio output, as well as analog audio input. The codec hangs off the i2c2 bus and responds to address 0x10. It is connected to the SAI1 audio controller of the RK3576, with one SDO (output) lane and one SDI (input) lane. The codec has two sets of outputs. One set, LOUT1/ROUT1, is connected through a set of 22uF non-polarised coupling capacitors to a 3-position connector that appears to be a clone of the JST BM03B-SURS-TF header, and is capable of mating with a JST 03SUR-32S (or JST 03SUR-36L if you prefer lemon-lime) or compatible clone connector. The right headphone output is the one closest to the Type-C DC input connector, the left headphone output is the one in the middle, and the third position, the one closest to the USB3 Type-A host connector, is puzzingly labelled as "HP_GND" in the schematic but is in fact connected to the codecs RIN1 input through a 1uF non-plarised coupling capacitor. LOUT2 and ROUT2 are routed to 1mm test pads T36 and T37 respectively. These are located on the bottom of the board, and do not go through any coupling capacitor. For use as line out, the ES8388 datasheet recommends adding 1uF coupling capacitor if one wishes to use it as a line-level output. There is also a pair of inputs for a stereo microphone, going from two 1mm testpads T34 and T35, which are decoupled with a 100pF capacitor and pulled to 3.3v and ground respectively. These inputs then go through 1uF capacitors each and end up in the LINPUT2 and RINPUT2 pins of the ES8388 codec. The codec's power inputs are routed to receive 3.3V for both its analog and digital inputs, though from different supplies. Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20250506-rk3576-sai-v4-3-a8b5f5733ceb@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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