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2020-12-02KVM: arm64: Fix memory leak on stage2 update of a valid PTEYanan Wang
When installing a new leaf PTE onto an invalid ptep, we need to get_page(ptep) to account for the new mapping. However, simply updating a valid PTE shouldn't result in any additional refcounting, as there is new mapping. This otherwise results in a page being forever wasted. Address this by fixing-up the refcount in stage2_map_walker_try_leaf() if the PTE was already valid, balancing out the later get_page() in stage2_map_walk_leaf(). Signed-off-by: Yanan Wang <wangyanan55@huawei.com> [maz: update commit message, add comment in the code] Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20201201201034.116760-2-wangyanan55@huawei.com
2020-12-01kbuild: Hoist '--orphan-handling' into KconfigNathan Chancellor
Currently, '--orphan-handling=warn' is spread out across four different architectures in their respective Makefiles, which makes it a little unruly to deal with in case it needs to be disabled for a specific linker version (in this case, ld.lld 10.0.1). To make it easier to control this, hoist this warning into Kconfig and the main Makefile so that disabling it is simpler, as the warning will only be enabled in a couple places (main Makefile and a couple of compressed boot folders that blow away LDFLAGS_vmlinx) and making it conditional is easier due to Kconfig syntax. One small additional benefit of this is saving a call to ld-option on incremental builds because we will have already evaluated it for CONFIG_LD_ORPHAN_WARN. To keep the list of supported architectures the same, introduce CONFIG_ARCH_WANT_LD_ORPHAN_WARN, which an architecture can select to gain this automatically after all of the sections are specified and size asserted. A special thanks to Kees Cook for the help text on this config. Link: https://github.com/ClangBuiltLinux/linux/issues/1187 Acked-by: Kees Cook <keescook@chromium.org> Acked-by: Michael Ellerman <mpe@ellerman.id.au> (powerpc) Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Tested-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
2020-12-01arm64: sdei: Push IS_ENABLED() checks down to callee functionsWill Deacon
Handling all combinations of the VMAP_STACK and SHADOW_CALL_STACK options in sdei_arch_get_entry_point() makes the code difficult to read, particularly when considering the error and cleanup paths. Move the checking of these options into the callee functions, so that they return early if the relevant option is not enabled. Signed-off-by: Will Deacon <will@kernel.org>
2020-12-01arm64: scs: use vmapped IRQ and SDEI shadow stacksSami Tolvanen
Use scs_alloc() to allocate also IRQ and SDEI shadow stacks instead of using statically allocated stacks. Signed-off-by: Sami Tolvanen <samitolvanen@google.com> Acked-by: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20201130233442.2562064-3-samitolvanen@google.com [will: Move CONFIG_SHADOW_CALL_STACK check into init_irq_scs()] Signed-off-by: Will Deacon <will@kernel.org>
2020-12-01arm64: dts: allwinner: H5: NanoPi Neo Plus2: phy-mode rgmii-idHeinrich Schuchardt
Since commit bbc4d71d6354 ("net: phy: realtek: fix rtl8211e rx/tx delay config") network is broken on the NanoPi Neo Plus2. This patch changes the phy-mode to use internal delays both for RX and TX as has been done for other boards affected by the same commit. Fixes: bbc4d71d6354 ("net: phy: realtek: fix rtl8211e rx/tx delay config") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20201129194512.1475586-1-xypron.glpk@gmx.de
2020-12-01arm64: dts: allwinner: A64 Sopine: phy-mode rgmii-idHeinrich Schuchardt
Since commit bbc4d71d6354 ("net: phy: realtek: fix rtl8211e rx/tx delay config") iSCSI booting fails on the Pine A64 LTS. This patch changes the phy-mode to use internal delays both for RX and TX as has been done for other boards affected by the same commit. Fixes: bbc4d71d6354 ("net: phy: realtek: fix rtl8211e rx/tx delay config") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20201129162627.1244808-1-xypron.glpk@gmx.de
2020-12-01arm64: dts: imx8mm-beacon-som: Assign PMIC clockAdam Ford
The PMIC throws an errors because the clock isn't assigned to it. Fix this by assigning the clocks info. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-12-01arm64: dts: imx8mm-beacon-som: Configure RTC aliasesAdam Ford
On the i.MX8MM Beacon SOM, there is an RTC chip which is fed power from the baseboard during power off. The SNVS RTC integrated into the SoC is not fed power. Depending on the order the modules are loaded, this can be a problem if the external RTC isn't rtc0. Make the alias for rtc0 point to the external RTC all the time and rtc1 point to the SVNS in order to correctly hold date/time over a power-cycle. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-12-01arm64: dts: imx8mn: Add node for SPDIFAdam Ford
The i.MX8M Nano can support SPDIF which is compatible to the IP used on the i.MX35. Add the node. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-12-01arm64: dts: imx8mn: Add support for micfilAdam Ford
The i.MX8M Nano has supports the MICFIL digital interface. It's a 16-bit audio signal from a PDM microphone bitstream. The driver is already in the kernel, but the node is missing. Add the micfil node. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-12-01arm64: dts: imx8mn: Add SAI nodesAdam Ford
The i.MX8M Nano has several SAI nodes available to it. Enable them. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-12-01arm64: dts: imx8mn: Enable Asynchronous Sample Rate ConverterAdam Ford
The driver exists for the Enhanced Asynchronous Sample Rate Converter (EASRC) Controller, but there isn't a device tree entry for it. On the vendor kernel, they put this on a spba-bus for SDMA support. Add the node for the spba-bus with the easrc node inside. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-12-01arm64: dts: ls1028a: make the eMMC and SD card controllers use fixed indicesVladimir Oltean
As the boot order in the kernel continues to change, sometimes it may happen that the eSDHC controller mmc@2150000 (the one for eMMC) gets probed before the one at mmc@2140000 (for external SD cards). The effect is that the eMMC controller gets the /dev/mmcblk0 name, and the SD card gets /dev/mmcblk1. Since the introduction of this SoC, that has never happened in practice, even though it was never guaranteed in theory. Setting "root=/dev/mmcblk0p2" in /proc/cmdline has always caused the kernel to use the second partition from the SD card as the rootfs. The NXP development boards are typically shipped with either - LSDK, which uses "root=UUID=", or - OpenIL, which uses "root=/dev/mmcblkNp2" So for OpenIL, let's preserve that old behavior by adding some aliases which create naming consistency (for LSDK it doesn't matter): - the SD card controller uses /dev/mmcblk0 - the eMMC controller uses /dev/mmcblk1 For the Kontron SL28 boards, Michael Walle says that they are shipped with "root=UUID=" already, so the probing order doesn't matter, but it is more natural to him for /dev/mmcblk0 to be the eMMC, so let's do it the other way around there. The aliases are parsed by mmc_alloc_host() in drivers/mmc/core/host.c. Cc: Ashish Kumar <Ashish.Kumar@nxp.com> Cc: Yangbo Lu <yangbo.lu@nxp.com> Cc: Michael Walle <michael@walle.cc> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Michael Walle <michael@walle.cc> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-12-01arm64: defconfig: Enable more Librem 5 hardwareGuido Günther
This enables - CONFIG_BATTERY_MAX17042: battery chip - CONFIG_CHARGER_BQ25980: charge controller - CONFIG_DRM_PANEL_MANTIX_MLAF057WE5: LCD panel - CONFIG_GNSS/CONFIG_GNSS_MTK_SERIAL: GNSS receiver - CONFIG_IIO_ST_LSM6DSX: IMU - CONFIG_IMX_DCSS: 2nd display controller - CONFIG_LEDS_LM3692X: LCD backlight - CONFIG_REGULATOR_TPS65132: regulator for the LCD panel - CONFIG_TOUCHSCREEN_EDT_FT5X06: touch controller - CONFIG_TYPEC_TPS6598X: USB PD controller - CONFIG_VCNL4000: ambient light and proximity sensor as modules. Signed-off-by: Guido Günther <agx@sigxcpu.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-11-30arm64: dts: meson-sm1: fix typo in opp tableDongjin Kim
The freqency 1512000000 should be 1500000000. Signed-off-by: Dongjin Kim <tobetter@gmail.com> Fixes: 3d9e76483049 ("arm64: dts: meson-sm1-sei610: enable DVFS") Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201130060320.GA30098@anyang-linuxfactory-or-kr
2020-11-30arm64: dts: meson: add KHAMSIN IR remote node to SML5442TWChristian Hewitt
Set the IR keymap to the KHAMSIN remote shipped with the SML5442TW. Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201126050440.6273-1-christianshewitt@gmail.com
2020-11-30arm64: dts: meson: update the Khadas VIM3/3L LED bindingsChristian Hewitt
Update the VIM3/3L common dtsi to use the new function/color bindings. Suggested-by: Artem Lapkin <art@khadas.com> Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201125052914.4092-1-christianshewitt@gmail.com
2020-11-30arm64: dts: meson: fix spi-max-frequency on Khadas VIM2Artem Lapkin
The max frequency for the w25q32 (VIM v1.2) and w25q128 (VIM v1.4) spifc chip should be 104Mhz not 30MHz. Fixes: b8b74dda3908 ("ARM64: dts: meson-gxm: Add support for Khadas VIM2") Signed-off-by: Artem Lapkin <art@khadas.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201125024001.19036-1-christianshewitt@gmail.com
2020-11-30arm64: dts: meson: add rtc aliases to meson-khadas-vim3.dtsiChristian Hewitt
Tweak the node name to make it aliasable, then add aliases for the on-board RTC chip and meson-vrtc timer so they probe as rtc0 and rtc1 respectively. before: VIM3:~ # dmesg | grep rtc [ 3.622530] meson-vrtc ff8000a8.rtc: registered as rtc0 [ 3.622574] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:03 UTC (3) [ 3.646936] rtc-hym8563 0-0051: no valid clock/calendar values available [ 3.647125] rtc-hym8563 0-0051: registered as rtc1 [ 3.852382] rtc-hym8563 0-0051: no valid clock/calendar values available after: VIM3:~ # dmesg | grep rtc [ 3.583735] meson-vrtc ff8000a8.rtc: registered as rtc1 [ 3.633888] rtc-hym8563 0-0051: no valid clock/calendar values available [ 3.634120] rtc-hym8563 0-0051: registered as rtc0 [ 3.635250] rtc-hym8563 0-0051: no valid clock/calendar values available [ 3.635267] rtc-hym8563 0-0051: hctosys: unable to read the hardware clock [ 3.852632] rtc-hym8563 0-0051: no valid clock/calendar values available Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201124145338.17137-1-christianshewitt@gmail.com
2020-11-30arm64: dts: meson: Add capacity-dmips-mhz attributes to GXMChristian Hewitt
GXM (S912) is a big-little design with CPUs 0-3 clocked at 1.5GHz and CPUs 4-7 at 1.0GHz. Adding capacity-dmips-mhz attributes allows the scheduler to factor the different clock speeds into capacity calculations and prefer the higher-clocked cluster to improve overall performance. This was inspired by the similar change for G12B [0] boards. The diference here is that all cores are A53's so the same dmips-mhz value is used. VIM2:~ # cat /sys/devices/system/cpu/cpu*/cpufreq/scaling_cur_freq 1512000 1512000 1512000 1512000 1000000 1000000 1000000 1000000 before: VIM2:~ # cat /sys/devices/system/cpu/cpu*/cpu_capacity 1024 1024 1024 1024 1024 1024 1024 1024 after: VIM2:~ # cat /sys/devices/system/cpu/cpu*/cpu_capacity 1024 1024 1024 1024 677 677 677 677 The after value matches my table-napkin calculation: (1000000 / 1512000 = 0.661) * 1024 = 677 [0] https://github.com/torvalds/linux/commit/6eeaf4d2452ec8b1ece58776812140734fc2e088 Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201124121740.25704-1-christianshewitt@gmail.com
2020-11-30arm64: dts: meson-axg-s400: enable PCIe M.2 Key E slotsNeil Armstrong
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201120153229.3920123-5-narmstrong@baylibre.com
2020-11-30arm64: dts: meson-axg: add PCIe nodesNeil Armstrong
This adds the nodes for the : - AXG PCIe PHY, using the shared analog PCIe/MIPI DSI PHY - 2x AXG PCIe controllers Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201120153229.3920123-4-narmstrong@baylibre.com
2020-11-30arm64: dts: meson-axg: add MIPI DSI PHY nodesNeil Armstrong
This adds the nodes for : - MIPI DSI+PCIe analog phy - MIPI D-PHY Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201120152131.3918814-3-narmstrong@baylibre.com
2020-11-30arm64: dts: meson-axg: add PWRC nodeNeil Armstrong
This adds the power controller PWRC node and the corresponding ethernet power domain. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201120152131.3918814-2-narmstrong@baylibre.com
2020-11-30arm64: dts: meson: enable rtc node on Khadas VIM1/VIM2 boardsChristian Hewitt
Enable the rtc node on VIM1/VIM2 boards so users can simply attach a power cell and use the on-board RTC without modifying the device-tree. Cold boot with no cell attached is gracefully handled: VIM2:~ # dmesg | grep rtc [ 7.716150] rtc-hym8563 1-0051: no valid clock/calendar values available [ 7.716957] rtc-hym8563 1-0051: registered as rtc0 [ 7.729850] rtc-hym8563 1-0051: no valid clock/calendar values available [ 7.729877] rtc-hym8563 1-0051: hctosys: unable to read the hardware clock [ 8.126768] rtc-hym8563 1-0051: no valid clock/calendar values available Warm boot (and any boot with cell attached) recalls stored values resulting in consistently faster (re)boot times: VIM2:~ # dmesg | grep rtc [ 7.441671] rtc-hym8563 1-0051: registered as rtc0 [ 7.442663] rtc-hym8563 1-0051: setting system clock to 2020-11-16T05:49:59 UTC (1605505799) Suggested-by: Artem Lapkin <art@khadas.com> Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201116064147.12062-1-christianshewitt@gmail.com
2020-11-30arm64: defconfig: Enable RTC_DRV_HYM8563Jagan Teki
RTC HYM8563 used in the ARM64 Rockchip SoC's SDIO power sequence enablement. Enable it as module. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Link: https://lore.kernel.org/r/20201023181814.220974-1-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-11-30arm64: mte: Fix typo in macro definitionVincenzo Frascino
UL in the definition of SYS_TFSR_EL1_TF1 was misspelled causing compilation issues when trying to implement in kernel MTE async mode. Fix the macro correcting the typo. Note: MTE async mode will be introduced with a future series. Fixes: c058b1c4a5ea ("arm64: mte: system register definitions") Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/20201130170709.22309-1-vincenzo.frascino@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2020-11-30arm64: dts: qcom: c630: Define eDP bridge and panelBjorn Andersson
The Lenovo Yoga C630 drives the Boe NV133FHM-N61 eDP display from DSI using a TI SN65DSI86 bridge chip on I2C 10. Define the bridge and eDP panel and enable the display blocks. Tested-by: Steev Klimaszewski <steev@kali.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20201128034231.89750-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-30arm64: dts: qcom: c630: Fix pinctrl pins propertiesBjorn Andersson
The "pins" property takes an array of pin _names_, not pin numbers. Fix this. Tested-by: Steev Klimaszewski <steev@kali.org> Fixes: 44acee207844 ("arm64: dts: qcom: Add Lenovo Yoga C630") Link: https://lore.kernel.org/r/20201130170028.319798-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-30arm64: dts: qcom: c630: Polish i2c-hid devicesBjorn Andersson
The numbering of the i2c busses differs from ACPI and a number of typos was made in the original patch. Further more the irq flags for the various resources was not correct and i2c3 only has one of the two client devices active in any one device. Also label the various devices, for easier comparison with the ACPI tables. Tested-by: Steev Klimaszewski <steev@kali.org> Fixes: 44acee207844 ("arm64: dts: qcom: Add Lenovo Yoga C630") Link: https://lore.kernel.org/r/20201130165924.319708-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-30arm64: dts: qcom: sc7180: Add lpass cpu node for I2S driverAjit Pandey
Add the I2S controller node to sc7180 dtsi. Add pinmux for primary and secondary I2S. Reviewed-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Ajit Pandey <ajitp@codeaurora.org> Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org> Signed-off-by: V Sujith Kumar Reddy <vsujithk@codeaurora.org> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org> Link: https://lore.kernel.org/r/1600450426-14063-1-git-send-email-srivasam@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-30arm64: dts: ipq6018: Add the QPIC peripheral nodesKathiravan T
Add the QPIC BAM and QPIC NAND controller support and enable the same in board DTS file. Co-developed-by: Anusha Canchi Ramachandra Rao <anusharao@codeaurora.org> Signed-off-by: Anusha Canchi Ramachandra Rao <anusharao@codeaurora.org> Signed-off-by: Kathiravan T <kathirav@codeaurora.org> Link: https://lore.kernel.org/r/1606734105-12414-2-git-send-email-kathirav@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-30arm64: dts: sdm845: Add interconnect properties for QUPGeorgi Djakov
Add the interconnects DT property to describe the ports for GENI QUPs on the sdm845 platform. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Link: https://lore.kernel.org/r/20201105135211.7160-3-georgi.djakov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-30arm64: dts: qcom: c630: Expose LID eventsBjorn Andersson
The LID state can be read from GPIO 124 and the "tablet mode" from GPIO 95, expose these to the system using gpio-keys and mark the falling edge of the LID state as a wakeup-source - to wake the system from suspend. Tested-by: Steev Klimaszewski <steev@kali.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20201125060838.165576-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-30arm64: dts: qcom: c630: Re-enable apps_smmuBjorn Andersson
Re-enable the apps_smmu now that the arm-smmu driver supports stream mapping handoff from firmware. Tested-by: Steev Klimaszewski <steev@kali.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20201124184414.380796-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-30dts: qcom: sdm845: Add dt entries to support crypto engine.Thara Gopinath
Add crypto engine (CE) and CE BAM related nodes and definitions to "sdm845.dtsi". Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org> Link: https://lore.kernel.org/r/20201119155233.3974286-6-thara.gopinath@linaro.org [bjorn: Replaced RPMH_CE_CLK constant, for now] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-30arm64: dts: rockchip: add isp and sensors for ScarletEddie Cai
Enable ISP and camera sensor ov2685 and ov5695 for Scarlet Chromebook Verified with: make ARCH=arm64 dtbs_check Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com> Signed-off-by: Tomasz Figa <tfiga@chromium.org> Signed-off-by: Helen Koike <helen.koike@collabora.com> Reviewed-by: Tomasz Figa <tfiga@chromium.org> Link: https://lore.kernel.org/r/20201020193850.1460644-10-helen.koike@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-11-30arm64: dts: rockchip: add isp0 node for rk3399Shunqian Zheng
RK3399 has two ISPs, but only isp0 was tested. Add isp0 node in rk3399 dtsi Verified with: make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/media/rockchip-isp1.yaml Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Signed-off-by: Helen Koike <helen.koike@collabora.com> Link: https://lore.kernel.org/r/20201020193850.1460644-9-helen.koike@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-11-30KVM: arm64: Advertise ID_AA64PFR0_EL1.CSV3=1 if the CPUs are Meltdown-safeMarc Zyngier
Cores that predate the introduction of ID_AA64PFR0_EL1.CSV3 to the ARMv8 architecture have this field set to 0, even of some of them are not affected by the vulnerability. The kernel maintains a list of unaffected cores (A53, A55 and a few others) so that it doesn't impose an expensive mitigation uncessarily. As we do for CSV2, let's expose the CSV3 property to guests that run on HW that is effectively not vulnerable. This can be reset to zero by writing to the ID register from userspace, ensuring that VMs can be migrated despite the new property being set. Reported-by: Will Deacon <will@kernel.org> Signed-off-by: Marc Zyngier <maz@kernel.org>
2020-11-30arm64: dts: armada-3720-turris-mox: add 3W power capability to SFP cageMarek Behún
Add maximum-power-milliwatt = 3000 to SFP node of Turris MOX. Signed-off-by: Marek Behún <kabel@kernel.org> Fixes: 7109d817db2e ("arm64: dts: marvell: add DTS for Turris Mox") Cc: Gregory CLEMENT <gregory.clement@bootlin.com> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-11-30arm64: dts: marvell: keep SMMU disabled by default for Armada 7040 and 8040Tomasz Nowicki
FW has to configure devices' StreamIDs so that SMMU is able to lookup context and do proper translation later on. For Armada 7040 & 8040 and publicly available FW, most of the devices are configured properly, but some like ap_sdhci0, PCIe, NIC still remain unassigned which results in SMMU faults about unmatched StreamID (assuming ARM_SMMU_DISABLE_BYPASS_BY_DEFAUL=y). Since there is dependency on custom FW let SMMU be disabled by default. People who still willing to use SMMU need to enable manually and use ARM_SMMU_DISABLE_BYPASS_BY_DEFAUL=n (or via kernel command line) with extra caution. Fixes: 83a3545d9c37 ("arm64: dts: marvell: add SMMU support") Cc: <stable@vger.kernel.org> # 5.9+ Signed-off-by: Tomasz Nowicki <tn@semihalf.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-11-30arm64: dts: mcbin-singleshot: add heartbeat LEDTomasz Maciej Nowak
With board revision 1.3, SolidRun moved the power LED to the middle of the board. In old place of power LED a GPIO controllable heartbeat LED was added. This commit only touches Single Shot variant, since only this variant is all revision 1.3. Reported-by: Alexandra Alth <alexandra@alth.de> Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-11-30arm64: dts: marvell: cp11x: Harmonize xHCI DT nodes nameSerge Semin
In accordance with the Generic xHCI bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "generic-xhci"-compatible nodes are correctly named. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-11-30arm64: dts: freescale: update calibration table for TMU moduleYuantian Tang
Update the calibration table to make the temperature more accurate. Three platforms have been updated: ls1012a, ls1043a and ls1046a. Signed-off-by: Yuantian Tang <andy.tang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-11-30arm64: dts: freescale: sl28: combine SPI MTD partitionsMichael Walle
The upstream port, doesn't really follow the vendor partitioning. The bootloader partition has one U-Boot FIT image containing all needed bits and pieces. Even today the bootloader is already larger than the current "bootloader" partition. Thus, fold all the partitions into one and keep the environment one. The latter is still valid. We keep the failsafe partitions because the first half of the SPI flash is preinstalled by the vendor and immutable. Fixes: 815364d0424e ("arm64: dts: freescale: add Kontron sl28 support") Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-11-30arm64: dts: ls1028a: add optee nodeMichael Walle
Add the optee node which can either be enabled by a specific board or by the bootloader. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-11-30arm64: dts: ls1028a: fix FlexSPI clock inputMichael Walle
On the LS1028A the FlexSPI clock is connected to the first HWA output, see Figure 7 "Clock subsystem block diagram". Fixes: c77fae5ba09a ("arm64: dts: ls1028a: Add FlexSPI support") Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-11-30arm64: dts: ls1028a: fix ENETC PTP clock inputMichael Walle
On the LS1028A the ENETC reference clock is connected to 4th HWA output, see Figure 7 "Clock subsystem block diagram". The PHC may run with a wrong frequency. ptp_qoriq_auto_config() will read the clock speed of the clock given in the device tree. It is likely that, on the reference board this wasn't noticed because both clocks have the same frequency. But this must not be always the case. Fix it. Fixes: 49401003e260 ("arm64: dts: fsl: ls1028a: add ENETC 1588 timer node") Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-11-30arm64: dts: imx: Fix imx8mm-kontron-n801x-s.dtb targetNathan Chancellor
While running 'make dtbs_install', the following error occurs: make[3]: *** No rule to make target 'rootfs/freescale/imx8mm-kontron-n801x-s.dts', needed by '__dtbs_install'. It should be .dtb, not .dts. Fixes: 8668d8b2e67f ("arm64: dts: Add the Kontron i.MX8M Mini SoMs and baseboards") Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-11-30arm64: dts: imx8mn-evk: add IR supportJoakim Zhang
Add IR support on i.MX8MN EVK board. Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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