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2016-02-26Merge tag 'arm-soc/for-4.6/devicetree-arm64' of ↵Arnd Bergmann
http://github.com/Broadcom/stblinux into next/dt64 Merge "Broadcom devicetree-arm64 changes for 4.6" from Florian Fainelli: This pull request contains Broadcom ARM64-based SoCs device tree changes: - Anup adds additional nodes to the Broadcom Northstart 2 Device Trees: SDHCI (iProc-compatible), ARM SP804 timers, ARM SP805 watchdog - Anup also adds a binding documentation for the ARM SP805 watchdog since there was not one in tree before - Ray adds PCIE root complex nodes to the Northstar 2 Device Tree nodes, using the iProc-compatible binding - Jayachandran C. adds binding documentation for the Broadcom Vulcan processors and reference platforms * tag 'arm-soc/for-4.6/devicetree-arm64' of http://github.com/Broadcom/stblinux: dt-bindings: Add documentation for Broadcom Vulcan arm64: dts: Add PCIe0 and PCIe4 DT nodes for NS2 arm64: dts: Add ARM SP805 watchdog DT node for NS2 dt-bindings: watchdog: Add ARM SP805 DT bindings arm64: dts: Add ARM SP804 timer DT nodes for NS2 arm64: dts: Add SDHCI DT node for NS2
2016-02-26arm64: dts: alpine: add the MSIX node in the Alpine v2 dtsiAntoine Tenart
Following the addition of the Alpine MSIX controller driver, add the corresponding node in the Alpine v2 device tree. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Tsahee Zidenberg <tsahee@annapurnalabs.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-02-26arm64: dts: add the Alpine v2 EVPAntoine Tenart
This patch adds the initial support for the Alpine v2 EVP board from Annapurna Labs (Amazon). Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Barak Wasserstrom <barak@annapurnalabs.com> Signed-off-by: Tsahee Zidenberg <tsahee@annapurnalabs.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-02-26arm64: alpine: select the Alpine MSI controller driverAntoine Tenart
Select the Alpine MSI controller driver when using an Alpine platform. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Tsahee Zidenberg <tsahee@annapurnalabs.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-02-26arm64: defconfig: enable the Alpine familyAntoine Tenart
Enable the Alpine SoC family in the arm64 defconfig. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-02-26arm64: add Alpine SoC familyAntoine Tenart
This patch introduces ARCH_ALPINE to add the support of the Alpine SoC family for the arm64 architecture. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-02-26Merge tag 'zynqmp-dt-for-4.6' of https://github.com/Xilinx/linux-xlnx into ↵Arnd Bergmann
next/dt64 Merge "ARM: Xilinx ZynqMP dt patches for v4.6" from Michal Simek: - Extract clock information from EP108 - Sort GPIO node * tag 'zynqmp-dt-for-4.6' of https://github.com/Xilinx/linux-xlnx: ARM64: zynqmp: Extract clock information from EP108 ARM64: zynqmp: Keep gpio node alphabetically sorted
2016-02-26Merge tag 'v4.5-next-dts64' of https://github.com/mbgg/linux-mediatek into ↵Arnd Bergmann
next/dt64 Merge "ARM: mediatek: dts updates for v4.6" from Matthias Brugger: Add nor-flash to mt8173 SoC. Add efuse device to mt8173 SoC. Fix power-domain issue mt8173-evb which uses older chip revision. * tag 'v4.5-next-dts64' of https://github.com/mbgg/linux-mediatek: ARM64: dts: Mediatek: mt8173-evb: fix access MMC fail issue dts: arm64: Add EFUSE device node arm64: dts: mt8173: Add nor flash node
2016-02-26arm64: lse: deal with clobbered IP registers after branch via PLTArd Biesheuvel
The LSE atomics implementation uses runtime patching to patch in calls to out of line non-LSE atomics implementations on cores that lack hardware support for LSE. To avoid paying the overhead cost of a function call even if no call ends up being made, the bl instruction is kept invisible to the compiler, and the out of line implementations preserve all registers, not just the ones that they are required to preserve as per the AAPCS64. However, commit fd045f6cd98e ("arm64: add support for module PLTs") added support for routing branch instructions via veneers if the branch target offset exceeds the range of the ordinary relative branch instructions. Since this deals with jump and call instructions that are exposed to ELF relocations, the PLT code uses x16 to hold the address of the branch target when it performs an indirect branch-to-register, something which is explicitly allowed by the AAPCS64 (and ordinary compiler generated code does not expect register x16 or x17 to retain their values across a bl instruction). Since the lse runtime patched bl instructions don't adhere to the AAPCS64, they don't deal with this clobbering of registers x16 and x17. So add them to the clobber list of the asm() statements that perform the call instructions, and drop x16 and x17 from the list of registers that are callee saved in the out of line non-LSE implementations. In addition, since we have given these functions two scratch registers, they no longer need to stack/unstack temp registers. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> [will: factored clobber list into #define, updated Makefile comment] Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-26arm64: mm: dump: Use VA_START directly instead of private LOWEST_ADDRKefeng Wang
Use VA_START macro in asm/memory.h instead of private LOWEST_ADDR definition in dump.c. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-26arm64: kconfig: add submenu for 8.2 architectural featuresWill Deacon
UAO is a feature of ARMv8.2, so add a submenu like we have for 8.1. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-26arm64: vmemmap: use virtual projection of linear regionArd Biesheuvel
Commit dd006da21646 ("arm64: mm: increase VA range of identity map") made some changes to the memory mapping code to allow physical memory to reside at an offset that exceeds the size of the virtual mapping. However, since the size of the vmemmap area is proportional to the size of the VA area, but it is populated relative to the physical space, we may end up with the struct page array being mapped outside of the vmemmap region. For instance, on my Seattle A0 box, I can see the following output in the dmesg log. vmemmap : 0xffffffbdc0000000 - 0xffffffbfc0000000 ( 8 GB maximum) 0xffffffbfc0000000 - 0xffffffbfd0000000 ( 256 MB actual) We can fix this by deciding that the vmemmap region is not a projection of the physical space, but of the virtual space above PAGE_OFFSET, i.e., the linear region. This way, we are guaranteed that the vmemmap region is of sufficient size, and we can even reduce the size by half. Cc: <stable@vger.kernel.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-02-26arm64: kernel: acpi: fix ioremap in ACPI parking protocol cpu_postbootLorenzo Pieralisi
When secondary cpus are booted through the ACPI parking protocol, the booted cpu should check that FW has correctly cleared its mailbox entry point value to make sure the boot process was correctly executed. The entry point check is carried in the cpu_ops->cpu_postboot method, that is executed by secondary cpus when entering the kernel with irqs disabled. The ACPI parking protocol cpu_ops maps/unmaps the mailboxes on the primary CPU to trigger secondary boot in the cpu_ops->cpu_boot method and on secondary processors to carry out FW checks on the booted CPU to verify the boot protocol was successfully executed in the cpu_ops->cpu_postboot method. Therefore, the cpu_ops->cpu_postboot method is forced to ioremap/unmap the mailboxes, which is wrong in that ioremap cannot be safely be carried out with irqs disabled. To fix this issue, this patch reshuffles the code so that the mailboxes are still mapped after the boot processor executes the cpu_ops->cpu_boot method for a given cpu, and the VA at which a mailbox is mapped for a given cpu is stashed in the per-cpu data struct so that secondary cpus can retrieve them in the cpu_ops->cpu_postboot and complete the required FW checks. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reported-by: Itaru Kitayama <itaru.kitayama@riken.jp> Tested-by: Loc Ho <lho@apm.com> Tested-by: Itaru Kitayama <itaru.kitayama@riken.jp> Cc: Will Deacon <will.deacon@arm.com> Cc: Hanjun Guo <hanjun.guo@linaro.org> Cc: Loc Ho <lho@apm.com> Cc: Itaru Kitayama <itaru.kitayama@riken.jp> Cc: Sudeep Holla <sudeep.holla@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mark Salter <msalter@redhat.com> Cc: Al Stone <ahs3@redhat.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-26arm64: Add support for Half precision floating pointSuzuki K Poulose
ARMv8.2 extensions [1] include an optional feature, which supports half precision(16bit) floating point/asimd data processing instructions. This patch adds support for detecting and exposing the same to the userspace via HWCAPs [1] https://community.arm.com/groups/processors/blog/2016/01/05/armv8-a-architecture-evolution Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-26arm64: Remove fixmap include fragilityMark Rutland
The asm-generic fixmap.h depends on each architecture's fixmap.h to pull in the definition of PAGE_KERNEL_RO, if this exists. In the absence of this, FIXMAP_PAGE_RO will not be defined. In mm/early_ioremap.c the definition of early_memremap_ro is predicated on FIXMAP_PAGE_RO being defined. Currently, the arm64 fixmap.h doesn't include pgtable.h for the definition of PAGE_KERNEL_RO, and as a knock-on effect early_memremap_ro is not always defined, leading to link-time failures when it is used. This has been observed with defconfig on next-20160226. Unfortunately, as pgtable.h includes fixmap.h, adding the include introduces a circular dependency, which is just as fragile. Instead, this patch factors out PAGE_KERNEL_RO and other prot definitions into a new pgtable-prot header which can be included by poth pgtable.h and fixmap.h, avoiding the circular dependency, and ensuring that early_memremap_ro is alwyas defined where it is used. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reported-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-26arm64: Add workaround for Cavium erratum 27456Andrew Pinski
On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI instructions may cause the icache to become corrupted if it contains data for a non-current ASID. This patch implements the workaround (which invalidates the local icache when switching the mm) by using code patching. Signed-off-by: Andrew Pinski <apinski@cavium.com> Signed-off-by: David Daney <david.daney@cavium.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-26arm64: mm: Mark .rodata as ROJeremy Linton
Currently the .rodata section is actually still executable when DEBUG_RODATA is enabled. This changes that so the .rodata is actually read only, no execute. It also adds the .rodata section to the mem_init banner. Signed-off-by: Jeremy Linton <jeremy.linton@arm.com> Reviewed-by: Kees Cook <keescook@chromium.org> Acked-by: Mark Rutland <mark.rutland@arm.com> [catalin.marinas@arm.com: added vm_struct vmlinux_rodata in map_kernel()] Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-26arm64: dts: marvell: re-order Device Tree nodes for Armada AP806Thomas Petazzoni
The DT nodes representing the XOR engines were not placed at the proper location to comply with the requirement of ordering DT nodes by their unit address. This commit fixes this mistake. [gregory.clement@free-electrons.com: Fix commit title by adding ' dts:'] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-02-26arm64: dts: marvell: update Armada AP806 clock descriptionThomas Petazzoni
Following the review from the DT maintainers, the DT binding for the clocks has changed, and we now use a DFX server node exposing a syscon, with the clock nodes being subnodes of the DFX server node. This commit therefore updates the AP806 Device Tree file to use this new DT binding. [gregory.clement@free-electrons.com: Fix commit title by adding ' dts:'] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-02-26arm64: dts: marvell: add Device Tree files for Armada 7K/8KThomas Petazzoni
This commit adds the base Device Tree files for the Armada 7K and 8K SoCs, as well as the Armada 8040 DB board. The Armada 7020, 7040 (7K family) and 8020, 8040 (8K family) are composed of: - An AP806 block that contains the CPU core and a few basic peripherals. The AP806 is available in dual core configurations (used in 7020 and 8020) and quad core configurations (used in 8020 and 8040). - One or two CP110 blocks that contain all the high-speed interfaces (SATA, PCIe, Ethernet, etc.). The 7K family chips have one CP110, and the 8K family chips have two CP110, giving them twice the number of HW interfaces. In order to represent this from a Device Tree point of view, this commit creates the following hierarchy: * armada-ap806.dtsi - definitions common to dual/quad ap806 * armada-ap806-dual.dtsi - description of the two CPUs * armada-7020.dtsi - description of the 7020 SoC * armada-8020.dtsi - description of the 8020 SoC * armada-ap806-quad.dtsi - description of the four CPUs * armada-7040.dtsi - description of the 7040 SoC * armada-7040-db.dts - description of the 7040 board * armada-8040.dtsi - description of the 8040 SoC The CP110 blocks are not described yet, and will be part of future patch series. [gregory.clement@free-electrons.com: Fix commit title by adding ' dts:'] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-02-26arm64/mm: remove unnecessary boundary checkMiles Chen
Remove the unnecessary boundary check since there is a huge gap between user and kernel address that they would never overlap. (arm64 does not have enough levels of page tables to cover 64-bit virtual address) See Documentation/arm64/memory.txt Signed-off-by: Miles Chen <miles.chen@mediatek.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-25Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds
Pull KVM fixes from Paolo Bonzini: "KVM/ARM fixes: - Fix per-vcpu vgic bitmap allocation - Do not give copy random memory on MMIO read - Fix GICv3 APR register restore order KVM/x86 fixes: - Fix ubsan warning - Fix hardware breakpoints in a guest vs. preempt notifiers - Fix Hurd Generic: - use __GFP_NOWARN together with GFP_NOWAIT" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: KVM: x86: MMU: fix ubsan index-out-of-range warning arm64: KVM: vgic-v3: Restore ICH_APR0Rn_EL2 before ICH_APR1Rn_EL2 KVM: async_pf: do not warn on page allocation failures KVM: x86: fix conversion of addresses to linear in 32-bit protected mode KVM: x86: fix missed hardware breakpoints arm/arm64: KVM: Feed initialized memory to MMIO accesses KVM: arm/arm64: vgic: Ensure bitmaps are long enough
2016-02-25arm64: dts: apm: Add DT node for X-Gene v2 SLIMpro Mailbox I2C DriverDuc Dang
Add DT node to enable SLIMpro Mailbox I2C Driver for X-Gene v2 platforms. Signed-off-by: Duc Dang <dhdang@apm.com>
2016-02-25arm64: dts: apm: Mailbox device tree node for APM X-Gene v2 platform.Duc Dang
Add mailbox device tree node for APM X-Gene v2 platform. Signed-off-by: Duc Dang <dhdang@apm.com>
2016-02-25arm64: dts: apm: Add DT node for X-Gene v1 SLIMpro Mailbox I2C DriverDuc Dang
Add DT node to enable SLIMpro Mailbox I2C Driver for X-Gene v1 platforms. Signed-off-by: Duc Dang <dhdang@apm.com>
2016-02-25arm64: dts: apm: mailbox device tree node for APM X-Gene platform.Duc Dang
Mailbox device tree node for APM X-Gene platform. Signed-off-by: Feng Kan <fkan@apm.com> Signed-off-by: Duc Dang <dhdang@apm.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2016-02-25arm64: dts: apm: Update GPIO to control power-off on X-Gene v2 platformsDuc Dang
This patch updates gpio-keys node that supports power-off for X-Gene v2 Merlin board to adapt with new changes in xgene-gpio-sb driver (to support configuring some GPIO pins as interrupt pins). Signed-off-by: Quan Nguyen <qnguyen@apm.com> Signed-off-by: Duc Dang <dhdang@apm.com>
2016-02-25arm64: dts: apm: Update GPIO standby controller DT node for X-Gene v2 platformsDuc Dang
xgene-gpio-sb driver now supports configuring some GPIO pins as interrupt pins. This patch adds the required fields for GPIO standby controller DT node of X-Gene v2 platform to work with this new driver change. Signed-off-by: Quan Nguyen <qnguyen@apm.com> Signed-off-by: Duc Dang <dhdang@apm.com>
2016-02-25arm64: dts: apm: Update GPIO to control power-off on X-Gene v1 platformsDuc Dang
This patch updates gpio-keys node that supports power-off for X-Gene v1 Mustang board to adapt with new changes in xgene-gpio-sb driver (to support configuring some GPIO pins as interrupt pins). Signed-off-by: Duc Dang <dhdang@apm.com>
2016-02-26arm64: defconfig: Enable exynos thermal configAlim Akhtar
This patch enables Exynos thermal and related configs for the TMU found on Exynos7 SoC. This also enables thermal emulation mode to test trip points. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
2016-02-26arm64: dts: salvator-x: enable USB 2.0 Host of channel 1 and 2Yoshihiro Shimoda
We should set SW15 to pin 2-3 side on the board before we use CN9 as USB host or peripheral. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-26arm64: dts: salvator-x: enable usb2_phy of channel 1 and 2Yoshihiro Shimoda
This board has a MAX3355 chip. However, we cannot use the extcon/max3355 driver because the ID pin doesn't connect to a gpio pin (in other words, it connects to the SoC specific pin). And, the phy-rcar-gen3-usb2 driver cannot handle such a chip for now. So, this patch enables usb2_phy of channel 1 and 2. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-26arm64: dts: r8a7795: add USB2.0 Host (EHCI/OHCI) device nodesYoshihiro Shimoda
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-26arm64: dts: r8a7795: add usb2_phy device nodesYoshihiro Shimoda
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-26arm64: dts: r8a7795: use fallback etheravb compatibility stringSimon Horman
Use recently added fallback compatibility string in r8a7795 device tree. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-02-26arm64: dts: r8a7795: salvator-x: enable SDHI0 & 3Ai Kyuse
Add the exposed SD card slots. The on-board eMMC needs to wait until we fixed the 8bit support. Signed-off-by: Ai Kyuse <ai.kyuse.uw@renesas.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-26arm64: dts: r8a7795: Add SDHI support to dtsiAi Kyuse
Signed-off-by: Ai Kyuse <ai.kyuse.uw@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> [wsa: squashed some fixes and added mmc-caps] Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-25arm64: dts: qcom: fix usb digital voltage levelsSrinivas Kandagatla
This patch updates the digital voltage levels from corner values to microvolts as we are going to use s1 regulator directly for vddcx instead of s1_corner. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
2016-02-25arm64: dts: qcom: apq8016-sbc: enable lpass on DB410cSrinivas Kandagatla
This patch enables the lpass on DB410C. LPASS is used as cpu dai for both analog and digital audio. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
2016-02-25arm64: dts: qcom: add lpass nodeSrinivas Kandagatla
This patch adds lpass node to the SOC. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
2016-02-25arm64: dts: qcom: add audio pinctrlsSrinivas Kandagatla
This patch adds pinctrls required for digital and analog audio via lpass. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
2016-02-25arm64: dts: qcom: apq8016-sbc: add usb supportSrinivas Kandagatla
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
2016-02-25arm64: dts: qcom: add manual pullup setting to otg.Srinivas Kandagatla
This patch adds manual pull up setting for usb otg indicating that the vbus is vbus is not routed to USB controller/phy therefore enables pull-up explicitly before starting controller. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
2016-02-25arm64: dts: apm: Update X-Gene standby GPIO controller DTS entriesQuan Nguyen
Update APM X-Gene standby GPIO controller DTS entries to enable it as interrupt controller. [dhdang: update patch subject] Signed-off-by: Y Vo <yvo@apm.com> Signed-off-by: Quan Nguyen <qnguyen@apm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Duc Dang <dhdang@apm.com>
2016-02-25arm64: dts: apm: Update Merlin DT PCP PLL clock node for v2 hardwareLoc Ho
Update Merlin DT PCP PLL clock node to reflect compatible string change to reflect v2 hardware. [dhdang: change patch subject] Signed-off-by: Loc Ho <lho@apm.com> Signed-off-by: Duc Dang <dhdang@apm.com>
2016-02-25arm64: add defconfig options for Allwinner SoCsAndre Przywara
With the Allwinner platform now supported, enable it in the defconfig and add some options to give some decent out-of-the-box experience on those SoCs. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-25arm64: Fix building error with 16KB pages and 36-bit VACatalin Marinas
In such configuration, Linux uses only two pages of page tables and __pud_populate() should not be used. However, the BUILD_BUG() triggers since pud_sect() is still defined and the compiler cannot eliminate such code, even though at run-time it should not be triggered. This patch extends the #ifdef ARM64_64K_PAGES condition for pud_sect to include PGTABLE_LEVELS < 3. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-25dts: mt8173: Add iommu/smi nodes for mt8173Yong Wu
This patch add the iommu/larbs nodes for mt8173 Signed-off-by: Yong Wu <yong.wu@mediatek.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2016-02-25arm64: defconfig: Enable DesignWare APB GPIO controllerKefeng Wang
The Synopsys DesignWare APB GPIO controller is used by several vender's socs, like apm/marvell/altera/hisilicon, enable it by default. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-02-25arm64: dts: hip05: Append power button node for D02 boardKefeng Wang
This patch adds poweroff button device node to support poweroff feature on hip05 d02 board. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
generated by cgit (git 2.34.1) at 2025-10-03 13:13:18 +0000