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2025-08-11arm64: dts: qcom: qcs615: add a PCIe port for WLANYu Zhang(Yuriy)
Add an original PCIe port for WLAN. This port will be referenced and supplemented by specific WLAN devices. Signed-off-by: Yu Zhang (Yuriy) <yu.zhang@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250727-615-v7-1-2adb6233bbb9@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: qcs615-ride: Enable PCIe interfaceKrishna chaitanya chundru
Add platform configurations in devicetree for PCIe, board related gpios, PMIC regulators, etc. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250725112346.614316-3-ziyue.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: qcs615: enable pcieKrishna chaitanya chundru
Add configurations in devicetree for PCIe0, including registers, clocks, interrupts and phy setting sequence. Add PCIe lane equalization preset properties for 8 GT/s. Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250725112346.614316-2-ziyue.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: ipq5018: Add GE PHY to internal mdio busGeorge Moussalem
The IPQ5018 SoC contains an internal GE PHY, always at phy address 7. As such, let's add the GE PHY node to the SoC dtsi. The LDO controller found in the SoC must be enabled to provide constant low voltages to the PHY. The mdio-ipq4019 driver already has support for this, so adding the appropriate TCSR register offset. In addition, the GE PHY outputs both the RX and TX clocks to the GCC which gate controls them and routes them back to the PHY itself. So let's create two DT fixed clocks and register them in the GCC node. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://lore.kernel.org/r/20250630-ipq5018-ge-phy-v6-3-01be06378c15@outlook.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: ipq5018: Add MDIO busesGeorge Moussalem
IPQ5018 contains two mdio buses of which one bus is used to control the SoC's internal GE PHY, while the other bus is connected to external PHYs or switches. There's already support for IPQ5018 in the mdio-ipq4019 driver, so let's simply add the mdio nodes for them. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://lore.kernel.org/r/20250630-ipq5018-ge-phy-v6-2-01be06378c15@outlook.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: Update IPQ5424 xo_board to use fixed factor clockLuo Jie
xo_board is fixed to 24 MHZ, which is routed from WiFi output clock 48 MHZ (also being the reference clock of CMN PLL) divided 2 by analog block routing channel. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Luo Jie <quic_luoj@quicinc.com> Link: https://lore.kernel.org/r/20250610-qcom_ipq5424_cmnpll-v3-4-ceada8165645@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: ipq5424: Add CMN PLL nodeLuo Jie
Add CMN PLL node for enabling output clocks to the networking hardware blocks on IPQ5424 devices. The reference clock of CMN PLL is routed from XO to the CMN PLL through the internal WiFi block. .XO (48 MHZ or 96 MHZ or 192 MHZ)-->WiFi (multiplier/divider)--> 48 MHZ to CMN PLL. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Luo Jie <quic_luoj@quicinc.com> Link: https://lore.kernel.org/r/20250610-qcom_ipq5424_cmnpll-v3-3-ceada8165645@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: sm7225-fairphone-fp4: Enable USB audio offload supportLuca Weiss
Enable USB audio offloading which allows to play audio via a USB-C headset with lower power consumption and enabling some other features. This can be used like the following: $ amixer -c0 cset name='USB_RX Audio Mixer MultiMedia1' On $ aplay --device=plughw:0,0 test.wav Compared to regular playback to the USB sound card no xhci-hcd interrupts appear during playback, instead the ADSP will be handling the USB transfers. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250501-fp4-usb-audio-offload-v2-5-30f4596281cd@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: sm6350: Add q6usbdai nodeLuca Weiss
Add a node for q6usb which handles USB audio offloading, allowing to play audio via a USB-C headset with lower power consumption and enabling some other features. We also need to set num-hc-interrupters for the dwc3 for the q6usb to be able to use its sideband interrupter. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250501-fp4-usb-audio-offload-v2-4-30f4596281cd@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: qcs615: add missing dt property in QUP SEsViken Dadhaniya
Add the missing required-opps and operating-points-v2 properties to several I2C, SPI, and UART nodes in the QUP SEs. Fixes: f6746dc9e379 ("arm64: dts: qcom: qcs615: Add QUPv3 configuration") Cc: stable@vger.kernel.org Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250630064338.2487409-1-viken.dadhaniya@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: add Bluetooth supportJens Glathe
To enable Bluetooth pwrseq appears to be required for the WCN7850. Add the nodes from QCP, add the TODO hint for vreg_wcn_0p95 and vreg_wcn_1p9 Add uart14 for the BT interface. Tested-by: Anthony Ruhier <aruhier@mailbox.org> Signed-off-by: Jens Glathe <jens.glathe@oldschoolsolutions.biz> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250624-slim7x-bt-v3-1-7ada18058419@oldschoolsolutions.biz Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: x1p42100: Add GPU supportAkhil P Oommen
X1P42100 SoC has a new GPU called Adreno X1-45 which is a smaller version of Adreno X1-85 GPU. Describe this new GPU and also add the secure gpu firmware path that should used for X1P42100 CRD. Tested-by: Jens Glathe <jens.glathe@oldschoolsolutions.biz> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Tested-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com> # x1-26-100 Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250623-x1p-adreno-v4-4-d2575c839cbb@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: sm8250: Drop venus-enc/decoder nodeKonrad Dybcio
Commit 687bfbba5a1c ("media: venus: Add support for static video encoder/decoder declarations") invalidates these empty nodes. Get rid of them. Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250614-topic-encdec-v1-4-f974c3e9cb43@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: sdm845: Drop venus-enc/decoder nodeKonrad Dybcio
Commit 687bfbba5a1c ("media: venus: Add support for static video encoder/decoder declarations") invalidates these empty nodes. Get rid of them. Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250614-topic-encdec-v1-3-f974c3e9cb43@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: sc7180: Drop venus-enc/decoder nodeKonrad Dybcio
Commit 687bfbba5a1c ("media: venus: Add support for static video encoder/decoder declarations") invalidates these empty nodes. Get rid of them. Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250614-topic-encdec-v1-2-f974c3e9cb43@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: msm8916: Drop venus-enc/decoder nodeKonrad Dybcio
Commit 687bfbba5a1c ("media: venus: Add support for static video encoder/decoder declarations") invalidates these empty nodes. Get rid of them. Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250614-topic-encdec-v1-1-f974c3e9cb43@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: rename qcs615.dtsi to sm6150.dtsiDmitry Baryshkov
The established practice is to have the base DTSI file named after the base SoC name (see examples of qrb5165-rb5.dts vs sm8250.dtsi, qrb2210-rb1.dts vs qcm2290.dtsi, qrb4210-rb2.dts vs sm4250.dtsi vs sm6115.dtsi). Rename the SoC dtsi file accordingly and add "qcom,sm6150" as a fallback compat string. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250604-qcs615-sm6150-v1-2-2f01fd46c365@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: sa8775p: rename bus clock to follow the bindingsDmitry Baryshkov
DT bindings for the DPU SA8775P declare the first clock to be "nrt_bus", not just "bus". Fix the DT file accordingly. Fixes: 2f39d2d46c73 ("arm64: dts: qcom: sa8775p: add display dt nodes for MDSS0 and DPU") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250602-sa8775p-fix-dts-v1-1-f9f6271b33a3@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: sdm850-lenovo-yoga-c630: add routing for second USB connectorDmitry Baryshkov
On Lenovo Yoga C630 second (left) Type-C port is not connected to the SoC directly. Instead it has a USB hub, which also powers on the onboard USB camera. Describe these signal lines properly. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250608-c630-ports-v1-1-e4951db96efa@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: sar2130p: use defines for DSI PHY clocksDmitry Baryshkov
Use defined IDs to reference DSI PHY clocks instead of using raw numbers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250618-sar2130p-fix-mdss-v1-3-78c2fb9e9fba@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: sar2130p: correct VBIF region size for MDSSDmitry Baryshkov
Correct the VBIF region size for the display device on the SAR1230P platform. Fixes: 541d0b2f4dcd ("arm64: dts: qcom: sar2130p: add display nodes") Reported-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Closes: https://lore.kernel.org/all/c14dfd37-7d12-40c3-8281-fd0a7410813e@oss.qualcomm.com/ Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250618-sar2130p-fix-mdss-v1-2-78c2fb9e9fba@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: sar2130p: use TAG_ALWAYS for MDSS's mdp0-mem pathDmitry Baryshkov
Switch the main memory interconnect of the MDSS device to use QCOM_ICC_TAG_ALWAYS instead of _ACTIVE_ONLY. Fixes: 541d0b2f4dcd ("arm64: dts: qcom: sar2130p: add display nodes") Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250618-sar2130p-fix-mdss-v1-1-78c2fb9e9fba@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: sdm845: rename DisplayPort labelsDmitry Baryshkov
Rename DP labels to have mdss_ prefix, so that corresponding device nodes are grouped together. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250621-sdm845-dp-rename-v1-1-6f7f13443b43@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: ipq5018: Add tsens nodeSricharan Ramabadhran
IPQ5018 has tsens V1.0 IP with 5 sensors, though 4 are in use. There is no RPM, so tsens has to be manually enabled. Adding the tsens and nvmem nodes and adding 4 thermal sensors (zones). The critical trip temperature is set to 120'C with an action to reboot. In addition, adding a cooling device to the CPU thermal zone which uses CPU frequency scaling. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> [bjorn: Added tsens-v1 fallback compatible, per binding] Link: https://lore.kernel.org/r/20250612-ipq5018-tsens-v13-2-a210f3683240@outlook.com
2025-08-11arm64: dts: qcom: sm8650: Flatten the USB nodesNeil Armstrong
Transition the USB controllers found in the SM8650 SoC to the newly introduced, flattened representation of the Qualcomm USB block. The reg and interrupts properties from the usb child node are merged with their counterpart in the outer node, remaining properties and child nodes are simply moved. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250811-topic-sm8x50-usb-flatten-v2-2-0bbb3ac292e4@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: dts: qcom: sm8550: Flatten the USB nodesNeil Armstrong
Transition the USB controllers found in the SM8550 SoC to the newly introduced, flattened representation of the Qualcomm USB block. The reg and interrupts properties from the usb child node are merged with their counterpart in the outer node, remaining properties and child nodes are simply moved. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250811-topic-sm8x50-usb-flatten-v2-1-0bbb3ac292e4@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-11arm64: defconfig: Enable the RZ/V2H(P) RSPI driverFabrizio Castro
Enable the Renesas RZ/V2H(P) RSPI driver for the benefit of RZ/V2H(P) based platforms. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250624192304.338979-6-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-08-11arm64: defconfig: Enable Renesas RZ/T2H serial SCIThierry Bultel
Selects RZ/T2H (aka r9a09g077) SCI (serial) specific code, as used on the RZ/T2H and RZ/N2H EVKs. Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com> Link: https://lore.kernel.org/20250515141828.43444-11-thierry.bultel.yh@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-08-11arm64: dts: renesas: r9a09g057: Add RSPI nodesFabrizio Castro
Add nodes for the RSPI IPs found in the Renesas RZ/V2H(P) SoC. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250624192304.338979-7-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-08-11arm64: dts: renesas: Add initial support for the RZ/N2H EVKPaul Barker
Add an initial device tree file for the Renesas RZ/N2H Evaluation Board (EVK). Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250617171957.162145-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-08-11arm64: dts: renesas: Add DTSI for R9A09G087M44 variant of RZ/N2HPaul Barker
Add the device tree source include file for the R9A09G087M44 variant of the Renesas RZ/N2H SoC, which features a 4-core configuration. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250617171957.162145-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-08-11arm64: dts: renesas: Refactor RZ/T2H EVK device treePaul Barker
The RZ/T2H EVK and RZ/N2H EVK are very similar boards. As there is so much overlap between these parts, common device tree entries are moved to the new file rzt2h-n2h-evk-common.dtsi. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250617171957.162145-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-08-11arm64: dts: renesas: Add initial SoC DTSI for the RZ/N2H SoCLad Prabhakar
Add the initial SoC DTSI for the Renesas RZ/N2H ("R9A09G087") SoC, below is the list of blocks added: - EXT CLKs - 4x CA55 - SCIF - CPG - GIC - ARMv8 Timer Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250617171957.162145-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-08-11arm64: dts: renesas: Add initial support for the Renesas RZ/T2H eval boardThierry Bultel
Add the initial device tree for the RZ/T2H evaluation board. Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250617162810.154332-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-08-11arm64: dts: renesas: Add initial support for the Renesas RZ/T2H SoCThierry Bultel
Add the initial dtsi for the RZ/T2H SoC: - GIC - ARMv8-timer - CPG clock - SCI0 UART also add arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi, that keeps all 4 CPUs enabled, for consistency with later support of -m24 and -m04 SoC revisions, that only have 2 and 1 Cortex-A55, respectively, and that will use /delete-node/ to disable the missing CPUs. Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250617162810.154332-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-08-11arm64: dts: rockchip: convert rk3528 power-domains to dt-binding constantsHeiko Stuebner
Now that the binding head has been merged, convert the power-domain ids back to these constants for easier handling. Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250620201715.1572609-1-heiko@sntech.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-08-11arm64: dts: rockchip: enable NPU on ROCK 5BNicolas Frattaroli
The NPU on the ROCK5B uses the same regulator for both the sram-supply and the npu's supply. Add this regulator, and enable all the NPU bits. Also add the regulator as a domain-supply to the pd_npu power domain. v8: - Remove notion of top core (Robin Murphy) Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net> Link: https://lore.kernel.org/r/20250721-6-10-rocket-v9-10-77ebd484941e@tomeuvizoso.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-08-11arm64: dts: rockchip: Enable the NPU on quartzpro64Tomeu Vizoso
Enable the nodes added in a previous commit to the rk3588s device tree. v2: - Split nodes (Sebastian Reichel) - Sort nodes (Sebastian Reichel) - Add board regulators (Sebastian Reichel) v8: - Remove notion of top core (Robin Murphy) Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net> Link: https://lore.kernel.org/r/20250721-6-10-rocket-v9-9-77ebd484941e@tomeuvizoso.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-08-11arm64: dts: rockchip: Add nodes for NPU and its MMU to rk3588-baseTomeu Vizoso
See Chapter 36 "RKNN" from the RK3588 TRM (Part 1). The IP is divided in three cores, programmed independently. The first core though is special, being able to delegate work to the other cores. The IOMMU of the first core is also special in that it has two subunits (read/write?) that need to be programmed in sync. v2: - Have one device for each NPU core (Sebastian Reichel) - Have one device for each IOMMU (Sebastian Reichel) - Correctly sort nodes (Diederik de Haas) - Add rockchip,iommu compatible to IOMMU nodes (Sebastian Reichel) v3: - Adapt to a split of the register block in the DT bindings (Nicolas Frattaroli) v4: - Adapt to changes in bindings v6: - pclk and npu clocks are needed by all clocks (Rob Herring) v8: - Remove notion of top core (Robin Murphy) Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net> Link: https://lore.kernel.org/r/20250721-6-10-rocket-v9-8-77ebd484941e@tomeuvizoso.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-08-11arm64: dts: rockchip: add pd_npu label for RK3588 power domainsNicolas Frattaroli
The NPU of the RK3588 has an external supply. This supply also affects the power domain of the NPU, not just the NPU device nodes themselves. Since correctly modelled boards will want the power domain to be aware of the regulator so that it doesn't always have to be on, add a label to the NPU power domain node so board files can reference it. Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net> Link: https://lore.kernel.org/r/20250721-6-10-rocket-v9-7-77ebd484941e@tomeuvizoso.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-08-11arm64: dts: rockchip: Add vcc-supply to SPI flash on rk3399-pinebook-proPeter Robinson
As described in the pinebookpro_v2.1_mainboard_schematic.pdf page 10, he SPI Flash's VCC connector is connected to VCC_3V0 power source. This fixes the following warning: spi-nor spi1.0: supply vcc not found, using dummy regulator Fixes: 5a65505a69884 ("arm64: dts: rockchip: Add initial support for Pinebook Pro") Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/20250730102129.224468-1-pbrobinson@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-08-11arm64: dts: rockchip: Add thermal trim OTP and tsadc nodesNicolas Frattaroli
Thanks to Heiko's work getting OTP working on the RK3576, we can specify the thermal sensor trim values which are stored there now, and with my driver addition to rockchip_thermal, we can make use of these. Add them to the devicetree for the SoC. Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20250610-rk3576-tsadc-upstream-v6-7-b6e9efbf1015@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-08-11arm64: dts: rockchip: Add thermal nodes to RK3576Nicolas Frattaroli
Add the TSADC node to the RK3576. Additionally, add everything the TSADC needs to function, i.e. thermal zones, their trip points and maps, as well as adjust the CPU cooling-cells property. The polling-delay properties are set to 0 as we do have interrupts for this TSADC on this particular SoC, though the polling-delay-passive properties are set to 100 for the thermal zones that have a passive cooling device, as otherwise the thermal throttling behaviour never unthrottles. Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20250610-rk3576-tsadc-upstream-v6-6-b6e9efbf1015@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-08-11arm64: dts: rockchip: Enable eMMC on rk3576-evb1-v10Chaoyi Chen
Some rk3576-evb1 boards use eMMC instead of UFS. Enable eMMC for it. Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> Link: https://lore.kernel.org/r/20250731062415.212-1-kernel@airkyi.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-08-11arm64: dts: rockchip: mark eeprom as read-only for Radxa E52CChukun Pan
The eeprom on the Radxa E52C SBC contains manufacturer data such as the mac address, so it should be marked as read-only. Fixes: 9be4171219b6 ("arm64: dts: rockchip: Add Radxa E52C") Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Link: https://lore.kernel.org/r/20250810100020.445053-2-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-08-11arm64: dts: rockchip: set LAN LEDs to default-off on Radxa E52CChukun Pan
The NICs have default-trigger of "netdev" in order to show up as LAN/WAN connected, so their default-state should be set to "off". Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Link: https://lore.kernel.org/r/20250810100020.445053-3-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-08-11arm64: dts: rockchip: Enable HDMI audio output for NanoPi R6C/R6SAnton Kirilov
Enable HDMI audio output for FriendlyElec NanoPi R6C/R6S boards. Signed-off-by: Anton Kirilov <anton.kirilov@arm.com> Link: https://lore.kernel.org/r/20250807170012.88178-1-anton.kirilov@arm.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-08-10arm64: dts: qcom: Add lemans evaluation kit (EVK) initial board supportWasim Nazir
Lemans EVK is an IoT board without safety monitoring feature of Safety Island(SAIL) subsystem. Lemans EVK is single board supporting these peripherals: - Storage: 2 × 128 GB UFS, micro-SD card, EEPROMs for MACs, eMMC on mezzanine card - Audio/Video, Camera & Display ports - Connectivity: RJ45 2.5GbE, WLAN/Bluetooth, CAN/CAN-FD - Sensors: IMU - PCIe ports - USB & UART ports On top of lemans EVK board additional mezzanine boards can be stacked in future. Implement basic features like uart/ufs to enable 'boot to shell'. Co-developed-by: Rakesh Kota <quic_kotarake@quicinc.com> Signed-off-by: Rakesh Kota <quic_kotarake@quicinc.com> Co-developed-by: Sayali Lokhande <quic_sayalil@quicinc.com> Signed-off-by: Sayali Lokhande <quic_sayalil@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Wasim Nazir <wasim.nazir@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250803110113.401927-9-wasim.nazir@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-10arm64: dts: qcom: lemans: Fix dts inclusion for IoT boards and update memory mapWasim Nazir
IoT boards currently inherit the automotive memory map, which is not suitable for their configuration. This leads to incorrect memory layout and inclusion of unnecessary carveouts. Use lemans.dtsi as the base for IoT boards to apply the correct memory map. Include additional DTSI files as needed to complete the board configuration. Update 'model' string to represent these boards as 'lemans'. Signed-off-by: Wasim Nazir <wasim.nazir@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250803110113.401927-7-wasim.nazir@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-08-10arm64: dts: qcom: lemans: Rename sa8775p-pmics.dtsi to lemans-pmics.dtsiWasim Nazir
The existing PMIC DTSI file is named sa8775p-pmics.dtsi, which does not align with the updated naming convention for Lemans platform components. This inconsistency can lead to confusion and misalignment with other platform-specific files. Rename the file to lemans-pmics.dtsi to reflect the platform naming convention and improve clarity. Signed-off-by: Wasim Nazir <wasim.nazir@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250803110113.401927-6-wasim.nazir@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
generated by cgit (git 2.34.1) at 2025-10-02 23:47:06 +0000