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2011-12-08powerpc/kdump: Delay before sending IPI on a system resetAnton Blanchard
If we enter the kdump code via system reset, wait a bit before sending the IPI to capture all secondary CPUs. Without it we race with the hypervisor that is issuing the system reset to each CPU. If the IPI gets there first the system reset oops output then shows the register state of the IPI handler which is not what we want. I took the opportunity to add defines for all the various delays we have. There's no need for cpu_relax when we are doing an mdelay, so remove them too. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-12-08powerpc/xics: Reset the CPPR if H_EOI failsAnton Blanchard
I have an intermittent kdump fail where the hypervisor fails an H_EOI. As a result our CPPR is never reset to 0xff and we no longer accept interrupts. This patch calls icp_hv_set_cppr to reset the CPPR if H_EOI fails, fixing the kdump fail. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-12-08powerpc: Reduce pseries panic timeout from 180s to 10sAnton Blanchard
We've had a 180 second panic timeout on ppc64 for as long as I can remember. This patch reduces it to 10 seconds on pseries for a few reasons: - Almost all pseries machines have a hypervisor console so panic output will be available in a scrollback buffer. - The 180 seconds impacts our availability, users (other than kernel hackers) just want the box to come back around so it can continue its work. - I spend a lot of my life staring at the 180 second panic timeout. Many pseries machines take minutes to power cycle, so it's quicker to sit through the 180 seconds than it is to power cycle. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-12-08powerpc: Rework die()Anton Blanchard
Our die() code was based off a very old x86 version. Update it to mirror the current x86 code. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-12-08powerpc: Cleanup crash/kexec codeAnton Blanchard
Remove some unnecessary defines and fix some spelling mistakes. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-12-08powerpc/kdump: Use setjmp/longjmp to handle kdump and system reset recursionAnton Blanchard
We can handle recursion caused by system reset by reusing the crash shutdown fault handler. Since we don't have an OS triggerable NMI, if all CPUs don't make it into kdump then we tell the user to issue a system reset. However if we have a panic timeout set we cannot wait forever and must continue the kdump. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-12-08powerpc: Remove broken and complicated kdump system reset codeAnton Blanchard
We have a lot of complicated logic that handles possible recursion between kdump and a system reset exception. We can solve this in a much simpler way using the same setjmp/longjmp tricks xmon does. As a first step, this patch removes the old system reset code. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-12-08powerpc: Give us time to get all oopses out before panickingAnton Blanchard
I've been seeing truncated output when people send system reset info to me. We should see a backtrace for every CPU, but the panic() code takes the box down before they all make it out to the console. The panic code runs unlocked so we also see corrupted console output. If we are going to panic, then delay 1 second before calling into the panic code. Move oops_exit inside the die lock and put a newline between oopses for clarity. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-12-08powerpc/cpuidle: Handle power_save=offDeepthi Dharwar
This patch makes pseries_idle_driver not to be registered when power_save=off kernel boot option is specified. The cpuidle_disable variable used here is similar to its usage on x86. If cpuidle_disable is set then sysfs entries for cpuidle framework are not created and the required drivers are not loaded. Signed-off-by: Deepthi Dharwar <deepthi@linux.vnet.ibm.com> Signed-off-by: Trinabh Gupta <g.trinabh@gmail.com> Signed-off-by: Arun R Bharadwaj <arun.r.bharadwaj@gmail.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-12-08powerpc/cpuidle: Enable cpuidle and directly call cpuidle_idle_call() for ↵Deepthi Dharwar
pSeries This patch enables cpuidle for pSeries and pSeries_idle is directly called from the idle loop. As a result of pSeries_idle, cpuidle driver registered with cpuidle subsystem comes into action. On failure of loading of the driver or cpuidle framework default idle is executed as part of the function. This patch also removes the routines pseries_shared_idle_sleep and pseries_dedicated_idle_sleep as they are now implemented as part of pseries_idle cpuidle driver. Signed-off-by: Deepthi Dharwar <deepthi@linux.vnet.ibm.com> Signed-off-by: Trinabh Gupta <g.trinabh@gmail.com> Signed-off-by: Arun R Bharadwaj <arun.r.bharadwaj@gmail.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-12-08powerpc/cpuidle: cpuidle driver for pSeriesDeepthi Dharwar
This patch implements a back-end cpuidle driver for pSeries based on pseries_dedicated_idle_loop and pseries_shared_idle_loop routines. The driver is built only if CONFIG_CPU_IDLE is set. This cpuidle driver uses global registration of idle states and not per-cpu. Signed-off-by: Deepthi Dharwar <deepthi@linux.vnet.ibm.com> Signed-off-by: Trinabh Gupta <g.trinabh@gmail.com> Signed-off-by: Arun R Bharadwaj <arun.r.bharadwaj@gmail.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-12-08powerpc/cpuidle: Add cpu_idle_wait() to allow switching of idle routinesDeepthi Dharwar
This patch provides cpu_idle_wait() routine for the powerpc platform which is required by the cpuidle subsystem. This routine is required to change the idle handler on SMP systems. The equivalent routine for x86 is in arch/x86/kernel/process.c but the powerpc implementation is different. cpuidle_disable variable is to enable/disable cpuidle framework if power_save option is set during the boot time. Signed-off-by: Deepthi Dharwar <deepthi@linux.vnet.ibm.com> Signed-off-by: Trinabh Gupta <g.trinabh@gmail.com> Signed-off-by: Arun R Bharadwaj <arun.r.bharadwaj@gmail.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-12-08Merge branch 'booke-hugetlb' into nextBenjamin Herrenschmidt
2011-12-08ARM: S3C64XX: Hook up VDDINT on CragganmoreMark Brown
Basic hookup, we do have a GPIO to use to control the voltage but we don't currently use it. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2011-12-08ARM: EXYNOS: Fix build error without CONFIG_LOCAL_TIMERSKukjin Kim
arch/arm/mach-exynos/mct.c: In function 'exynos4_timer_resources': arch/arm/mach-exynos/mct.c:450: error: 'exynos4_mct_tick_isr' undeclared (first use in this function) arch/arm/mach-exynos/mct.c:450: error: (Each undeclared identifier is reported only once arch/arm/mach-exynos/mct.c:450: error: for each function it appears in.) make[1]: *** [arch/arm/mach-exynos/mct.o] Error 1 Reported-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Changhwan Youn <chaos.youn@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Cc: Marc Zyngier <marc.zyngier@arm.com>
2011-12-08ARM: EXYNOS: Fix for stall in case of cpu hotplug or sleepAmit Daniel Kachhap
This patch adds remove_irq in place of disable_irq which is correct equivalent function for setup_irq used in exynos4_mct_tick_init. Signed-off-by: Amit Daniel Kachhap <amit.kachhap@linaro.org> Tested-by: Inderpal Singh <inderpal.singh@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2011-12-08ARM: S5PV210: Set 1000ns as PWM backlight period on SMDKV210Jingoo Han
The SMDK board uses LT3591 as backlight LED driver of LTE480WV LCD. According to the LT3591 datasheet, the switching frequency should be 1MHz. So, PWM period is calculated by following formula: PWM period = 1/switching frequency = 1/1MHz = 1000ns Thus, the PWM backlight period should be 1000ns. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2011-12-08ARM: SAMSUNG: remove duplicated header includeJingoo Han
This patch removes duplicated slab header for pwm backlight. arch/arm/plat-samsung/dev-backlight.c: slab.h is included more than once. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2011-12-08ARM: SAMSUNG: Use kmemdup rather than duplicating its implementationThomas Meyer
The semantic patch that makes this change is available in scripts/coccinelle/api/memdup.cocci. Signed-off-by: Thomas Meyer <thomas@m3y3r.de> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2011-12-07Merge branch 'for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/geert/linux-m68k * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/linux-m68k: m68k: Wire up process_vm_{read,write}v
2011-12-07x86, NMI: Add to_cpumask() to silence compile warningDan Carpenter
Gcc complains if we don't cast this to a struct cpumask pointer. arch/x86/kernel/nmi_selftest.c:93:2: warning: passing argument 1 of ‘cpumask_empty’ from incompatible pointer type [enabled by default] Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Cc: Don Zickus <dzickus@redhat.com> Link: http://lkml.kernel.org/r/20111207110612.GA3437@mwanda Signed-off-by: Ingo Molnar <mingo@elte.hu>
2011-12-07x86, NMI: NMI selftest depends on the local apicDon Zickus
The selftest doesn't work with out a local apic for now. Reported-by: Randy Durlap <rdunlap@xenotime.net> Signed-off-by: Don Zickus <dzickus@redhat.com> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Link: http://lkml.kernel.org/r/20111207210630.GI1669@redhat.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
2011-12-07MIPS: Netlogic: Mark Netlogic chips as SMT capableHillf Danton
Netlogic XLR chip has multiple cores. Each core includes four integrated hardware threads, and they share L1 data and instruction caches. If the chip is marked to be SMT capable, scheduler then could do more, say, idle load balancing. Changes are now confined only to the code of XLR, and hardware is probed to get core ID for correct setup. [jayachandranc: simplified and adapted for new merged XLR/XLP code] Signed-off-by: Hillf Danton <dhillf@gmail.com> Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2972/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-07MIPS: Netlogic: Add support for XLP 3XX coresJayachandran C
Add new processor ID to asm/cpu.h and kernel/cpu-probe.c. Update to new CPU frequency detection code which works on XLP 3XX and 8XX. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2971/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-07MIPS: Netlogic: Merge some of XLR/XLP wakup codeJayachandran C
Create a common NMI and reset handler in smpboot.S and use this for both XLR and XLP. In the earlier code, the woken up CPUs would busy wait until released, switch this to wakeup by NMI. The initial wakeup code or XLR and XLP are differ since they are started from different bootloaders (XLP from u-boot and XLR from netlogic bootloader). But in both platforms the woken up CPUs wait and are released by sending an NMI. Add support for starting XLR and XLP in 1/2/4 threads per core. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2970/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-07MIPS: Netlogic: Add default XLP config.Jayachandran C
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2969/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-07MIPS: Netlogic: Add XLP makefiles and configJayachandran C
- Add CPU_XLP and NLM_XLR_BOARD to arch/mips/Kconfig for Netlogic XLP boards - Update mips Makefiles to add XLP Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2968/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-07MIPS: Netlogic: Add XLP platform files for XLP SoCJayachandran C
- Update common files to support XLP. - Add arch/mips/include/asm/netlogic/xlp-hal for register definitions and access macros - Add arch/mips/netlogic/xlp/ for XLP specific files. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2967/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-07MIPS: Netlogic: XLP CPU support.Jayachandran C
Add support for Netlogic's XLP MIPS SoC. This patch adds: * XLP processor ID in cpu_probe.c and asm/cpu.h * XLP case to asm/module.h * CPU_XLP case to mm/tlbex.c * minor change to r4k cache handling to ignore XLP secondary cache * XLP cpu overrides to mach-netlogic/cpu-feature-overrides.h Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2966/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-07MIPS: Netlogic: Update default configJayachandran C
- Enable PCI and MSI by default - Update cross compile tool-chain and rootfs Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2965/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-07MIPS: Netlogic: Move code common with XLP to common/Jayachandran C
- Move code that can be shared with XLP (irq.c, smp.c, time.c and xlr_console.c) to arch/mips/netlogic/common - Add asm/netlogic/haldefs.h and asm/netlogic/common.h for common and io functions shared with XLP - remove type 'nlm_reg_t *' and use uint64_t for mmio offsets - Move XLR specific code in smp.c to xlr/wakeup.c - Move XLR specific PCI code from irq.c to mips/pci/pci-xlr.c - Provide API for pic functions called from common/irq.c Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2964/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-07MIPS: Netlogic: No need to set -Werror in mips/xlrJayachandran C
The -Werror compilation flag is already set for arch/mips - it can be removed from arch/mips/xlr/Makefile Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2963/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-07MIPS: Netlogic: Use CPU_XLR instead of NLM_XLRJayachandran C
The CPU_XLR config variable is sufficient for XLR compilation, the variable NLM_XLR can be removed. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2962/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-07MIPS: Netlogic: Style fixes for PlatformJayachandran C
- Use platform- variable for xlr - Load address common for all netlogic chips Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2961/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-07MIPS: Netlogic: Add basic MSI support for XLR/XLSGanesan Ramalingam
Add basic support for MSI. Signed-off-by: Ganesan Ramalingam <ganesanr@netlogicmicro.com> Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2730/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-07MIPS: Netlogic: Avoid unnecessary cache flushesJayachandran C
XLR dcache is fully coherent across CPUs, so avoid unnecessary dcache flushes. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2729/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-07MIPS: Netlogic: add r4k_wait as the cpu_waitJayachandran C
Use r4k_wait as the CPU wait function for XLR/XLS processors. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2728/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-07MIPS: Netlogic: Change load addressJayachandran C
Move load address from 0x84000000 to 0x80100000 to avoid wasting memory. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2727/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-07MIPS/Perf-events: Cleanup event->destroy at event initDeng-Cheng Zhu
Simplify the code by changing the place of event->destroy(). Signed-off-by: Deng-Cheng Zhu <dczhu@mips.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Ingo Molnar <mingo@elte.hu> Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net> Cc: David Daney <david.daney@cavium.com> Cc: Eyal Barzilay <eyal@mips.com> Cc: Zenon Fortuna <zenon@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/3109/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-07MIPS/Perf-events: Remove pmu and event state checking in validate_event()Deng-Cheng Zhu
Why removing pmu checking: Since 3.2-rc1, when arch level event init is called, the event is already connected to its PMU. Also, validate_event() is _only_ called by validate_group() in event init, so there is no need of checking or temporarily assigning event pmu during validate_group(). Why removing event state checking: Events could be created in PERF_EVENT_STATE_OFF (attr->disabled == 1), when these events go through this checking, validate_group() does dummy work. But we do need to do group scheduling emulation for them in event init. Again, validate_event() is _only_ called by validate_group(). Reference: http://www.spinics.net/lists/mips/msg42190.html Signed-off-by: Deng-Cheng Zhu <dczhu@mips.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Ingo Molnar <mingo@elte.hu> Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net> Cc: David Daney <david.daney@cavium.com> Cc: Eyal Barzilay <eyal@mips.com> Cc: Zenon Fortuna <zenon@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/3108/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-07MIPS/Perf-events: Remove erroneous check on active_eventsDeng-Cheng Zhu
Port the following patch for ARM by Mark Rutland: - 57ce9bb39b476accf8fba6e16aea67ed76ea523d ARM: 6902/1: perf: Remove erroneous check on active_events When initialising a PMU, there is a check to protect against races with other CPUs filling all of the available event slots. Since armpmu_add checks that an event can be scheduled, we do not need to do this at initialisation time. Furthermore the current code is broken because it assumes that atomic_inc_not_zero will unconditionally increment active_counts and then tries to decrement it again on failure. This patch removes the broken, redundant code. Signed-off-by: Deng-Cheng Zhu <dczhu@mips.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Ingo Molnar <mingo@elte.hu> Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net> Cc: David Daney <david.daney@cavium.com> Cc: Eyal Barzilay <eyal@mips.com> Cc: Zenon Fortuna <zenon@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/3106/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-07MIPS/Perf-events: Don't do validation on raw eventsDeng-Cheng Zhu
MIPS licensees may want to modify performance counters to count extra events. Also, now that the user is working on raw events, the manual is being used for sure. And feeding unsupported events shouldn't cause hardware failure and the like. [ralf@linux-mips.org: performance events also being used in internal performance evaluation and have a tendency to change as the micro- architecture evolves, even for minor revisions that may not be distinguishable by PrID. It's not very practicable to maintain a list of all events and there is no real benefit.] Signed-off-by: Deng-Cheng Zhu <dczhu@mips.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Ingo Molnar <mingo@elte.hu> Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net> Cc: David Daney <david.daney@cavium.com> Cc: Eyal Barzilay <eyal@mips.com> Cc: Zenon Fortuna <zenon@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/3107/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-07MIPS Kprobes: Support branch instructions probingManeesh Soni
This patch provides support for kprobes on branch instructions. The branch instruction at the probed address is actually emulated and not executed out-of-line like other normal instructions. Instead the delay-slot instruction is copied and single stepped out of line. At the time of probe hit, the original branch instruction is evaluated and the target cp0_epc is computed similar to compute_retrun_epc(). It is also checked if the delay slot instruction can be skipped, which is true if there is a NOP in delay slot or branch is taken in case of branch likely instructions. Once the delay slot instruction is single stepped the normal execution resume with the cp0_epc updated the earlier computed cp0_epc as per the branch instructions. Signed-off-by: Maneesh Soni <manesoni@cisco.com> Signed-off-by: Victor Kamensky <kamensky@cisco.com> Cc: David Daney <david.daney@cavium.com> Cc: ananth@in.ibm.com Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2914/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-07MIPS Kprobes: Refactor branch emulationManeesh Soni
This patch refactors MIPS branch emulation code so as to allow skipping delay slot instruction in case of branch likely instructions when branch is not taken. This is useful for keeping the code common for use cases like kprobes where one would like to handle the branch instructions keeping the delay slot instuction also in picture for branch likely instructions. Also allow emulation when instruction to be decoded is not at pt_regs->cp0_epc as in case of kprobes where pt_regs->cp0_epc points to the breakpoint instruction. The patch also exports the function for modules. Signed-off-by: Maneesh Soni <manesoni@cisco.com> Signed-off-by: Victor Kamensky <kamensky@cisco.com> Cc: David Daney <david.daney@cavium.com> Cc: ananth@in.ibm.com Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2913/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-07MIPS Kprobes: Deny probes on ll/sc instructionsManeesh Soni
As ll/sc instruction are for atomic read-modify-write operations, allowing probes on top of these insturctions is a bad idea. Signed-off-by: Victor Kamensky <kamensky@cisco.com> Signed-off-by: Maneesh Soni <manesoni@cisco.com> Cc: David Daney <david.daney@cavium.com> Cc: ananth@in.ibm.com Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2912/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-07MIPS Kprobes: Fix OOPS in arch_prepare_kprobe()Maneesh Soni
This patch fixes the arch_prepare_kprobe() on MIPS when it tries to find the instruction at the previous address to the probed address. The oops happens when the probed address is the first address in a kernel module and there is no previous address. The patch uses probe_kernel_read() to safely read the previous instruction. CPU 3 Unable to handle kernel paging request at virtual address ffffffffc0211ffc, epc == ffffffff81113204, ra == ffffffff8111511c Oops[#1]: Cpu 3 $ 0 : 0000000000000000 0000000000000001 ffffffffc0212000 0000000000000000 $ 4 : ffffffffc0220030 0000000000000000 0000000000000adf ffffffff81a3f898 $ 8 : ffffffffc0220030 ffffffffffffffff 000000000000ffff 0000000000004821 $12 : 000000000000000a ffffffff81105ddc ffffffff812927d0 0000000000000000 $16 : ffffffff81a40000 ffffffffc0220030 ffffffffc0220030 ffffffffc0212660 $20 : 0000000000000000 0000000000000008 efffffffffffffff ffffffffc0220000 $24 : 0000000000000002 ffffffff8139f5b0 $28 : a800000072adc000 a800000072adfca0 ffffffffc0220000 ffffffff8111511c Hi : 0000000000000000 Lo : 0000000000000000 epc : ffffffff81113204 arch_prepare_kprobe+0x1c/0xe8 Tainted: P ra : ffffffff8111511c register_kprobe+0x33c/0x730 Status: 10008ce3 KX SX UX KERNEL EXL IE Cause : 00800008 BadVA : ffffffffc0211ffc PrId : 000d9008 (Cavium Octeon II) Modules linked in: bpa_mem crashinfo pds tun cpumem ipv6 exportfs nfsd OOBnd(P) OOBhal(P) cvmx_mdio cvmx_gpio aipcmod(P) mtsmod procfs(P) utaker_mod dplr_pci hello atomicm_foo [last unloaded: sysmgr_hb] Process stapio (pid: 5603, threadinfo=a800000072adc000, task=a8000000722e0438, tls=000000002b4bcda0) Stack : ffffffff81a40000 ffffffff81a40000 ffffffffc0220030 ffffffff8111511c ffffffffc0218008 0000000000000001 ffffffffc0218008 0000000000000001 ffffffffc0220000 ffffffffc021efe8 1000000000000000 0000000000000008 efffffffffffffff ffffffffc0220000 ffffffffc0220000 ffffffffc021d500 0000000000000022 0000000000000002 1111000072be02b8 0000000000000000 00000000000015e6 00000000000015e6 00000000007d0f00 a800000072be02b8 0000000000000000 ffffffff811d16c8 a80000000382e3b0 ffffffff811d5ba0 ffffffff81b0a270 ffffffff81b0a270 ffffffffc0212000 0000000000000013 ffffffffc0220030 ffffffffc021ed00 a800000089114c80 000000007f90d590 a800000072adfe38 a800000089114c80 0000000010020000 0000000010020000 ... Call Trace: [<ffffffff81113204>] arch_prepare_kprobe+0x1c/0xe8 [<ffffffff8111511c>] register_kprobe+0x33c/0x730 [<ffffffffc021d500>] _stp_ctl_write_cmd+0x8e8/0xa88 [atomicm_foo] [<ffffffff812925cc>] vfs_write+0xb4/0x178 [<ffffffff81292828>] SyS_write+0x58/0x148 [<ffffffff81103844>] handle_sysn32+0x44/0x84 Code: ffb20010 ffb00000 dc820028 <8c44fffc> 8c500000 0c4449e0 0004203c 14400029 3c048199 Signed-off-by: Maneesh Soni <manesoni@cisco.com> Signed-off-by: Victor Kamensky <kamensky@cisco.com> Cc: David Daney <david.daney@cavium.com> Cc: ananth@in.ibm.com Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2915/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-07MIPS: irq: Remove IRQF_DISABLEDYong Zhang
Since commit [e58aa3d2: genirq: Run irq handlers with interrupts disabled], We run all interrupt handlers with interrupts disabled and we even check and yell when an interrupt handler returns with interrupts enabled (see commit [b738a50a: genirq: Warn when handler enables interrupts]). So now this flag is a NOOP and can be removed. [ralf@linux-mips.org: Fixed up conflicts in arch/mips/alchemy/common/dbdma.c, arch/mips/cavium-octeon/smp.c and arch/mips/kernel/perf_event.c.] Signed-off-by: Yong Zhang <yong.zhang0@gmail.com> To: linux-kernel@vger.kernel.org Cc: tglx@linutronix.de linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2835/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-07MIPS: Handle initmem in systems with kernel not in add_memory_region() memDavid Daney
This patch addresses a couple of related problems: 1) The kernel may reside in physical memory outside of the ranges set by plat_mem_setup(). If this is the case, init mem cannot be reused as it resides outside of the range of pages that the kernel memory allocators control. 2) initrd images might be loaded in physical memory outside of the ranges set by plat_mem_setup(). The memory likewise cannot be reused. The patch doesn't handle this specific case, but the infrastructure is useful for future patches that do. The crux of the problem is that there are memory regions that need be memory_present(), but that cannot be free_bootmem() at the time of arch_mem_init(). We create a new type of memory (BOOT_MEM_INIT_RAM) for use with add_memory_region(). Then arch_mem_init() adds the init mem with this type if the init mem is not already covered by existing ranges. When memory is being freed into the bootmem allocator, we skip the BOOT_MEM_INIT_RAM ranges so they are not clobbered, but we do signal them as memory_present(). This way when they are later freed, the necessary memory manager structures have initialized and the Sparse allocater is prevented from crashing. The Octeon specific code that handled this case is removed, because the new general purpose code handles the case. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1988/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-07MIPS: Add fast get_user_pagesHillf Danton
Gup is used in a few cases, say futex. This work is derived from the x86 version, and operations of pte and pmd are adapted to the defines of MIPS in straight forward manner. [ralf@linux-mips.org: Fixed up reject in arch/mips/mm/Makefile due to whitespace formatting differences. Fixed build error in gup.c due to conflicting changes elsewhere in the kernel.] Signed-off-by: Hillf Danton <dhillf@gmail.com> Cc: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2859/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-12-07MIPS: Hugetlb: Keep TLB cache hot while flushingHillf Danton
If we only flush the TLB of the given huge page, the TLB cache remains hot for the relevant mm as it is, and less will be refilled after flush, huge or not. Signed-off-by: Hillf Danton <dhillf@gmail.com> Cc: linux-mips@linux-mips.org Acked-by: David Daney <david.daney@cavium.com> Patchwork: https://patchwork.linux-mips.org/patch/2860/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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