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2021-10-20Merge tag 'sunxi-dt-for-5.16-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt Our usual round of DT patches for the 5.16 merge window, with: - DT schema fixes - I2S support for the R40 - HDMI support for the pinetab - devfreq support for the A64 GPU * tag 'sunxi-dt-for-5.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (21 commits) dt-bindings: interconnect: sunxi: Add R40 MBUS compatible arm64: dts: allwinner: NanoPi R1S H5: Add generic compatible string for I2C EEPROM arm64: dts: allwinner: pinetab: Add HDMI support arm64: dts: allwinner: a64: Add GPU opp table ARM: dts: sun8i: r40: Add I2S nodes dt-bindings: sound: sun4i-i2s: add Allwinner R40 I2S compatible arm64: dts: allwinner: teres-i: Remove wakekup-source from the PMIC arm64: dts: allwinner: teres-i: Add missing reg arm64: dts: allwinner: pinetab: Change regulator node name to avoid warning arm64: dts: allwinner: a100: Fix thermal zone node name arm64: dts: allwinner: h6: Fix de3 parent clocks ordering arm64: dts: allwinner: h5: Fix GPU thermal zone node name ARM: dts: cubieboard4: Remove the dumb-vga-dac compatible ARM: dts: tbs711: Fix touchscreen compatible ARM: dts: sunxi: Fix the SPI NOR node names ARM: dts: sunxi: Fix OPPs node name ARM: dts: sunxi: Fix OPP arrays ARM: dts: sunxi: Rename gpio pinctrl names ARM: dts: sunxi: Rename power-supply names dt-bindings: sunxi: Add Allwinner A80 PRCM Binding ... Link: https://lore.kernel.org/r/5cad5ac6-187d-4d36-9437-5821c6e8242d.lettre@localhost Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-10-20x86/fpu: Provide a proper function for ex_handler_fprestore()Thomas Gleixner
To make upcoming changes for support of dynamically enabled features simpler, provide a proper function for the exception handler which removes exposure of FPU internals. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20211015011540.053515012@linutronix.de
2021-10-20x86/fpu: Replace the includes of fpu/internal.hThomas Gleixner
Now that the file is empty, fixup all references with the proper includes and delete the former kitchen sink. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20211015011540.001197214@linutronix.de
2021-10-20x86/fpu: Mop up the internal.h leftoversThomas Gleixner
Move the global interfaces to api.h and the rest into the core. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20211015011539.948837194@linutronix.de
2021-10-20x86/sev: Include fpu/xcr.hThomas Gleixner
Include the header which only provides the XCR accessors. That's all what is needed here. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20211015011539.896573039@linutronix.de
2021-10-20x86/fpu: Remove internal.h dependency from fpu/signal.hThomas Gleixner
In order to remove internal.h make signal.h independent of it. Include asm/fpu/xstate.h to fix a missing update_regset_xstate_info() prototype, which is Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20211015011539.844565975@linutronix.de
2021-10-20x86/fpu: Move fpstate functions to api.hThomas Gleixner
Move function declarations which need to be globally available to api.h where they belong. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20211015011539.792363754@linutronix.de
2021-10-20x86/fpu: Move mxcsr related code to coreThomas Gleixner
No need to expose that to code which only needs the XCR0 accessors. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20211015011539.740012411@linutronix.de
2021-10-20x86/fpu: Move fpregs_restore_userregs() to coreThomas Gleixner
Only used internally in the FPU core code. While at it, convert to the percpu accessors which verify preemption is disabled. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20211015011539.686806639@linutronix.de
2021-10-20x86/fpu: Make WARN_ON_FPU() privateThomas Gleixner
No point in being in global headers. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20211015011539.628516182@linutronix.de
2021-10-20x86/fpu: Move legacy ASM wrappers to coreThomas Gleixner
Nothing outside the core code requires them. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20211015011539.572439164@linutronix.de
2021-10-20x86/fpu: Move os_xsave() and os_xrstor() to coreThomas Gleixner
Nothing outside the core code needs these. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20211015011539.513368075@linutronix.de
2021-10-20x86/fpu: Make os_xrstor_booting() privateThomas Gleixner
It's only required in the xstate init code. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20211015011539.455836597@linutronix.de
2021-10-20x86/fpu: Clean up CPU feature testsThomas Gleixner
Further disintegration of internal.h: Move the CPU feature tests to a core header and remove the unused one. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20211015011539.401510559@linutronix.de
2021-10-20x86/fpu: Move context switch and exit to user inlines into sched.hThomas Gleixner
internal.h is a kitchen sink which needs to get out of the way to prepare for the upcoming changes. Move the context switch and exit to user inlines into a separate header, which is all that code needs. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20211015011539.349132461@linutronix.de
2021-10-20x86/fpu: Mark fpu__init_prepare_fx_sw_frame() as __initThomas Gleixner
No need to keep it around. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20211015011539.296435736@linutronix.de
2021-10-20x86/fpu: Rework copy_xstate_to_uabi_buf()Thomas Gleixner
Prepare for replacing the KVM copy xstate to user function by extending copy_xstate_to_uabi_buf() with a pkru argument which allows the caller to hand in the pkru value, which is required for KVM because the guest PKRU is not accessible via current. Fixup all callsites accordingly. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20211015011539.191902137@linutronix.de
2021-10-20x86/fpu: Replace KVMs home brewed FPU copy from userThomas Gleixner
Copying a user space buffer to the memory buffer is already available in the FPU core. The copy mechanism in KVM lacks sanity checks and needs to use cpuid() to lookup the offset of each component, while the FPU core has this information cached. Make the FPU core variant accessible for KVM and replace the home brewed mechanism. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: kvm@vger.kernel.org Link: https://lkml.kernel.org/r/20211015011539.134065207@linutronix.de
2021-10-20x86/fpu: Move KVMs FPU swapping to FPU coreThomas Gleixner
Swapping the host/guest FPU is directly fiddling with FPU internals which requires 5 exports. The upcoming support of dynamically enabled states would even need more. Implement a swap function in the FPU core code and export that instead. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Cc: kvm@vger.kernel.org Link: https://lkml.kernel.org/r/20211015011539.076072399@linutronix.de
2021-10-20x86/fpu/xstate: Mark all init only functions __initThomas Gleixner
No point to keep them around after boot. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20211015011539.017919252@linutronix.de
2021-10-20x86/fpu/xstate: Provide and use for_each_xfeature()Thomas Gleixner
These loops evaluating xfeature bits are really hard to read. Create an iterator and use for_each_set_bit_from() inside which already does the right thing. No functional changes. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20211015011538.958107505@linutronix.de
2021-10-20x86/fpu: Cleanup xstate xcomp_bv initializationThomas Gleixner
No point in having this duplicated all over the place with needlessly different defines. Provide a proper initialization function which initializes user buffers properly and make KVM use it. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20211015011538.897664678@linutronix.de
2021-10-20x86/fpu: Do not inherit FPU context for kernel and IO worker threadsThomas Gleixner
There is no reason why kernel and IO worker threads need a full clone of the parent's FPU state. Both are kernel threads which are not supposed to use FPU. So copying a large state or doing XSAVE() is pointless. Just clean out the minimally required state for those tasks. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20211015011538.839822981@linutronix.de
2021-10-20x86/process: Clone FPU in copy_thread()Thomas Gleixner
There is no reason to clone FPU in arch_dup_task_struct(). Quite the contrary - it prevents optimizations. Move it to copy_thread(). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20211015011538.780714235@linutronix.de
2021-10-20x86/fpu: Remove pointless memset in fpu_clone()Thomas Gleixner
Zeroing the forked task's FPU registers buffer to avoid leaking init optimized stale data into the clone is a pointless exercise for the case where the current task has TIF_NEED_FPU_LOAD set. In that case, the FPU registers state is copied from current's FPU register buffer which can contain stale init optimized data as well. The alledged information leak is non-existant because this stale init optimized data is used nowhere and cannot leak anywhere. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20211015011538.722854569@linutronix.de
2021-10-20x86/fpu: Cleanup the on_boot_cpu clutterThomas Gleixner
Defensive programming is useful, but this on_boot_cpu debug is really silly. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20211015011538.665080855@linutronix.de
2021-10-20x86/fpu: Restrict xsaves()/xrstors() to independent statesThomas Gleixner
These interfaces are really only valid for features which are independently managed and not part of the task context state for various reasons. Tighten the checks and adjust the misleading comments. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20211015011538.608492174@linutronix.de
2021-10-20x86/pkru: Remove useless includeThomas Gleixner
PKRU code does not need anything from FPU headers. Include cpufeature.h instead and fixup the resulting fallout in perf. This is a preparation for FPU changes in order to prevent recursive include hell. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20211015011538.551522694@linutronix.de
2021-10-20x86/fpu: Update stale commentsThomas Gleixner
copy_fpstate_to_sigframe() does not have a slow path anymore. Neither does the !ia32 restore in __fpu_restore_sig(). Update the comments accordingly. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20211015011538.493570236@linutronix.de
2021-10-20x86/fpu: Remove pointless argument from switch_fpu_finish()Thomas Gleixner
Unused since the FPU switching rework. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20211015011538.433135710@linutronix.de
2021-10-20Merge tag 'imx-dt64-5.16' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt i.MX arm64 device tree changes for 5.16: - New board support: LX2160A based BlueBox3, S32G2 EVB and RDB2 boards. - Quite some updates on imx8mq-librem5 board: delay the startup of the SDIO, add power sequencing for M.2 cards, add wifi regulator, add panel reset GPIO, fix led_r and led_g pinctrl, etc. - Fix the SPI chipselect polarity for a couple of i.MX8MM boards. - Add GPU nodes for i.MX8MM 2D and 3D core. - Add VPU and DISP blk-ctrl devices for i.MX8MM. - A series from Michael Walle to LS1028A device trees and add GPU support. - Random and small updates on various boards. * tag 'imx-dt64-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (37 commits) arm64: dts: imx8mm-kontron: Add support for ultra high speed modes on SD card arm64: dts: imx8mm-venice-gw7901.dts: disable pgc_gpumix arm64: dts: imx8mq-librem5: set debounce interval of volume buttons to 50ms arm64: dts: imx8mq-librem5: Limit the max sdio frequency arm64: dts: imx8mq-librem5: add power sequencing for M.2 cards arm64: dts: imx8mq-librem5: delay the startup of the SDIO arm64: dts: imx8mq-librem5: wire up the wifi regulator arm64: dts: imx8mq-librem5: Fix led_r and led_g pinctrl assignments arm64: dts: imx8mq-librem5: add reset gpio to mantix panel description arm64: dts: imx8mm-kontron: Fix reset delays for ethernet PHY arm64: dts: imx8mm: add DISP blk-ctrl arm64: dts: imx8mm: add VPU blk-ctrl arm64: dts: imx8mm: Add GPU nodes for 2D and 3D core arm64: dts: imx8mm: put USB controllers into power-domains arm64: dts: imx8mm: add GPC node arm64: dts: ls1028a: mark internal links between Felix and ENETC as capable of flow control arm64: dts: freescale: Fix 'interrupt-map' parent address cells arm64: dts: ls1028a: use phy-mode instead of phy-connection-type arm64: dts: ls1028a: move PHY nodes to MDIO controller arm64: dts: ls1028a: disable usb controller by default ... Link: https://lore.kernel.org/r/20211016140138.1603-4-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-10-20Merge tag 'imx-dt-5.16' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt i.MX device tree changes for 5.16: - New board support: Kobo Libra H2O, Tolino Vision 5, SKOV LT2 and Colibri i.MX6ULL eMMC variants. - A series from Fabio Estevam to correct SPI chipselect polarity for various i.MX6/7 boards. - A couple of patches from Krzysztof Kozlowski to clean up unsupported properties from imx6dl-b1x5v2 and imx6dl-prtrvt boards. - A series from Li Yang to clean up LS1021a based boards and add missing device nodes. - A series from Matthias Schiffer to fix typo, add SPI-NOR flash and partition layout for imx7-tqma7/mba7 boards. - Fix the schema check errors in i.MX PCIe device nodes. - Other random and small fix-up and device additions. * tag 'imx-dt-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (42 commits) ARM: dts: ls1021a-tsn: use generic "jedec,spi-nor" compatible for flash ARM: dts: ls1021a: move thermal-zones node out of soc/ ARM: dts: ls1021a-tsn: remove undocumented property "position" from mma8452 node ARM: dts: ls1021a-qds: change fpga to simple-mfd device ARM: dts: ls1021a: add #power-domain-cells for power-controller node ARM: dts: ls1021a: add #dma-cells to qdma node ARM: dts: ls1021a: fix memory node for schema check ARM: dts: ls1021a: remove regulators simple-bus ARM: dts: ls1021a: disable ifc node by default ARM: dts: ls1021a: breakup long values in thermal node ARM: dts: ls1021a: fix board compatible to follow binding schema ARM: dts: ls1021a: update pcie nodes for dt-schema check ARM: dts: ls1021a-qds: Add node for QSPI flash ARM: dts: ls1021a: change to use SPDX identifiers ARM: dts: ls1021a: change dma channels order to match schema ARM: dts: ls1021a: remove clock-names property for i2c nodes ARM: dts: imx6dl-prtrvt: drop undocumented TRF7970A NFC properties ARM: dts: imx6: phytec: Add gpio pinctrl for i2c bus recovery ARM: dts: imx6: skov: provide panel support for lt2 variants ARM: dts: imx6qdl-apalis: Fix typo in ADC comment ... Link: https://lore.kernel.org/r/20211016140138.1603-3-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-10-20Merge tag 'visconti-arm-dt-for-v5.16' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/iwamatsu/linux-visconti into arm/dt Visconti device tree updates for 5.16 - Add DT support for Toshiba Visconti5 PCIe driver - Add 150MHz fixed clock to TMPV7708 SoC - Add DT support for VisROBO VRB boardi * tag 'visconti-arm-dt-for-v5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/iwamatsu/linux-visconti: arm64: dts: visconti: Add DTS for the VisROBO board dt-bindings: arm: toshiba: Add the TMPV7708 VisROBO VRB board arm64: dts: visconti: Add 150MHz fixed clock to TMPV7708 SoC arm64: dts: visconti: Add PCIe host controller support for TMPV7708 SoC Link: https://lore.kernel.org/r/YWoH3g7vU1ZEAp+P@toshiba.co.jp Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-10-20Merge tag 'mvebu-dt-5.16-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into arm/dt mvebu dt for 5.16 (part 1) Add support for Netgear GS110EMX switch (Armada 381 SoC based) * tag 'mvebu-dt-5.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu: ARM: dts: mvebu: add device tree for netgear gs110emx switch Link: https://lore.kernel.org/r/874k9imeel.fsf@BL-laptop Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-10-20Merge tag 'mvebu-dt64-5.16-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into arm/dt mvebu dt64 for 5.16 (part 1) Add support for Globalscale MOCHAbin an Armada 7040 based development board. * tag 'mvebu-dt64-5.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu: arm64: dts: marvell: add Globalscale MOCHAbin Link: https://lore.kernel.org/r/877deemefy.fsf@BL-laptop Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-10-20KVM: s390: preserve deliverable_mask in __airqs_kick_single_vcpuHalil Pasic
Changing the deliverable mask in __airqs_kick_single_vcpu() is a bug. If one idle vcpu can't take the interrupts we want to deliver, we should look for another vcpu that can, instead of saying that we don't want to deliver these interrupts by clearing the bits from the deliverable_mask. Fixes: 9f30f6216378 ("KVM: s390: add gib_alert_irq_handler()") Signed-off-by: Halil Pasic <pasic@linux.ibm.com> Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Michael Mueller <mimu@linux.ibm.com> Reviewed-by: Claudio Imbrenda <imbrenda@linux.ibm.com> Link: https://lore.kernel.org/r/20211019175401.3757927-3-pasic@linux.ibm.com Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2021-10-20KVM: s390: clear kicked_mask before sleeping againHalil Pasic
The idea behind kicked mask is that we should not re-kick a vcpu that is already in the "kick" process, i.e. that was kicked and is is about to be dispatched if certain conditions are met. The problem with the current implementation is, that it assumes the kicked vcpu is going to enter SIE shortly. But under certain circumstances, the vcpu we just kicked will be deemed non-runnable and will remain in wait state. This can happen, if the interrupt(s) this vcpu got kicked to deal with got already cleared (because the interrupts got delivered to another vcpu). In this case kvm_arch_vcpu_runnable() would return false, and the vcpu would remain in kvm_vcpu_block(), but this time with its kicked_mask bit set. So next time around we wouldn't kick the vcpu form __airqs_kick_single_vcpu(), but would assume that we just kicked it. Let us make sure the kicked_mask is cleared before we give up on re-dispatching the vcpu. Fixes: 9f30f6216378 ("KVM: s390: add gib_alert_irq_handler()") Reported-by: Matthew Rosato <mjrosato@linux.ibm.com> Signed-off-by: Halil Pasic <pasic@linux.ibm.com> Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Michael Mueller <mimu@linux.ibm.com> Reviewed-by: Claudio Imbrenda <imbrenda@linux.ibm.com> Link: https://lore.kernel.org/r/20211019175401.3757927-2-pasic@linux.ibm.com Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2021-10-20powerpc/smp: do not decrement idle task preempt count in CPU offlineNathan Lynch
With PREEMPT_COUNT=y, when a CPU is offlined and then onlined again, we get: BUG: scheduling while atomic: swapper/1/0/0x00000000 no locks held by swapper/1/0. CPU: 1 PID: 0 Comm: swapper/1 Not tainted 5.15.0-rc2+ #100 Call Trace: dump_stack_lvl+0xac/0x108 __schedule_bug+0xac/0xe0 __schedule+0xcf8/0x10d0 schedule_idle+0x3c/0x70 do_idle+0x2d8/0x4a0 cpu_startup_entry+0x38/0x40 start_secondary+0x2ec/0x3a0 start_secondary_prolog+0x10/0x14 This is because powerpc's arch_cpu_idle_dead() decrements the idle task's preempt count, for reasons explained in commit a7c2bb8279d2 ("powerpc: Re-enable preemption before cpu_die()"), specifically "start_secondary() expects a preempt_count() of 0." However, since commit 2c669ef6979c ("powerpc/preempt: Don't touch the idle task's preempt_count during hotplug") and commit f1a0a376ca0c ("sched/core: Initialize the idle task with preemption disabled"), that justification no longer holds. The idle task isn't supposed to re-enable preemption, so remove the vestigial preempt_enable() from the CPU offline path. Tested with pseries and powernv in qemu, and pseries on PowerVM. Fixes: 2c669ef6979c ("powerpc/preempt: Don't touch the idle task's preempt_count during hotplug") Signed-off-by: Nathan Lynch <nathanl@linux.ibm.com> Reviewed-by: Valentin Schneider <valentin.schneider@arm.com> Reviewed-by: Srikar Dronamraju <srikar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20211015173902.2278118-1-nathanl@linux.ibm.com
2021-10-20powerpc/idle: Don't corrupt back chain when going idleMichael Ellerman
In isa206_idle_insn_mayloss() we store various registers into the stack red zone, which is allowed. However inside the IDLE_STATE_ENTER_SEQ_NORET macro we save r2 again, to 0(r1), which corrupts the stack back chain. We used to do the same in isa206_idle_insn_mayloss() itself, but we fixed that in 73287caa9210 ("powerpc64/idle: Fix SP offsets when saving GPRs"), however we missed that the macro also corrupts the back chain. Corrupting the back chain is bad for debuggability but doesn't necessarily cause a bug. However we recently changed the stack handling in some KVM code, and it now relies on the stack back chain being valid when it returns. The corruption causes that code to return with r1 pointing somewhere in kernel data, at some point LR is restored from the stack and we branch to NULL or somewhere else invalid. Only affects Power8 hosts running KVM guests, with dynamic_mt_modes enabled (which it is by default). The fixes tag below points to the commit that changed the KVM stack handling, exposing this bug. The actual corruption of the back chain has always existed since 948cf67c4726 ("powerpc: Add NAP mode support on Power7 in HV mode"). Fixes: 9b4416c5095c ("KVM: PPC: Book3S HV: Fix stack handling in idle_kvm_start_guest()") Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20211020094826.3222052-1-mpe@ellerman.id.au
2021-10-20arm64: dts: rockchip: Add idle cooling devices to rk3399Daniel Lezcano
The thermal framework accepts now the cpu idle cooling device as an alternative when the cpufreq cooling device fails. Add the node in the DT so the cooling devices will be present and the platforms can extend the thermal zone definition to add them. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20211001161728.1729664-1-daniel.lezcano@linaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-10-20ARM: dts: rockchip: remove usb-phy fallback string from rk3066a/rk3188Johan Jonker
With the conversion of rockchip-usb-phy.yaml a long time used fallback string for rk3066a/rk3188 was added. The linux driver doesn't do much with the GRF phy address range, however the u-boot driver rockchip_usb2_phy.c does. The bits in GRF_UOC0_CON2 for rk3066a/rk3188 and rk3288 for example don't match. Remove the usb-phy fallback string for rk3066a/rk3188 to prevent possible strange side effects. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20210828111218.10026-2-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-10-20ARM: dts: gemini: Consolidate PCI interrupt-map propertiesRob Herring
The Gemini PCI 'interrupt-map' does not vary by board, so let's move the definition to a common location. This avoids having incomplete interrupt properties (i.e. #interrupt-cells without interrupt-map). Cc: Hans Ulli Kroll <ulli.kroll@googlemail.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-10-19x86/ftrace: Remove fault protection code in prepare_ftrace_returnSteven Rostedt (VMware)
Removing the fault protection code when writing return_hooker to stack. As Steven noted: > That protection was there from the beginning due to being "paranoid", > considering ftrace was bricking network cards. But that protection > would not have even protected against that. Link: https://lkml.kernel.org/r/20211008091336.33616-3-jolsa@kernel.org Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org> Signed-off-by: Jiri Olsa <jolsa@kernel.org> Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
2021-10-19x86/ftrace: Remove extra orig rax moveJiri Olsa
There's identical move 2 lines earlier. Link: https://lkml.kernel.org/r/20211008091336.33616-2-jolsa@kernel.org Signed-off-by: Jiri Olsa <jolsa@kernel.org> Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
2021-10-20ARM: dts: ixp4xx: Group PCI interrupt properties togetherRob Herring
Move the PCI 'interrupt-map-mask' and '#interrupt-cells' properties alongside the 'interrupt-map' property in each board dts. This avoids having incomplete set of interrupt properties which may fail validation. Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Rob Herring <robh@kernel.org>
2021-10-20Merge tag 'stm32-dt-for-v5.16-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dt STM32 DT for v5.16, round 1 Highlights: ---------- - MPU: - ST boards: - Add new stm32mp135f-dk board. It embedds new STM32MP135 SoC, with 512 MB of DDR3. Several connections are available on this board: 4*USB2.0, 1*USB2.0 typeC DRD, SDcard, 2*RJ45, HDMI, Combo Wifi/BT, ... Only SD card, uart4 (console) and watchdog IPs are enabled in this tag. - Change IRQ level for STUSB1600 on DKx boards. - Fix SAI subclocks range. - Add ck_usb0_48m clock in USB OHCI node device to match with STM32MP15 datasheet. - DH boards: - Reduce DHCOR SPI NOR frequency to 50 MHz to avoid sporadic issues. - Fix SAI pin muxing. - Odyssey: - Set DCMI pins. * tag 'stm32-dt-for-v5.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: ARM: dts: stm32: use usbphyc ck_usbo_48m as USBH OHCI clock on stm32mp151 ARM: dts: stm32: fix AV96 board SAI2 pin muxing on stm32mp15 ARM: dts: stm32: fix SAI sub nodes register range ARM: dts: stm32: fix STUSB1600 Type-C irq level on stm32mp15xx-dkx ARM: dts: stm32: set the DCMI pins on stm32mp157c-odyssey ARM: dts: stm32: Reduce DHCOR SPI NOR frequency to 50 MHz ARM: dts: stm32: add initial support of stm32mp135f-dk board dt-bindings: stm32: document stm32mp135f-dk board ARM: dts: stm32: add STM32MP13 SoCs support Link: https://lore.kernel.org/r/9d52c3e2-a3b9-89f3-1896-7cd3560e7010@foss.st.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-10-20Merge tag 'renesas-arm-dt-for-v5.16-tag2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt Renesas ARM DT updates for v5.16 (take two) - SPI Multi I/O Bus, SDHI, and Ethernet support for the RZ/G2L SoC, - SPI Multi I/O Bus, camera, and video-on support for the R-Car V3U SoC, - SPI FLASH support for the Falcon development board, - eMMC, microSD, and Ethernet support for the RZ/G2L SMARC EVK development board, - 2 GHz High-Performance support for the R-Car H3e-2G, M3e-2G, and M3Ne-2G SoCs, - Miscellaneous fixes and improvements. * tag 'renesas-arm-dt-for-v5.16-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: mailmap: Fix text encoding for Niklas Söderlund arm64: dts: renesas: rcar-gen3e: Add Cortex-A57 2 GHz opps arm64: dts: renesas: rzg2l-smarc-som: Enable Ethernet arm64: dts: renesas: r9a07g044: Add GbEthernet nodes arm64: dts: renesas: Add ports node to all adv7482 nodes arm64: dts: renesas: r8a779a0: Add and connect all CSI-2, ISP and VIN nodes arm64: dts: renesas: rzg2l-smarc: Enable microSD on SMARC platform arm64: dts: renesas: rzg2l-smarc-som: Enable eMMC on SMARC platform arm64: dts: renesas: r9a07g044: Add SDHI nodes arm64: dts: renesas: falcon-cpu: Add SPI flash via RPC arm64: dts: renesas: r8a779a0: Add RPC node arm64: dts: renesas: r9a07g044: Add SPI Multi I/O Bus controller node Link: https://lore.kernel.org/r/cover.1634298094.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-10-19Merge tag 'aspeed-5.16-devicetree' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc into arm/dt ASPEED device tree updates for 5.15 - New machines: * TYAN S7106 BMC, a x86 server from about four years ago - Descriptions for the AST2600 ADC, which now has an upstream driver - Lots of GPIO line names. The OpenBMC project has adopted a scheme for naming the lines, and new additions will follow this guide - New I2C devices for Rainier, Everest, EthanolX, Mt Jade - Fixes for fp5280g2 which has seen some recent development, including the addtion of a QEmu machine for testing * tag 'aspeed-5.16-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc: ARM: dts: aspeed: fp5280g2: Use the 64M layout ARM: dts: aspeed: Add TYAN S7106 BMC machine ARM: dts: aspeed: rainier: Add power-config-full-load gpio ARM: dts: aspeed: p10bmc: Define secure boot gpio ARM: dts: aspeed: mtjade: Add some gpios ARM: dts: aspeed: Add ADC for AST2600 and enable for Rainier and Everest ARM: dts: everest: Define name for gpio line B6 ARM: dts: everest: Define name for gpio line Q2 ARM: dts: rainier: Define name for gpio line Q2 ARM: dts: everest: Add 'factory-reset-toggle' as GPIOF6 ARM: dts: aspeed: everest: Add I2C bus 15 muxes ARM: dts: aspeed: rainier: Add system LEDs ARM: dts: aspeed: amd-ethanolx: Add FRU EEPROM ARM: dts: fp5280g2: Enable KCS 3 for MCTP binding Link: https://lore.kernel.org/r/CACPK8XdrMzY9tzdof7KpzxKquTo7GcWW4N9Zqwtmmu73C7htXA@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-10-19Merge tag 'hisi-arm64-dt-for-5.16' of git://github.com/hisilicon/linux-hisi ↵Arnd Bergmann
into arm/dt ARM64: DT: HiSilicon ARM64 DT updates for 5.16 - Add SPMI PMIC support for the Hikey970 board - Correct the sp805 watchdog compatible string to match the document - Correct the operating-points table name to match the dtschema * tag 'hisi-arm64-dt-for-5.16' of git://github.com/hisilicon/linux-hisi: arm64: dts: hisilicon: align operating-points table name with dtschema arm64: dts: hisilicon: fix arm,sp805 compatible string arm64: dts: hisilicon: Add support for Hikey 970 PMIC Link: https://lore.kernel.org/r/6168EB53.60503@hisilicon.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-10-19Merge tag 'ux500-dts-for-v5.16' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into arm/dt Ux500 DTS updates: - Flag the janice SPI display lines properly for the right line semantics. - Fix some errors in the Skomer regulator configuration. - Fix some SD card pin configurations on Skomer. - Assign the Skomer SD card a 300 ms power-on delay. - Rewrite the battery nodes to use the standard binding "monitored-battery" as used in the updated bindings, and provide the right Samsung battery compatibles for the Samsung phones. * tag 'ux500-dts-for-v5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik: ARM: dts: ux500: Switch battery nodes to standard ARM: dts: ux500: Skomer eMMC needs 300 ms power on ARM: dts: ux500: Fix up SD card pin config ARM: dts: ux500: Skomer regulator fixes ARM: dts: ux500: Tag Janice display SPI correct Link: https://lore.kernel.org/r/CACRpkdYf5GwRvG1Gemk4mE+aw6UnAVTY8OudwsVNPQXThHXu6g@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
generated by cgit (git 2.34.1) at 2025-09-19 04:58:20 +0000