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2013-07-01MIPS: BCM63xx: Add SMP support to prom.cKevin Cernekee
This involves two changes to the BSP code: 1) register_smp_ops() for BMIPS SMP 2) The CPU1 boot vector on some of the BCM63xx platforms conflicts with the special interrupt vector (IV). Move it to 0x8000_0380 at boot time, to resolve the conflict. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> [jogo@openwrt.org: moved SMP ops registration into ifdef guard, changed ifdef guards to if (IS_ENABLED())] Signed-off-by: Jonas Gorski <jogo@openwrt.org> Cc: linux-mips@linux-mips.org Cc: John Crispin <blogic@openwrt.org> Cc: Maxime Bizon <mbizon@freebox.fr> Cc: Florian Fainelli <florian@openwrt.org> Patchwork: https://patchwork.linux-mips.org/patch/5489/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: define write{b,w,l,q}_relaxedFlorian Fainelli
MIPS does define read{b,w,l,q}_relaxed but does not define their write counterparts: write{b,w,l,q}_relaxed. This patch adds the missing definitions for the write*_relaxed I/O accessors. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Cc: jogo@openwrt.org Patchwork: https://patchwork.linux-mips.org/patch/5352/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: Expose missing pci_io{map,unmap} declarationsMarkos Chandras
The GENERIC_PCI_IOMAP does not depend on CONFIG_PCI so move it to the CONFIG_MIPS symbol so it's always selected for MIPS. This fixes the missing pci_iomap declaration for MIPS. Moreover, the pci_iounmap function was not defined in the io.h header file if the CONFIG_PCI symbol is not set, but it should since MIPS is not using CONFIG_GENERIC_IOMAP. This fixes the following problem on a allyesconfig: drivers/net/ethernet/3com/3c59x.c:1031:2: error: implicit declaration of function 'pci_iomap' [-Werror=implicit-function-declaration] drivers/net/ethernet/3com/3c59x.c:1044:3: error: implicit declaration of function 'pci_iounmap' [-Werror=implicit-function-declaration] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Acked-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5478/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: Malta: Update GCMP detection.Leonid Yegoshin
Add GCMP detection for IASim Marvell chip emulation support. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Acked-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/5529/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01Revert "MIPS: make CAC_ADDR and UNCAC_ADDR account for PHYS_OFFSET"Leonid Yegoshin
This reverts commit 3f4579252aa166641861a64f1c2883365ca126c2. It is invalid because the macros CAC_ADDR and UNCAC_ADDR have a kernel virtual address as an argument and also returns a kernel virtual address. Using and physical address PHYS_OFFSET is blatantly wrong for a macro common to multiple platforms. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Acked-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Florian Fainelli <florian@openwrt.org> Patchwork: https://patchwork.linux-mips.org/patch/5528/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: APSP: Remove <asm/kspd.h>Deng-Cheng Zhu
Now that KSPD is gone, kspd.h has no reason to be there. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: kevink@paralogos.com Cc: macro@linux-mips.org Cc: john@phrozen.org Patchwork: https://patchwork.linux-mips.org/patch/5060/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: microMIPS: Fix improper definition of ISA exception bit.Steven J. Hill
The ISA exception bit selects whether exceptions are taken in classic or microMIPS mode. This bit is Config3.ISAOnExc and was improperly defined as bits 16 and 17 instead of just bit 16. A new function was added so that platforms could set this bit when running a kernel compiled with only microMIPS instructions. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5377/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: Don't try to decode microMIPS branch instructions where they cannot exist.David Daney
In mm_isBranchInstr() we can short circuit the entire function if !cpu_has_mmips. Signed-off-by: David Daney <david.daney@cavium.com> Acked-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5326/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: Declare emulate_load_store_microMIPS as a static function.David Daney
It is only used from within a single file, it should not be globally visible. Signed-off-by: David Daney <david.daney@cavium.com> Acked-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5325/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: Fix typos and cleanup commentTony Wu
Signed-off-by: Tony Wu <tung7970@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5535/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: Cleanup indentation and whitespaceTony Wu
Signed-off-by: Tony Wu <tung7970@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5536/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: BMIPS: support booting from physical CPU other than 0Florian Fainelli
BMIPS43xx CPUs have two hardware threads, and on some SoCs such as 3368, the bootloader has configured the system to boot from TP1 instead of the more usual TP0. Create the physical to logical CPU mapping to cope with that, do not remap the software interrupts to be cross CPUs such that we do not have to do use the logical CPU mapping further down the code, and finally, reset the slave TP1 only if booted from TP0. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: Florian Fainelli <florian@openwrt.org> Cc: linux-mips@linux-mips.org Cc: blogic@openwrt.org Cc: cernekee@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/5553/ Patchwork: https://patchwork.linux-mips.org/patch/5556/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: Only set cpu_has_mmips if SYS_SUPPORTS_MICROMIPSDavid Daney
As Jonas Gorske said in his patch: Disable cpu_has_mmips for everything but SEAD3 and MALTA. Most of these platforms are from before the micromips introduction, so they are very unlikely to implement it. Reduces an -Os compiled, uncompressed kernel image by 8KiB for BCM63XX. This patch taks a different approach than his, we gate the runtime test for microMIPS by the config symbol SYS_SUPPORTS_MICROMIPS. Signed-off-by: David Daney <david.daney@cavium.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Acked-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5327/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: GIC: Fix gic_set_affinity infinite loopTony Wu
There is an infinite loop in gic_set_affinity. When irq_set_affinity gets called on gic controller, it blocks forever. Signed-off-by: Tony Wu <tung7970@gmail.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5537/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: Don't save/restore OCTEON wide multiplier state on syscalls.David Daney
The ABI allows these to be clobbered on syscalls, so only save and restore the multiplier state when the temporary registers need to be preserved. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: David Daney <david.daney@cavium.com> Patchwork: https://patchwork.linux-mips.org/patch/5540/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: Octeon: Enable interfaces on EdgeRouter LiteAaro Koskinen
Enable interfaces on EdgeRouter Lite. Tested with cavium_octeon_defconfig and busybox shell. DHCP & ping works with eth0, eth1 and eth2. The board type "UBNT_E100" is taken from the sources of the vendor kernel shipped with the product. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Acked-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5546/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: Move generated code to .text for microMIPSJayachandran C
Prepare of a next patch which will call tlbmiss_handler_setup_pgd on microMIPS. MicroMIPS complains if the called code s not in the .text section. To fix this we generate code into space reserved in arch/mips/mm/tlb-funcs.S While there, move the rest of the generated functions (handle_tlbl, handle_tlbs, handle_tlbm) to the same file. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5542/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: Get rid of MIPS I flag and test macros.Ralf Baechle
MIPS I is the ancestor of all MIPS ISA and architecture variants. Anything ever build in the MIPS empire is either MIPS I or at least contains MIPS I. If it's running Linux, that is. So there is little point in having cpu_has_mips_1 because it will always evaluate as true - though usually only at runtime. Thus there is no point in having the MIPS_CPU_ISA_I ISA flag, so get rid of it. Little complication: traps.c was using a test for a pure MIPS I ISA as a test for an R3000-style cp0. To deal with that, use a check for cpu_has_3kex or cpu_has_4kex instead. cpu_has_3kex is a new macro. At the moment its default implementation is !cpu_has_4kex but this may eventually change if Linux is ever going to support the oddball MIPS processors R6000 and R8000 so users of either of these macros should not make any assumptions. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/5551/
2013-07-01MIPS: Malta: Move platform-specific PCI code to arch/mips/pci.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: Sibyte: Fix comment.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: Sibyte: Remove duplicate but harmless line from Platform file.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: Update cavium_octeon_defconfigDavid Daney
The serial port changes make it advisable to enable the proper UART drivers. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: Jamie Iles <jamie@jamieiles.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Jiri Slaby <jslaby@suse.cz> Cc: linux-serial@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5518/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: OCTEON: Remove custom serial setup code.David Daney
We will use 8250_dw instead. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: Jamie Iles <jamie@jamieiles.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Jiri Slaby <jslaby@suse.cz> Cc: linux-serial@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5517/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: OCTEON: Set proper UART clock in internal device trees.David Daney
Following patch to use generic 8250 drivers will need proper clock information. So when using the internal device tree, populate the "clock-frequency" property with the correct value. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: Jamie Iles <jamie@jamieiles.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Jiri Slaby <jslaby@suse.cz> Cc: linux-serial@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5515/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: BCM63XX: add support for the Netgear CVG834GFlorian Fainelli
Add support for the Netgear CVG834G and enable the two UARTs, Ethernet on the first MAC, PCI and the two leds. Signed-off-by: Florian Fainelli <florian@openwrt.org> Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Cc: jogo@openwrt.org Cc: Florian Fainelli <florian@openwrt.org> Patchwork: https://patchwork.linux-mips.org/patch/5502/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: BCM63XX: let board specify an external GPIO to reset PHYFlorian Fainelli
Some boards may need to reset their external PHY or switch they are attached to, add a hook for doing this along with providing custom linux/gpio.h flags for doing this. Signed-off-by: Florian Fainelli <florian@openwrt.org> Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Cc: jogo@openwrt.org Cc: Florian Fainelli <florian@openwrt.org> Patchwork: https://patchwork.linux-mips.org/patch/5501/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: BCM63XX: provide a MAC address for BCM3368 chipsFlorian Fainelli
The BCM3368 SoC uses a NVRAM format which is not compatible with the one used by CFE, provide a default MAC address which is suitable for use and which is the default one also being used by the bootloader on these chips. Signed-off-by: Florian Fainelli <florian@openwrt.org> Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Cc: jogo@openwrt.org Patchwork: https://patchwork.linux-mips.org/patch/5498/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: BCM63XX: recognize Cable Modem firmware formatFlorian Fainelli
Add the firmware header format which is used by Broadcom Cable Modem SoCs such as the BCM3368 SoC. We export the bcm_hcs firmware format structure because it is used by user-land tools to create firmware images for these SoCs and will later be used by a corresponding MTD parser. Signed-off-by: Florian Fainelli <florian@openwrt.org> Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Cc: jogo@openwrt.org Patchwork: https://patchwork.linux-mips.org/patch/5496/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: BCM63XX: add support for BCM3368 Cable ModemFlorian Fainelli
The Broadcom BCM3368 Cable Modem SoC is extremely similar to the existing BCM63xx DSL SoCs, in particular BCM6358, therefore little effort in the existing code base is required to get it supported. This patch adds support for the following on-chip peripherals: - two UARTS - GPIO - Ethernet - SPI - PCI - NOR Flash The most noticeable difference with 3368 is that it has its peripheral register at 0xfff8_0000 we check that separately in ioremap.h. Since 3368 is identical to 6358 for its clock and reset bits, we use them verbatim. Signed-off-by: Florian Fainelli <florian@openwrt.org> Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Cc: jogo@openwrt.org Patchwork: https://patchwork.linux-mips.org/patch/5499/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: BCM63XX: select BOOT_RAWFlorian Fainelli
Enabling BOOT_RAW is mandatory to get a binary image (objcopy from ELF to binary) to work. This does not affect the ELF kernels which are used by CFE on BCM63XX DSL platforms, but is going to be necessary to support BCM63XX on Cable Modem chips such as BCM3368. Signed-off-by: Florian Fainelli <florian@openwrt.org> Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Cc: jogo@openwrt.org Patchwork: https://patchwork.linux-mips.org/patch/5500/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: Delete Wind River ppmc eval board support.Paul Gortmaker
This board has been EOL for many years now; lets not burden people doing build coverage and other tree wide work with working on essentially dead files. [ralf@linux-mips.org: Also remove arch/mips/include/asm/mach-wrppmc/war.h.] Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-mips@linux-mips.org Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Patchwork: http://patchwork.linux-mips.org/patch/5503/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: fcntl.h: Use __kernel_off_t, not off_t.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: Use proper include guard symbol for <uapi/asm/fcntl.h>.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: remove alloc_pci_controller prototypeJonas Gorski
Commit 610019baddcb4c4c323c12cd44ca7f73d7145d6f ("[MIPS] Remove unused function alloc_pci_controller.") removed the function, but left the prototype in the header file. Remove it as well so people don't get tempted to use it and wonder why it doesn't work. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5473/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: BCM63XX: select BMIPS4350 and default to 2 CPUs for supported SoCsJonas Gorski
All BCM63XX SoCs starting with BCM6358 have a BMIPS4350 instead of a BMIPS3300, so select it unless support for any of the older SoCs is selected. All BMIPS4350 have only two CPUs, so select the appropriate default. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Cc: linux-mips@linux-mips.org Cc: John Crispin <blogic@openwrt.org> Cc: Maxime Bizon <mbizon@freebox.fr> Cc: Florian Fainelli <florian@openwrt.org> Cc: Kevin Cernekee <cernekee@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/5355/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: BCM63XX: Handle SW IRQs 0-1Kevin Cernekee
MIPS software IRQs 0 and 1 are used for interprocessor signaling (IPI) on BMIPS SMP. Make the board support code aware of them. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> [jogo@openwrt.org: move sw irqs behind timer irq] Signed-off-by: Jonas Gorski <jogo@openwrt.org> Cc: linux-mips@linux-mips.org Cc: John Crispin <blogic@openwrt.org> Cc: Maxime Bizon <mbizon@freebox.fr> Cc: Florian Fainelli <florian@openwrt.org> Patchwork: https://patchwork.linux-mips.org/patch/5354/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: r4k,octeon,r2300: stack protector: change canary per taskGregory Fong
For non-SMP, uses the new random canary value that is stored in the task struct whenever a new task is forked. Based on ARM version in df0698be14c6683606d5df2d83e3ae40f85ed0d9 and subject to the same limitations: the variable GCC expects, __stack_chk_guard, is global, so this will not work on SMP. Quoting Nicolas Pitre <nico@fluxnic.net>: "One way to overcome this GCC limitation would be to locate the __stack_chk_guard variable into a memory page of its own for each CPU, and then use TLB locking to have each CPU see its own page at the same virtual address for each of them." Signed-off-by: Gregory Fong <gregory.0xf0@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5488/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: initial stack protector supportGregory Fong
Implements basic stack protector support based on ARM version in c743f38013aeff58ef6252601e397b5ba281c633 , with Kconfig option, constant canary value set at boot time, and script to check if compiler actually supports stack protector. Tested by creating a kernel module that writes past end of char[]. Signed-off-by: Gregory Fong <gregory.0xf0@gmail.com> Cc: linux-mips@linux-mips.org Cc: Filippo Arcidiacono <filippo.arcidiacono@st.com> Cc: Carmelo Amoroso <carmelo.amoroso@st.com> Patchwork: https://patchwork.linux-mips.org/patch/5448/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01MIPS: Boot: Compressed: Remove -fstack-protector from CFLAGSMarkos Chandras
When building with -fstack-protector, gcc emits the __stack_chk_guard and __stack_chk_fail symbols to check for stack stability. These symbols are defined in vmlinux but the generated vmlinux.bin that is used to create the compressed vmlinuz image has no symbol table so the linker can't find these symbols during the final linking phase. As a result of which, we need either to redefine these symbols just for the compressed image or drop the -fstack-protector option when building the compressed image. This patch implements the latter of two options. Fixes the following linking problem: dbg.c:(.text+0x7c): undefined reference to `__stack_chk_guard' dbg.c:(.text+0x80): undefined reference to `__stack_chk_guard' dbg.c:(.text+0xd4): undefined reference to `__stack_chk_guard' dbg.c:(.text+0xec): undefined reference to `__stack_chk_fail' [ralf@linux-mips.org: I'm applying this before the patch that actually adds stack protector support for MIPS. This means, it will not be possible to trigger above error message with any commit from the tree but rather they are what one would hit without this commit.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/5575/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-07-01Merge branch 'for-next/hugepages' of ↵Catalin Marinas
git://git.linaro.org/people/stevecapper/linux into upstream-hugepages * 'for-next/hugepages' of git://git.linaro.org/people/stevecapper/linux: ARM64: mm: THP support. ARM64: mm: Raise MAX_ORDER for 64KB pages and THP. ARM64: mm: HugeTLB support. ARM64: mm: Move PTE_PROT_NONE bit. ARM64: mm: Make PAGE_NONE pages read only and no-execute. ARM64: mm: Restore memblock limit when map_mem finished. mm: thp: Correct the HPAGE_PMD_ORDER check. x86: mm: Remove general hugetlb code from x86. mm: hugetlb: Copy general hugetlb code from x86 to mm. x86: mm: Remove x86 version of huge_pmd_share. mm: hugetlb: Copy huge_pmd_share from x86 to mm. Conflicts: arch/arm64/Kconfig arch/arm64/include/asm/pgtable-hwdef.h arch/arm64/include/asm/pgtable.h
2013-07-01Merge tag 'v3.10' into sched/coreIngo Molnar
Merge in a recent upstream commit: c2853c8df57f include/linux/math64.h: add div64_ul() because: 72a4cf20cb71 sched: Change cfs_rq load avg to unsigned long relies on it. [ We don't rebase sched/core for this, because the handful of followup commits after the broken commit are not behavioral changes so are unlikely to be needed during bisection. ] Signed-off-by: Ingo Molnar <mingo@kernel.org>
2013-07-01ARM: shmobile: r8a73a4: Fix resources for SCIFB0Takanari Hayama
Fix base address and IRQ resources associated with SCIFB0. This bug was introduced by e481a528901d0cd18b5b5fcbdc55207ea3b6ef68 ("ARM: shmobile: r8a73a4 SCIF support V3") which was included in v3.10. Signed-off-by: Takanari Hayama <taki@igel.co.jp> Acked-by: Magnus Damm <damm@opensource.se> [ horms+renesas@verge.net.au: Add information about commit and version this bug was added in ] Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Cc: stable@vger.kernel.org
2013-07-01powerpc/pseries: Support compression of oops text via pstoreAruna Balakrishnaiah
The patch set supports compression of oops messages while writing to NVRAM, this helps in capturing more of oops data to lnx,oops-log. The pstore file for oops messages will be in decompressed format making it readable. In case compression fails, the patch takes care of copying the header added by pstore and last oops_data_sz bytes of big_oops_buf to NVRAM so that we have recent oops messages in lnx,oops-log. In case decompression fails, it will result in absence of oops file but still have files (in /dev/pstore) for other partitions. Signed-off-by: Aruna Balakrishnaiah <aruna@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-07-01powerpc/pseries: Re-organise the oops compression codeAruna Balakrishnaiah
nvram_compress() and zip_oops() is used by the nvram_pstore_write API to compress oops messages hence re-organise the functions accordingly to avoid forward declarations. Signed-off-by: Aruna Balakrishnaiah <aruna@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-07-01pstore: Pass header size in the pstore write callbackAruna Balakrishnaiah
Header size is needed to distinguish between header and the dump data. Incorporate the addition of new argument (hsize) in the pstore write callback. Signed-off-by: Aruna Balakrishnaiah <aruna@linux.vnet.ibm.com> Acked-by: Kees Cook <keescook@chromium.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-07-01powerpc/powernv: Fix iommu initialization againBenjamin Herrenschmidt
So because those things always end up in trainwrecks... In 7846de406 we moved back the iommu initialization earlier, essentially undoing 37f02195b which was causing us endless trouble... except that in the meantime we had merged 959c9bdd58 (to workaround the original breakage) which is now ... broken :-) This fixes it by doing a partial revert of the latter (we keep the ppc_md. path which will be needed in the hotplug case, which happens also during some EEH error recovery situations). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> CC: <stable@vger.kernel.org> [v3.10]
2013-07-01Merge tag 'v3.10' into nextBenjamin Herrenschmidt
Merge 3.10 in order to get some of the last minute powerpc changes, resolve conflicts and add additional fixes on top of them.
2013-07-01powerpc/pseries: Inform the hypervisor we are using EBB regsMichael Ellerman
On LPAR systems we need to inform the hypervisor that we are using the EBB registers. We do this by setting a bit in the Virtual Processor Area (VPA) - formerly known as the lppaca. For now we do this always, ie. we do not dynamically enable/disable. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-07-01powerpc/perf: Add power8 EBB supportMichael Ellerman
Add logic to the power8 PMU code to support EBB. Future processors would also be expected to implement similar constraints. At that time we could possibly factor these out into common code. Finally mark the power8 PMU as supporting EBB, which is the actual enable switch which allows EBBs to be configured. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-07-01powerpc/perf: Core EBB support for 64-bit book3sMichael Ellerman
Add support for EBB (Event Based Branches) on 64-bit book3s. See the included documentation for more details. EBBs are a feature which allows the hardware to branch directly to a specified user space address when a PMU event overflows. This can be used by programs for self-monitoring with no kernel involvement in the inner loop. Most of the logic is in the generic book3s code, primarily to avoid a proliferation of PMU callbacks. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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