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2019-04-23ARM: 8857/1: efi: enable CP15 DMB instructions before cleaning the cacheArd Biesheuvel
The EFI stub is entered with the caches and MMU enabled by the firmware, and once the stub is ready to hand over to the decompressor, we clean and disable the caches. The cache clean routines use CP15 barrier instructions, which can be disabled via SCTLR. Normally, when using the provided cache handling routines to enable the caches and MMU, this bit is enabled as well. However, but since we entered the stub with the caches already enabled, this routine is not executed before we call the cache clean routines, resulting in undefined instruction exceptions if the firmware never enabled this bit. So set the bit explicitly in the EFI entry code, but do so in a way that guarantees that the resulting code can still run on v6 cores as well (which are guaranteed to have CP15 barriers enabled) Cc: <stable@vger.kernel.org> # v4.9+ Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2019-04-23ARM: 8856/1: NOMMU: Fix CCR register faulty initialization when MPU is disabledTigran Tadevosyan
When CONFIG_ARM_MPU is not defined, the base address of v7M SCB register is not initialized with correct value. This prevents enabling I/D caches when the L1 cache poilcy is applied in kernel. Fixes: 3c24121039c9da14692eb48f6e39565b28c0f3cf ("ARM: 8756/1: NOMMU: Postpone MPU activation till __after_proc_init") Signed-off-by: Tigran Tadevosyan <tigran.tadevosyan@arm.com> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2019-04-23ARM: fix function graph tracer and unwinder dependenciesRussell King
Naresh Kamboju recently reported that the function-graph tracer crashes on ARM. The function-graph tracer assumes that the kernel is built with frame pointers. We explicitly disabled the function-graph tracer when building Thumb2, since the Thumb2 ABI doesn't have frame pointers. We recently changed the way the unwinder method was selected, which seems to have made it more likely that we can end up with the function- graph tracer enabled but without the kernel built with frame pointers. Fix up the function graph tracer dependencies so the option is not available when we have no possibility of having frame pointers, and adjust the dependencies on the unwinder option to hide the non-frame pointer unwinder options if the function-graph tracer is enabled. Reviewed-by: Masami Hiramatsu <mhiramat@kernel.org> Tested-by: Masami Hiramatsu <mhiramat@kernel.org> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2019-04-23ARM: 8858/1: vdso: use $(LD) instead of $(CC) to link VDSOMasahiro Yamada
We use $(LD) to link vmlinux, modules, decompressors, etc. VDSO is the only exceptional case where $(CC) is used as the linker driver, but I do not know why we need to do so. VDSO uses a special linker script, and does not link standard libraries at all. I changed the Makefile to use $(LD) rather than $(CC). I confirmed the same vdso.so.raw was still produced. Users will be able to use their favorite linker (e.g. lld instead of of bfd) by passing LD= from the command line. My plan is to rewrite all VDSO Makefiles to use $(LD), then delete cc-ldoption. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2019-04-23ARM: 8855/1: remove unused <asm/limits.h>Masahiro Yamada
No one includes this. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2019-04-23ARM: 8850/1: use memblocks_presentPeng Fan
arm_memory_present is doing same thing as memblocks_present, so let's use common code memblocks_present instead of platform specific arm_memory_present. Patchwork: https://patchwork.kernel.org/patch/10805693/ Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2019-04-23ARM: 8854/1: drop -mauto-itStefan Agner
The assembler option -mauto-it is no longer a valid option. The last remaining references have been removed from the documentation in July 2009 [0]. The currently supported binutils version is 2.20 (released in September 2009) or higher where gas supports -mimplicit-it=always. Drop the fallback to -mauto-it and use -mimplicit-it=always only. [0] https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=529707530657a333a304c651c808ea630c955223 Signed-off-by: Stefan Agner <stefan@agner.ch> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2019-04-23ARM: 8846/1: warn if divided syntax assembler is usedStefan Agner
Remove the -mno-warn-deprecated assembler flag to make sure the GNU assembler warns in case non-unified syntax is used. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Nicolas Pitre <nico@linaro.org> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2019-04-23ARM: 8853/1: drop WASM to work around LLVM issueStefan Agner
Currently LLVM's integrated assembler does not recognize .w form of the pld instructions (LLVM Bug 40972 [0]): ./arch/arm/include/asm/processor.h:133:5: error: invalid instruction "pldw.wt%a0 n" ^ <inline asm>:2:1: note: instantiated into assembly here pldw.w [r0] ^ 1 error generated. The W macro for generating wide instructions when targeting Thumb-2 is not strictly required for the preload data instructions (pld, pldw) since they are only available as wide instructions. The GNU assembler works with or without the .w appended when compiling an Thumb-2 kernel. Drop the macro to work around LLVM Bug 40972 issue. [0] https://bugs.llvm.org/show_bug.cgi?id=40972 Signed-off-by: Stefan Agner <stefan@agner.ch> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2019-04-23ARM: 8852/1: uaccess: use unified assembler language syntaxStefan Agner
Convert the conditional infix to a postfix to make sure this inline assembly is unified syntax. Since gcc assumes non-unified syntax when emitting ARM instructions, make sure to define the syntax as unified. This allows to use LLVM's integrated assembler. Additionally, for GCC ".syntax unified" for inline assembly. When compiling non-Thumb2 GCC always emits a ".syntax divided" at the beginning of the inline assembly which makes the assembler fail. Since GCC 5 there is the -masm-syntax-unified GCC option which make GCC assume unified syntax asm and hence emits ".syntax unified" even in ARM mode. However, the option is broken since GCC version 6 (see GCC PR88648 [1]). Work around by adding ".syntax unified" as part of the inline assembly. [0] https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html#index-masm-syntax-unified [1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88648 Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2019-04-23ARM: 8851/1: add TUSERCOND() macro for conditional postfixStefan Agner
Unified assembly syntax requires conditionals to be postfixes. TUSER() currently only takes a single argument which then gets appended t (with translation) on every instruction. This fixes a build error when using LLVM's integrated assembler: In file included from kernel/futex.c:72: ./arch/arm/include/asm/futex.h:116:3: error: invalid instruction, did you mean: strt? "2: " TUSER(streq) " %3, [%4]n" ^ <inline asm>:5:4: note: instantiated into assembly here 2: streqt r2, [r4] ^~~~~~ Additionally, for GCC ".syntax unified" for inline assembly. When compiling non-Thumb2 GCC always emits a ".syntax divided" at the beginning of the inline assembly which makes the assembler fail. Since GCC 5 there is the -masm-syntax-unified GCC option which make GCC assume unified syntax asm and hence emits ".syntax unified" even in ARM mode. However, the option is broken since GCC version 6 (see GCC PR88648 [1]). Work around by adding ".syntax unified" as part of the inline assembly. [0] https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html#index-masm-syntax-unified [1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88648 Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2019-04-23x86/MCE/AMD: Don't report L1 BTB MCA errors on some family 17h modelsYazen Ghannam
AMD family 17h Models 10h-2Fh may report a high number of L1 BTB MCA errors under certain conditions. The errors are benign and can safely be ignored. However, the high error rate may cause the MCA threshold counter to overflow causing a high rate of thresholding interrupts. In addition, users may see the errors reported through the AMD MCE decoder module, even with the interrupt disabled, due to MCA polling. Clear the "Counter Present" bit in the Instruction Fetch bank's MCA_MISC0 register. This will prevent enabling MCA thresholding on this bank which will prevent the high interrupt rate due to this error. Define an AMD-specific function to filter these errors from the MCE event pool so that they don't get reported during early boot. Rename filter function in EDAC/mce_amd to avoid a naming conflict, while at it. [ bp: Move function prototype to the internal header and massage/cleanup, fix typos. ] Reported-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: "clemej@gmail.com" <clemej@gmail.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Morse <james.morse@arm.com> Cc: Kees Cook <keescook@chromium.org> Cc: Mauro Carvalho Chehab <mchehab@kernel.org> Cc: Pu Wen <puwen@hygon.cn> Cc: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Cc: Shirish S <Shirish.S@amd.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Cc: Vishal Verma <vishal.l.verma@intel.com> Cc: linux-edac <linux-edac@vger.kernel.org> Cc: x86-ml <x86@kernel.org> Cc: <stable@vger.kernel.org> # 5.0.x: c95b323dcd35: x86/MCE/AMD: Turn off MC4_MISC thresholding on all family 0x15 models Cc: <stable@vger.kernel.org> # 5.0.x: 30aa3d26edb0: x86/MCE/AMD: Carve out the MC4_MISC thresholding quirk Cc: <stable@vger.kernel.org> # 5.0.x: 9308fd407455: x86/MCE: Group AMD function prototypes in <asm/mce.h> Cc: <stable@vger.kernel.org> # 5.0.x Link: https://lkml.kernel.org/r/20190325163410.171021-2-Yazen.Ghannam@amd.com
2019-04-23x86/MCE: Add an MCE-record filtering functionYazen Ghannam
Some systems may report spurious MCA errors. In general, spurious MCA errors may be disabled by clearing a particular bit in MCA_CTL. However, clearing a bit in MCA_CTL may not be recommended for some errors, so the only option is to ignore them. An MCA error is printed and handled after it has been added to the MCE event pool. So an MCA error can be ignored by not adding it to that pool in the first place. Add such a filtering function. [ bp: Move function prototype to the internal header and massage. ] Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Arnd Bergmann <arnd@arndb.de> Cc: "clemej@gmail.com" <clemej@gmail.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Pu Wen <puwen@hygon.cn> Cc: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Cc: "rafal@milecki.pl" <rafal@milecki.pl> Cc: Shirish S <Shirish.S@amd.com> Cc: <stable@vger.kernel.org> # 5.0.x Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Cc: Vishal Verma <vishal.l.verma@intel.com> Cc: x86-ml <x86@kernel.org> Link: https://lkml.kernel.org/r/20190325163410.171021-1-Yazen.Ghannam@amd.com
2019-04-23x86/xen: Add "xen_timer_slop" command line optionRyan Thibodeaux
Add a new command-line option "xen_timer_slop=<INT>" that sets the minimum delta of virtual Xen timers. This commit does not change the default timer slop value for virtual Xen timers. Lowering the timer slop value should improve the accuracy of virtual timers (e.g., better process dispatch latency), but it will likely increase the number of virtual timer interrupts (relative to the original slop setting). The original timer slop value has not changed since the introduction of the Xen-aware Linux kernel code. This commit provides users an opportunity to tune timer performance given the refinements to hardware and the Xen event channel processing. It also mirrors a feature in the Xen hypervisor - the "timer_slop" Xen command line option. [boris: updated comment describing TIMER_SLOP] Signed-off-by: Ryan Thibodeaux <ryan.thibodeaux@starlab.io> Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com> Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
2019-04-23s390/cpum_cf_diag: Add support for CPU-MF SVN 6Thomas-Mich Richter
Add support for the CPU-Measurement Facility counter second version number 6. This number is used to detect some more counters in the crypto counter set and the extended counter set. Signed-off-by: Thomas Richter <tmricht@linux.ibm.com> Reviewed-by: Hendrik Brueckner <brueckner@linux.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2019-04-23s390/mm: convert to the generic get_user_pages_fast codeMartin Schwidefsky
Define the gup_fast_permitted to check against the asce_limit of the mm attached to the current task, then replace the s390 specific gup code with the generic implementation in mm/gup.c. Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2019-04-23s390/mm: make the pxd_offset functions more robustMartin Schwidefsky
Change the way how pgd_offset, p4d_offset, pud_offset and pmd_offset walk the page tables. pgd_offset now always calculates the index for the top-level page table and adds it to the pgd, this is either a segment table offset for a 2-level setup, a region-3 offset for 3-levels, region-2 offset for 4-levels, or a region-1 offset for a 5-level setup. The other three functions p4d_offset, pud_offset and pmd_offset will only add the respective offset if they dereference the passed pointer. With the new way of walking the page tables a sequence like this from mm/gup.c now works: pgdp = pgd_offset(current->mm, addr); pgd = READ_ONCE(*pgdp); p4dp = p4d_offset(&pgd, addr); p4d = READ_ONCE(*p4dp); pudp = pud_offset(&p4d, addr); pud = READ_ONCE(*pudp); pmdp = pmd_offset(&pud, addr); pmd = READ_ONCE(*pmdp); Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2019-04-23ARM: dts: Add queue manager and NPE to the IXP4xx DTSILinus Walleij
The AHB queue manager and Network Processing Engines are present on all IXP4xx SoCs, so we add them to the overarching device tree include. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23soc: ixp4xx: qmgr: Pass resourcesLinus Walleij
Instead of using hardcoded base address implicitly obtained through <linux/io.h>, pass the physical base for the QMGR block as a memory resource and remap it in the driver. Also pass the two IRQs as resources and obtain them in the driver. Use devm_* accessors and simplify the error path in the process. Drop memory region request as this is done by the devm_ioremap* functions. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23soc: ixp4xx: npe: Pass addresses as resourcesLinus Walleij
Instead of using hardcoded base addresses implicitly obtained through <linux/io.h>, pass the physical base for the three NPE blocks as memory resources and remap these in the driver. Drop the memory request region business, this will anyways be done by devm_* remapping functions. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23ARM: ixp4xx: Turn the QMGR into a platform deviceLinus Walleij
Instead of registering everything related to the QMGR unconditionally in the module_init() call (which will never work with multiplatform) create a platform device and probe the QMGR like any other device. Put the device second in the list of devices added for the platform so it is there when the dependent network and crypto drivers probe later on. This probe() path will not be taken unconditionally on device tree boots, so remove the DT guard. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23ARM: ixp4xx: Turn the NPE into a platform deviceLinus Walleij
Instead of registering everything related to the NPE unconditionally in the module_init() call (which will never work with multiplatform) create a platform device and probe the NPE like any other device. Put the device first in the list of devices added for the platform so it is there when the dependent network and crypto drivers probe later on. This probe() path will not be taken unconditionally on device tree boots, so remove the DT guard. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23ARM: ixp4xx: Move IXP4xx QMGR and NPE headersLinus Walleij
This moves the IXP4xx Queue Manager and Network Processing Engine headers out of the <mack/*> include path as that is incompatible with multiplatform. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23ARM: ixp4xx: Move NPE and QMGR to drivers/socLinus Walleij
The Network Processing Engine and Queue Manager are versatile firmware components used by several IXP4xx drivers. Drivers are relying on getting access to these components using <mach/*> headers which does not work with multiplatform. We need to find a better place for the drivers to live. Let's first move them to drivers/soc and the start to refactor a bit by passing resources and moving headers. This patch introduce static IRQ assignments but that will be fixed by later patches in this series. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23ARM: dts: Add some initial IXP4xx device treesLinus Walleij
This adds a device tree for the IXP4xx-based Linksys NSLU2 and Gateworks GW2358 which encompass the Gateworks Cambria family. These will be the first IXP4xx device tree platforms. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23ARM: ixp4xx: Add device tree boot supportLinus Walleij
This adds a minimal support for booting IXP4xx systems from device tree. We have to add hacks to the QMGR, NPE and notably also ethernet and watchdog drivers so that they don't crash the platform: these drivers are unconditionally starting to grab regions of statically remapped IO space with no concern of the device model or other platforms. We will go in and properly fix these drivers as we go along but for now this hack gets us to a place where we can start working on proper device tree support for these platforms. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23ARM: ixp4xx: Switch to use new timer driverLinus Walleij
This augments the IXP4xx to select and use the new timer driver in drivers/clocksource and removes the old code in the machine. Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23ARM: ixp4xx: Switch to use new IRQ+GPIO driversLinus Walleij
This deletes the old irq+gpiochip combo from the IXP4xx machine and switches it over to use the new drivers merged in respective subsystem. Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23arm64/module: ftrace: deal with place relative nature of PLTsArd Biesheuvel
Another bodge for the ftrace PLT code: plt_entries_equal() now takes the place relative nature of the ADRP/ADD based PLT entries into account, which means that a struct trampoline instance on the stack is no longer equal to the same set of opcodes in the module struct, given that they don't point to the same place in memory anymore. Work around this by using memcmp() in the ftrace PLT handling code. Acked-by: Will Deacon <will.deacon@arm.com> Tested-by: dann frazier <dann.frazier@canonical.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2019-04-23arm64: mm: Ensure tail of unaligned initrd is reservedBjorn Andersson
In the event that the start address of the initrd is not aligned, but has an aligned size, the base + size will not cover the entire initrd image and there is a chance that the kernel will corrupt the tail of the image. By aligning the end of the initrd to a page boundary and then subtracting the adjusted start address the memblock reservation will cover all pages that contains the initrd. Fixes: c756c592e442 ("arm64: Utilize phys_initrd_start/phys_initrd_size") Cc: stable@vger.kernel.org Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2019-04-23KVM: arm64: Add a vcpu flag to control ptrauth for guestAmit Daniel Kachhap
A per vcpu flag is added to check if pointer authentication is enabled for the vcpu or not. This flag may be enabled according to the necessary user policies and host capabilities. This patch also adds a helper to check the flag. Reviewed-by: Dave Martin <Dave.Martin@arm.com> Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Christoffer Dall <christoffer.dall@arm.com> Cc: kvmarm@lists.cs.columbia.edu Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-04-23arm64: dts: sdm845: Introduce ADSP and CDSP PAS nodesBjorn Andersson
Add the Audio DSP (ADSP) and Compute DSP (CDSP) nodes for TrustZone based remoteproc, supporting booting these cores on e.g. the MTP, and enable the same for the MTP. Tested-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Sibi Sankar <sibis@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
2019-04-23arm64: dts: qcom: sdm845: Define rmtfs memoryBjorn Andersson
Define the rmtfs memory node. As the memory region specified in version 10 of the memory map is only 1MB a chunk of unallocated memory is chosen. Tested-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Sibi Sankar <sibis@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
2019-04-23arm64: dts: qcom: sdm845: Update reserved memory mapBjorn Andersson
Update existing and add missing regions to the reserved memory map, as described in version 10. Reviewed-by: Sibi Sankar <sibis@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
2019-04-23arm64: dts: sdm845: Add UFS PHY resetEvan Green
Wire up the reset controller in the Qcom UFS controller for the PHY. This will be used to toggle PHY reset during initialization of the PHY. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Evan Green <evgreen@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
2019-04-23ARM: dts: imx7s: Specify #io-channel-cells in ADC nodesAndrey Smirnov
Specify #io-channel-cells in ADC nodes. Needed to be able to reference them by phandle. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Chris Healy <cphealy@gmail.com> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Fabio Estevam <festevam@gmail.com> Cc: Rob Herring <robh@kernel.org> Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-22Merge tag 'mips_fixes_5.1_3' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux Pull MIPS fixes from Paul Burton: "A couple more MIPS fixes: - Fix indirect syscall tracing & seccomp filtering for big endian MIPS64 kernels, which previously loaded the syscall number incorrectly & would always use zero. - Fix performance counter IRQ setup for Atheros/ath79 SoCs, allowing perf to function on those systems. And not really a fix, but a useful addition: - Add a Broadcom mailing list to the MAINTAINERS entry for BMIPS systems to allow relevant engineers to track patch submissions" * tag 'mips_fixes_5.1_3' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: MIPS: perf: ath79: Fix perfcount IRQ assignment MIPS: scall64-o32: Fix indirect syscall number load MAINTAINERS: BMIPS: Add internal Broadcom mailing list
2019-04-22Merge tag 'v5.1-rc6' into for-5.2/blockJens Axboe
Pull in v5.1-rc6 to resolve two conflicts. One is in BFQ, in just a comment, and is trivial. The other one is a conflict due to a later fix in the bio multi-page work, and needs a bit more care. * tag 'v5.1-rc6': (770 commits) Linux 5.1-rc6 block: make sure that bvec length can't be overflow block: kill all_q_node in request_queue x86/cpu/intel: Lower the "ENERGY_PERF_BIAS: Set to normal" message's log priority coredump: fix race condition between mmget_not_zero()/get_task_mm() and core dumping mm/kmemleak.c: fix unused-function warning init: initialize jump labels before command line option parsing kernel/watchdog_hld.c: hard lockup message should end with a newline kcov: improve CONFIG_ARCH_HAS_KCOV help text mm: fix inactive list balancing between NUMA nodes and cgroups mm/hotplug: treat CMA pages as unmovable proc: fixup proc-pid-vm test proc: fix map_files test on F29 mm/vmstat.c: fix /proc/vmstat format for CONFIG_DEBUG_TLBFLUSH=y CONFIG_SMP=n mm/memory_hotplug: do not unlock after failing to take the device_hotplug_lock mm: swapoff: shmem_unuse() stop eviction without igrab() mm: swapoff: take notice of completion sooner mm: swapoff: remove too limiting SWAP_UNUSE_MAX_TRIES mm: swapoff: shmem_find_swap_entries() filter out other types slab: store tagged freelist for off-slab slabmgmt ... Signed-off-by: Jens Axboe <axboe@kernel.dk>
2019-04-22x86/irq: Fix outdated commentsJiang Biao
INVALIDATE_TLB_VECTOR_START has been removed by: 52aec3308db8("x86/tlb: replace INVALIDATE_TLB_VECTOR by CALL_FUNCTION_VECTOR") while VSYSCALL_EMU_VECTO(204) has also been removed, by: 3ae36655b97a("x86-64: Rework vsyscall emulation and add vsyscall= parameter") so update the comments in <asm/irq_vectors.h> accordingly. Signed-off-by: Jiang Biao <benbjiang@tencent.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: bp@alien8.de Link: http://lkml.kernel.org/r/20190422024943.71918-1-benbjiang@tencent.com [ Improved the changelog. ] Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-04-22x86/boot: Disable RSDP parsing temporarilyBorislav Petkov
The original intention to move RDSP parsing very early, before KASLR does its ranges selection, was to accommodate movable memory regions machines (CONFIG_MEMORY_HOTREMOVE) to still be able to do memory hotplug. However, that broke kexec'ing a kernel on EFI machines because depending on where the EFI systab was mapped, on at least one machine it isn't present in the kexec mapping of the second kernel, leading to a triple fault in the early code. Fixing this properly requires significantly involved surgery and we cannot allow ourselves to do that, that close to the merge window. So disable the RSDP parsing code temporarily until it is fixed properly in the next release cycle. Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Baoquan He <bhe@redhat.com> Cc: Chao Fan <fanc.fnst@cn.fujitsu.com> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: indou.takao@jp.fujitsu.com Cc: Ingo Molnar <mingo@redhat.com> Cc: Juergen Gross <jgross@suse.com> Cc: kasong@redhat.com Cc: Kees Cook <keescook@chromium.org> Cc: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> Cc: msys.mizuma@gmail.com Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: x86-ml <x86@kernel.org> Link: https://lkml.kernel.org/r/20190419141952.GE10324@zn.tnic
2019-04-22x86/kdump: Fall back to reserve high crashkernel memoryDave Young
crashkernel=xM tries to reserve memory for the crash kernel under 4G, which is enough, usually. But this could fail sometimes, for example when one tries to reserve a big chunk like 2G, for example. So let the crashkernel=xM just fall back to use high memory in case it fails to find a suitable low range. Do not set the ,high as default because it allocates extra low memory for DMA buffers and swiotlb, and this is not always necessary for all machines. Typically, crashkernel=128M usually works with low reservation under 4G, so keep <4G as default. [ bp: Massage. ] Signed-off-by: Dave Young <dyoung@redhat.com> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Ingo Molnar <mingo@kernel.org> Acked-by: Baoquan He <bhe@redhat.com> Cc: Dave Young <dyoung@redhat.com> Cc: David Howells <dhowells@redhat.com> Cc: Eric Biederman <ebiederm@xmission.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Kosina <jkosina@suse.cz> Cc: Jonathan Corbet <corbet@lwn.net> Cc: Juergen Gross <jgross@suse.com> Cc: Kees Cook <keescook@chromium.org> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: linux-doc@vger.kernel.org Cc: "Paul E. McKenney" <paulmck@linux.ibm.com> Cc: Petr Tesarik <ptesarik@suse.cz> Cc: piliu@redhat.com Cc: Ram Pai <linuxram@us.ibm.com> Cc: Sinan Kaya <okaya@codeaurora.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Thymo van Beers <thymovanbeers@gmail.com> Cc: vgoyal@redhat.com Cc: x86-ml <x86@kernel.org> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Zhimin Gu <kookoo.gu@intel.com> Link: https://lkml.kernel.org/r/20190422031905.GA8387@dhcp-128-65.nay.redhat.com
2019-04-22x86/kdump: Have crashkernel=X reserve under 4G by defaultDave Young
The kdump crashkernel low reservation is limited to under 896M even for X86_64. This obscure and miserable limitation exists for compatibility with old kexec-tools but the reason is not documented anywhere. Some more tests/investigations about the background: a) Previously, old kexec-tools could only load purgatory to memory under 2G. Eric removed that limitation in 2012 in kexec-tools: b4f9f8599679 ("kexec x86_64: Make purgatory relocatable anywhere in the 64bit address space.") b) Back in 2013 Yinghai removed all the limitations in new kexec-tools, bzImage64 can be loaded anywhere: 82c3dd2280d2 ("kexec, x86_64: Load bzImage64 above 4G") c) Test results with old kexec-tools with old and latest kernels: 1. Old kexec-tools can not build with modern toolchain anymore, I built it in a RHEL6 vm. 2. 2.0.0 kexec-tools does not work with the latest kernel even with memory under 896M and gives an error: "ELF core (kcore) parse failed" For that it needs below kexec-tools fix: ed15ba1b9977 ("build_mem_phdrs(): check if p_paddr is invalid") 3. Even with patched kexec-tools which fixes 2), it still needs some other fixes to work correctly for KASLR-enabled kernels. So the situation is: * Old kexec-tools is already broken with latest kernels. * We can not keep these limitations forever just for compatibility with very old kexec-tools. * If one must use old tools then he/she can choose crashkernel=X@Y. * People have reported bugs where crashkernel=384M failed because KASLR makes the 0-896M space sparse. * Crashkernel can reserve in low or high area, it is natural to understand low as memory under 4G. Hence drop the 896M limitation and change crashkernel low reservation to reserve under 4G by default. Signed-off-by: Dave Young <dyoung@redhat.com> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Ingo Molnar <mingo@kernel.org> Acked-by: Baoquan He <bhe@redhat.com> Cc: Dave Hansen <dave.hansen@intel.com> Cc: David Howells <dhowells@redhat.com> Cc: Eric Biederman <ebiederm@xmission.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Juergen Gross <jgross@suse.com> Cc: Petr Tesarik <ptesarik@suse.cz> Cc: piliu@redhat.com Cc: Ram Pai <linuxram@us.ibm.com> Cc: Sinan Kaya <okaya@codeaurora.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: vgoyal@redhat.com Cc: x86-ml <x86@kernel.org> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Zhimin Gu <kookoo.gu@intel.com> Link: https://lkml.kernel.org/r/20190421035058.943630505@redhat.com
2019-04-22csky/syscall_trace: Fixup return processing flowGuo Ren
The function tracehook_report_syscall_entry's return value is __must_check attribute. We should add return processing flow in ptrace.c and set the syscall number to -1 when failed just like riscv's. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Arnd Bergmann <arnd@arndb.de>
2019-04-22csky: Fixup compile warningGuo Ren
The function of __va() will return "void *", but the pgd_base is unsigned long. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Arnd Bergmann <arnd@arndb.de>
2019-04-22csky: Add support for perf registers samplingMao Han
This patch implements the perf registers sampling and validation API for csky arch. The valid registers and their register ID are defined in perf_regs.h. Perf tool can backtrace in userspace with unwind library and the registers/user stack dump support. Signed-off-by: Mao Han <han_mao@c-sky.com> Signed-off-by: Guo Ren <ren_guo@c-sky.com>
2019-04-22csky: add page fault perf event supportMao Han
This patch add support for page fault count, major fault count and minorfault count. Without this patch page faults are not sampled for perf event. Performance counter stats for '/usr/lib/perf-test/callchain_test': 0 page-faults # 0.000 K/sec Signed-off-by: Mao Han <han_mao@c-sky.com> Signed-off-by: Guo Ren <ren_guo@c-sky.com>
2019-04-22csky: Use va_pa_offset instead of phys_offsetGuo Ren
The name of phys_offset is so common for global export and it may conflict with some local name. So change phys_offset to va_pa_offset which also used by riscv. Also use __pa() and __va() instead of using phys_offset directly. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Arnd Bergmann <arnd@arndb.de>
2019-04-22csky: Support vmlinux bootup with MMU offGuo Ren
Modify SETUP_MMU macro to fit on both MMU-on or MMU-off enviornment and vmlinux could bootup from MMU off enviornment for some cases. Unify the style of _start and _start_smp_secondary in head.S to make head.S looks more concise and easy to understand. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Arnd Bergmann <arnd@arndb.de>
2019-04-22csky: Add perf_arch_fetch_caller_regs supportMao Han
In trace events as tracepoints context are not able to be retrieve with task_pt_regs. Without arch caller regs support the pt_regs context will be all zero, perf can not parsing the callchain and resolving the symbols correctly, some time will even get into deadlock while handling the page fault, eg: perf kmem —page record ls Changelog - Add test case cmd in comment - Use regs_fp(regs) which is defined in abi/regdef.h Signed-off-by: Mao Han <han_mao@c-sky.com> Signed-off-by: Guo Ren <guoren@kernel.org>
2019-04-22csky: Fixup wrong update_mmu_cache implementationGuo Ren
In our stress test, we found some crash problem caused by: if (!(vma->vm_flags & VM_EXEC)) return; in update_mmu_cache(). Seems current update_mmu_cache implementation is wrong and we retread to the conservative implementation. Also the usage of kmap_atomic in update_mmu_cache is risky, page-virtual may be scheduled out and changed, so we must use preempt_disable & pagefault_disable which is called by kmap_atomic(). Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Arnd Bergmann <arnd@arndb.de>