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2019-04-22csky: Support dynamic start physical addressGuo Ren
Before this patch csky-linux need CONFIG_RAM_BASE to determine start physical address. Now we use phys_offset variable to replace the macro of PHYS_OFFSET and we setup phys_offset with real physical address which is determined during startup in head.S. With this patch we needn't re-compile kernel for different start physical address. ie: 0x0 / 0xc0000000 start physical address could use the same vmlinux, be care different start address must be 512MB aligned. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Arnd Bergmann <arnd@arndb.de>
2019-04-22csky: Reconstruct signal processingGuo Ren
Linux kernel has provided some apis for arch signal's implementation. For example: restore_saved_sigmask() set_current_blocked() restore_altstack() But in last version of csky signal.c didn't use them and some codes are confusing, so reconstruct signal.c with reference to riscv's code. Now csky signal.c implementation are very close to riscv and we can get the following benefits: - Clear code structure - The signal code of riscv and csky can be reviewed together - Promoting the unification of arch's signal implementation Also modified the related code in entry.S Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Arnd Bergmann <arnd@arndb.de>
2019-04-22csky: Use in_syscall & forget_syscall instead of r11_sigGuo Ren
We could use regs->sr 16-24 bits to detect syscall: VEC_TRAP0 and r11_sig is no necessary for current implementation. In this patch, we implement the in_syscall and forget_syscall which are inspired from arm & nds32, but csky pt_regs has no syscall_num element and we just set zero to regs->sr's vector-bits-field instead. For ret_from_fork, current task was forked from parent which is in syscall progress and its regs->sr has been already setted with VEC_TRAP0. See: arch/csky/kernel/process.c: copy_thread() Signed-off-by: Guo Ren <ren_guo@c-sky.com>
2019-04-22csky: Add non-uapi asm/ptrace.h namespaceGuo Ren
Move #ifdef __KERNEL__ code in the uapi namespace to non-uapi include/asm/ptrace.h namespace and remove #ifdef __KERNEL__ in include/asm/ptrace.h. Seperate ptrace.h in uapi and non-uapi is more common and clear. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Dmitry V. Levin <ldv@altlinux.org>
2019-04-22csky: mm/fault.c: Remove duplicate headerJagadeesh Pagadala
Remove duplicate header which is included twice. Signed-off-by: Jagadeesh Pagadala <jagdsh.linux@gmail.com> Signed-off-by: Guo Ren <ren_guo@c-sky.com>
2019-04-22csky: remove redundant generic-yMasahiro Yamada
Since commit 7cbbbb8bc297 ("kbuild: warn redundant generic-y"), redundant generic-y is reported. I missed to delete this one. scripts/Makefile.asm-generic:25: redundant generic-y found in arch/csky/include/asm/Kbuild: ftrace.h In this case, csky-specific implementation exists in arch/csky/include/asm/ftrace.h Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Guo Ren <ren_guo@c-sky.com>
2019-04-22csky: Update syscall_trace_enter/exit implementationGuo Ren
Previous syscall_trace implementation couldn't support AUDITSYSCALL and SYSCALL_TRACEPOINTS. Now we redesign it to support audit_syscall and syscall_tracepoints just like other archs'. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Dmitry V. Levin <ldv@altlinux.org> Cc: Arnd Bergmann <arnd@arndb.de>
2019-04-22csky: Add perf callchain supportMao Han
This patch add support for perf callchain sampling on csky platform. As fp is used to unwind the stack, the program being sampled and the C library need to be compiled with -mbacktrace for user callchains, kernel callchains require CONFIG_STACKTRACE = y. Changelog: - Coding convention with Christoph's advice for riscv's. Signed-off-by: Mao Han <han_mao@c-sky.com> Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Christoph Hellwig <hch@infradead.org>
2019-04-22csky/ftrace: Add dynamic function tracer (include graph tracer)Guo Ren
Support dynamic ftrace including dynamic graph tracer. Gcc-csky with -pg will produce call site in every function prologue and we can use these call site to hook trace function. gcc with -pg origin call site: push lr jbsr _mcount nop32 nop32 If the (callee - caller)'s offset is in range of bsr instruction, we'll modify code with: push lr bsr _mcount nop32 nop32 Else if the (callee - caller)'s offset is out of bsr instrunction, we'll modify code with: push lr movih r26, ... ori r26, ... jsr r26 (r26 is reserved for jsr link reg in csky abiv2 spec.) Signed-off-by: Guo Ren <ren_guo@c-sky.com>
2019-04-22csky: Fixup vdsp&fpu issues in kernelGuo Ren
This fixup is continue to commit 35ff802af1c4 (csky: fixup remove vdsp implement for kernel.) and in that patch I didn't finish the job. We must forbid gcc to generate any vdsp & fpu instructions and remove vdsp asm in memmove.S. eg: For GCC it's -mcpu=ck860 and For AS it's -Wa,-mcpu=ck860fv Signed-off-by: Guo Ren <ren_guo@c-sky.com>
2019-04-22arm64: dts: lx2160a: add cpu idle supportRan Wang
lx2160a supports pw20 which could help save more power during cpu is dile. It needs system firmware support via PSCI. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-22arm64: dts: imx8mq: fix GPU clock frequencyLucas Stach
v2 of "clk: imx: Refactor entire sccg pll clk" dropped the implicit reparenting of the PLL output from the bypass clock to the real PLL. The commit introducing the GPU node had only been tested against v1 of this patch. Without an explicit reparent to the real PLL the GPU is stuck at the bypass clock rate of 25MHz, serverly hampering performance. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-22arm64: dts: fsl: imx8mq-evk: link regulator to GPU domainLucas Stach
Link the SW1AB regulator to the GPU domain, so that it gets enabled when needed. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-22arm64: dts: imx8mm: Add cpufreq propertiesLeonard Crestez
This is very similar to imx8mq cpufreq-dt support. Operating points are from datasheet: https://www.nxp.com/docs/en/data-sheet/IMX8MMCEC.pdf Higher opps were omitted (just like imx8mq) because it requires checking speed grade from OCOTP fuses. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-22arm64: dts: imx8qxp-mek: Add i2c1 with pca9646Leonard Crestez
Add an initial description of the i2c1 bus with a pca9646 i2c switch and various gpio expanders and sensors behind that. Only add the sensors which already have upstream drivers. According to the datasheet the pca9646 is software compatible with pca9546 so no driver changes should be required. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-22arm64: dts: imx8qxp: enable scu general irq channelAnson Huang
On i.MX8QXP, SCU uses MU1 general interrupt channel #3 to notify user for IRQs of RTC alarm, thermal alarm and WDOG etc., mailbox RX doorbell mode is used for this function, this patch adds support for it. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-22arm64: dts: imx8mq: add GPU nodeLucas Stach
This enables the Vivante GC7000L GPU on the i.MX8MQ SoC. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Guido Günther <agx@sigxcpu.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-22arm64: dts: imx: add Zii Ultra board supportLucas Stach
The Zii Ultra design, also known as RDU3, is the i.MX8M based successor to the the i.MX6 based RDU2. This adds the basic board support for all components which are supported by the upstream kernel at this time. The board comes in 2 different versions, called RMB3 and Zest, which are derived from the same design, but have different layouts and a few small differences in the populated components. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-22ARM: dts: vf610-zii-dev-rev-b: Specify CS as GPIO_ACTIVE_LOW in spi0Andrey Smirnov
Specify CS as GPIO_ACTIVE_LOW in spi0 to fix the following warning: m25p128@0 enforce active low on chipselect handle Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Chris Healy <cphealy@gmail.com> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Fabio Estevam <festevam@gmail.com> Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-22ARM: dts: vf610-zii-dev: Mark i2c0 SCL as GPIO_OPEN_DRAINAndrey Smirnov
Mark i2c0 SCL as GPIO_OPEN_DRAIN to fix the following warning: gpio-36 (scl): enforced open drain please flag it properly in DT/ACPI DSDT/board file Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Chris Healy <cphealy@gmail.com> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Fabio Estevam <festevam@gmail.com> Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-22ARM: dts: Add support for ZII i.MX7 RPU2 boardAndrey Smirnov
Add support for ZII's i.MX7 based Remote Peripheral Unit 2 (RPU2) board. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Chris Healy <cphealy@gmail.com> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Fabio Estevam <festevam@gmail.com> Cc: Rob Herring <robh@kernel.org> Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-22ARM: dts: bugfix tqma7 soft reset issueBruno Thomsen
Running reboot command on the TQMa7 board would just hang infinite at the end of the system shutdown process. Handling of i.MX7 errata e10574: Watchdog: A watchdog timeout or software trigger will not reset the SOC. Moved pinctrl from common mba7 to common tqma7 dtsi as it improves readability of errata handling. Most integrators of this SoM will likely use the development board as inspiration for handling this SoC issue. Signed-off-by: Bruno Thomsen <bruno.thomsen@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-21x86/fault: Make fault messages more succinctBorislav Petkov
So we are going to be staring at those in the next years, let's make them more succinct. In particular: - change "address = " to "address: " - "-privileged" reads funny. It should be simply "kernel" or "user" - "from kernel code" reads funny too. "kernel mode" or "user mode" is more natural. An actual example says more than 1000 words, of course: [ 0.248370] BUG: kernel NULL pointer dereference, address: 00000000000005b8 [ 0.249120] #PF: supervisor write access in kernel mode [ 0.249717] #PF: error_code(0x0002) - not-present page Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: dave.hansen@linux.intel.com Cc: luto@kernel.org Cc: riel@surriel.com Cc: sean.j.christopherson@intel.com Cc: yu-cheng.yu@intel.com Link: http://lkml.kernel.org/r/20190421183524.GC6048@zn.tnic Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-04-21arm64: dts: clearfog-gt-8k: add wlan_disable signal hogThomas Schreiber
There is currently no DT binding for GPIO rfkill signals. To make mini-PCIe attached WiFi devices work, use gpio-hog to hold the wlan_disable signal de-asserted. Signed-off-by: Thomas Schreiber <tschreibe@gmail.com> [baruch: add pinctrl node; rename tag] Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-04-21ARM: mvebu: kirkwood: remove error message when retrieving mac addressChris Packham
Kirkwood has always had the ability to retrieve the local-mac-address from the hardware (usually this was configured by the bootloader). This is particularly useful when dealing with a legacy non-DT aware bootloader. The "error" message just indicated that the board used an old bootloader and in many cases users can't do anything about this. The message probably should have been pr_info() to inform the user that the kernel has been helpful but rather than than let's remove it entirely to make the kernel less noisy. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-04-21ARM: dts: armada-38x: add interrupts for watchdogChris Packham
The first interrupt is for the regular watchdog timeout. Normally the RSTOUT line will trigger a reset before this interrupt fires but on systems with a non-standard reset it may still trigger. The second interrupt is for a timer1 which is used as a pre-timeout for the watchdog. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-04-21arm64: defconfig: enable mv-xor driverThomas Petazzoni
The mv-xor DMA driver is used for the XOR engine found in the ARM64 Marvell Armada 3720 SoC, so it makes sense to have it enabled in the arm64 defconfig. A recent boot-time regression was found in mv-xor, which would have been more easily noticed with this driver enabled by default. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Cc: Robin Murphy <robin.murphy@arm.com> Cc: John David Anglin <dave.anglin@bell.net> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-04-21powerpc/mm: Fix section mismatch warningAneesh Kumar K.V
This patch fix the below section mismatch warnings. WARNING: vmlinux.o(.text+0x2d1f44): Section mismatch in reference from the function devm_memremap_pages_release() to the function .meminit.text:arch_remove_memory() WARNING: vmlinux.o(.text+0x2d265c): Section mismatch in reference from the function devm_memremap_pages() to the function .meminit.text:arch_add_memory() Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-04-21powerpc/mm/hash: Rename KERNEL_REGION_ID to LINEAR_MAP_REGION_IDAneesh Kumar K.V
The region actually point to linear map. Rename the #define to clarify thati. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-04-21powerpc/mm: Print kernel map details to dmesgAneesh Kumar K.V
This helps in debugging. We can look at the dmesg to find out different kernel mapping details. On 4K config this shows kernel vmalloc start = 0xc000100000000000 kernel IO start = 0xc000200000000000 kernel vmemmap start = 0xc000300000000000 On 64K config: kernel vmalloc start = 0xc008000000000000 kernel IO start = 0xc00a000000000000 kernel vmemmap start = 0xc00c000000000000 Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-04-21powerpc/mm/hash: Simplify the region id calculation.Aneesh Kumar K.V
This reduces multiple comparisons in get_region_id to a bit shift operation. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-04-21powerpc/mm: Drop the unnecessary region checkAneesh Kumar K.V
All the regions are now mapped with top nibble 0xc. Hence the region id check is not needed for virt_addr_valid() Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-04-21powerpc/mm: Validate address values against different region limitsAneesh Kumar K.V
This adds an explicit check in various functions. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-04-21powerpc/mm/hash64: Map all the kernel regions in the same 0xc rangeAneesh Kumar K.V
This patch maps vmalloc, IO and vmemap regions in the 0xc address range instead of the current 0xd and 0xf range. This brings the mapping closer to radix translation mode. With hash 64K page size each of this region is 512TB whereas with 4K config we are limited by the max page table range of 64TB and hence there regions are of 16TB size. The kernel mapping is now: On 4K hash kernel_region_map_size = 16TB kernel vmalloc start = 0xc000100000000000 kernel IO start = 0xc000200000000000 kernel vmemmap start = 0xc000300000000000 64K hash, 64K radix and 4k radix: kernel_region_map_size = 512TB kernel vmalloc start = 0xc008000000000000 kernel IO start = 0xc00a000000000000 kernel vmemmap start = 0xc00c000000000000 Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-04-21powerpc/mm/hash64: Add a variable to track the end of IO mappingAneesh Kumar K.V
This makes it easy to update the region mapping in the later patch Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-04-21powerc/mm/hash: Reduce hash_mm_context sizeAneesh Kumar K.V
Allocate subpage protect related variables only if we use the feature. This helps in reducing the hash related mm context struct by around 4K Before the patch sizeof(struct hash_mm_context) = 8288 After the patch sizeof(struct hash_mm_context) = 4160 Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-04-21powerpc/mm: Reduce memory usage for mm_context_t for radixAneesh Kumar K.V
Currently, our mm_context_t on book3s64 include all hash specific context details like slice mask and subpage protection details. We can skip allocating these with radix translation. This will help us to save 8K per mm_context with radix translation. With the patch applied we have sizeof(mm_context_t) = 136 sizeof(struct hash_mm_context) = 8288 Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-04-21powerpc/mm: Move slb_addr_linit to early_init_mmuAneesh Kumar K.V
Avoid #ifdef in generic code. Also enables us to do this specific to MMU translation mode on book3s64 Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-04-21powerpc/mm: Add helpers for accessing hash translation related variablesAneesh Kumar K.V
We want to switch to allocating them runtime only when hash translation is enabled. Add helpers so that both book3s and nohash can be adapted to upcoming change easily. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-04-21powerpc/mm: Remove PPC_MM_SLICES #ifdef for book3s64Aneesh Kumar K.V
Book3s64 always have PPC_MM_SLICES enabled. So remove the unncessary #ifdef Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-04-21powerpc/mm: Fix build error with FLATMEM book3s64 configAneesh Kumar K.V
The current value of MAX_PHYSMEM_BITS cannot work with 32 bit configs. We used to have MAX_PHYSMEM_BITS not defined without SPARSEMEM and 32 bit configs never expected a value to be set for MAX_PHYSMEM_BITS. Dependent code such as zsmalloc derived the right values based on other fields. Instead of finding a value that works with different configs, use new values only for book3s_64. For 64 bit booke, use the definition of MAX_PHYSMEM_BITS as per commit a7df61a0e2b6 ("[PATCH] ppc64: Increase sparsemem defaults") That change was done in 2005 and hopefully will work with book3e 64. Fixes: 8bc086899816 ("powerpc/mm: Only define MAX_PHYSMEM_BITS in SPARSEMEM configurations") Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-04-21powerpc/32s: Implement Kernel Userspace Access ProtectionChristophe Leroy
This patch implements Kernel Userspace Access Protection for book3s/32. Due to limitations of the processor page protection capabilities, the protection is only against writing. read protection cannot be achieved using page protection. The previous patch modifies the page protection so that RW user pages are RW for Key 0 and RO for Key 1, and it sets Key 0 for both user and kernel. This patch changes userspace segment registers are set to Ku 0 and Ks 1. When kernel needs to write to RW pages, the associated segment register is then changed to Ks 0 in order to allow write access to the kernel. In order to avoid having the read all segment registers when locking/unlocking the access, some data is kept in the thread_struct and saved on stack on exceptions. The field identifies both the first unlocked segment and the first segment following the last unlocked one. When no segment is unlocked, it contains value 0. As the hash_page() function is not able to easily determine if a protfault is due to a bad kernel access to userspace, protfaults need to be handled by handle_page_fault when KUAP is set. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> [mpe: Drop allow_read/write_to/from_user() as they're now in kup.h, and adapt allow_user_access() to do nothing when to == NULL] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-04-21powerpc/32s: Prepare Kernel Userspace Access ProtectionChristophe Leroy
This patch prepares Kernel Userspace Access Protection for book3s/32. Due to limitations of the processor page protection capabilities, the protection is only against writing. read protection cannot be achieved using page protection. book3s/32 provides the following values for PP bits: PP00 provides RW for Key 0 and NA for Key 1 PP01 provides RW for Key 0 and RO for Key 1 PP10 provides RW for all PP11 provides RO for all Today PP10 is used for RW pages and PP11 for RO pages, and user segment register's Kp and Ks are set to 1. This patch modifies page protection to use PP01 for RW pages and sets user segment registers to Kp 0 and Ks 0. This will allow to setup Userspace write access protection by settng Ks to 1 in the following patch. Kernel space segment registers remain unchanged. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-04-21powerpc/32s: Implement Kernel Userspace Execution Prevention.Christophe Leroy
To implement Kernel Userspace Execution Prevention, this patch sets NX bit on all user segments on kernel entry and clears NX bit on all user segments on kernel exit. Note that powerpc 601 doesn't have the NX bit, so KUEP will not work on it. A warning is displayed at startup. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-04-21powerpc/8xx: Add Kernel Userspace Access ProtectionChristophe Leroy
This patch adds Kernel Userspace Access Protection on the 8xx. When a page is RO or RW, it is set RO or RW for Key 0 and NA for Key 1. Up to now, the User group is defined with Key 0 for both User and Supervisor. By changing the group to Key 0 for User and Key 1 for Supervisor, this patch prevents the Kernel from being able to access user data. At exception entry, the kernel saves SPRN_MD_AP in the regs struct, and reapply the protection. At exception exit it restores SPRN_MD_AP with the value saved on exception entry. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> [mpe: Drop allow_read/write_to/from_user() as they're now in kup.h] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-04-21powerpc/8xx: Add Kernel Userspace Execution PreventionChristophe Leroy
This patch adds Kernel Userspace Execution Prevention on the 8xx. When a page is Executable, it is set Executable for Key 0 and NX for Key 1. Up to now, the User group is defined with Key 0 for both User and Supervisor. By changing the group to Key 0 for User and Key 1 for Supervisor, this patch prevents the Kernel from being able to execute user code. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-04-21powerpc/8xx: Only define APG0 and APG1Christophe Leroy
Since the 8xx implements hardware page table walk assistance, the PGD entries always point to a 4k aligned page, so the 2 upper bits of the APG are not clobbered anymore and remain 0. Therefore only APG0 and APG1 are used and need a definition. We set the other APG to the lowest permission level. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-04-21powerpc/32: Prepare for Kernel Userspace Access ProtectionChristophe Leroy
This patch adds ASM macros for saving, restoring and checking the KUAP state, and modifies setup_32 to call them on exceptions from kernel. The macros are defined as empty by default for when CONFIG_PPC_KUAP is not selected and/or for platforms which don't handle (yet) KUAP. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-04-21powerpc/32: Remove MSR_PR test when returning from syscallChristophe Leroy
syscalls are from user only, so we can account time without checking whether returning to kernel or user as it will only be user. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-04-21powerpc/mm: Detect bad KUAP faultsMichael Ellerman
When KUAP is enabled we have logic to detect page faults that occur outside of a valid user access region and are blocked by the AMR. What we don't have at the moment is logic to detect a fault *within* a valid user access region, that has been incorrectly blocked by AMR. This is not meant to ever happen, but it can if we incorrectly save/restore the AMR, or if the AMR was overwritten for some other reason. Currently if that happens we assume it's just a regular fault that will be corrected by handling the fault normally, so we just return. But there is nothing the fault handling code can do to fix it, so the fault just happens again and we spin forever, leading to soft lockups. So add some logic to detect that case and WARN() if we ever see it. Arguably it should be a BUG(), but it's more polite to fail the access and let the kernel continue, rather than taking down the box. There should be no data integrity issue with failing the fault rather than BUG'ing, as we're just going to disallow an access that should have been allowed. To make the code a little easier to follow, unroll the condition at the end of bad_kernel_fault() and comment each case, before adding the call to bad_kuap_fault(). Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>